digital design and fabrication

1 Trends and Projections for the Future of Scaling and Future Integration Trends Hiroshi Iwai and Shun-ichiro Ohmi ...1-1 2 CMOS Circuits 2.1 VLSI Circuits Eugene John .... Now CMOS tech

The Computer Engineering

Handbook Second Edition

Edited by

Vojin G Oklobdzija

Digital Design and Fabrication Digital Systems and Applications

Computer Engineering Series

Series Editor: Vojin G Oklobdzija

Coding and Signal Processing for

Magnetic Recording Systems

Edited by Bane Vasic and Erozan M Kurtas

The Computer Engineering Handbook

Second Edition

Edited by Vojin G Oklobdzija

Digital Image Sequence Processing,

Compression, and Analysis

Edited by Todd R Reed

Low-Power Electronics Design

Edited by Christian Piguet

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Library of Congress Cataloging-in-Publication Data

Digital design and fabrication / Vojin Oklobdzija.

p cm.

Includes bibliographical references and index.

ISBN 978-0-8493-8602-2 (alk paper)

1 Computer engineering 2 Production engineering I Oklobdzija, Vojin G II Title.

Purpose and Background

Computer engineering is a vast field spanning many aspects of hardware and software; thus, it is difficult

to cover it in a single book It is also rapidly changing requiring constant updating as some aspects of itmay become obsolete In this book, we attempt to capture the long lasting fundamentals as well as thenew trends, directions, and developments This book could easily fill thousands of pages We are awarethat some areas were not given sufficient attention and some others were not covered at all We plan tocover these missing parts as well as more specialized topics in more details with new books under thecomputer engineering series and new editions of the current book We believe that the areas covered bythis new edition are covered very well because they are written by specialists, recognized as leadingexperts in their fields

Organization

This book contains five sections First, we start with the fabrication and technology that have been adriving factor for the electronic industry No sector of the industry has experienced such tremendousgrowth and advances as the semiconductor industry did in the past 30 years This progress has surpassedwhat we thought to be possible, and limits that were once thought of as fundamental were broken severaltimes This is best seen in the development of semiconductor memories, described in Section II.When the first 256-kbit DRAM chips were introduced, the ‘‘alpha particle scare’’ (the problem encoun-tered with alpha particles discharging the memory cell) predicted that radiation effects would limitfurther scaling in dimensions of memory chips Twenty years later, the industry was producing 256-MbitDRAM chips—a thousand times improvement in density—and we see no limit to further scaling even at4GB memory capacity In fact, the memory capacity has been tripling every 2 years while the number oftransistors in the processor chip has been doubling every 2 years

Important design techniques are described in two separate sections Section III addresses designtechniques used to create modern computer systems The most important design issues starting fromtiming and clocking, PLL and DLL design and ending with high-speed computer arithmetic and high-frequency design are described in this section Section IV deals with power consumed by the system.Power consumption is becoming the most important issue as computers are starting to penetrate largeconsumer product markets, and in several cases low-power consumption is more important than theperformance that the system can deliver

Finally, reliability and testability of computer systems are described in Section V

v

Locating Your Topic

Several avenues are available to access desired information A complete table of contents is presented atthe front of the book Each of the sections is preceded with an individual table of contents Finally, eachchapter begins with its own table of contents Each contributed chapter contains comprehensivereferences Some of them contain a ‘‘To Probe Further’’ section, in which a general discussion of varioussources such as books, journals, magazines, and periodicals is located To be in tune with the moderntimes, some of the authors have also included Web pointers to valuable resources and information Wehope our readers will find this to be appropriate and of much use

A subject index has been compiled to provide a means of accessing information It can also be used

to locate definitions The page on which the definition appears for each key defining term is given inthe index

This book is designed to provide answers to most inquiries and to direct inquirers to further sourcesand references We trust that it will meet the needs of our readership

Acknowledgments

The value of this book is based entirely on the work of people who are regarded as top experts in theirrespective field and their excellent contributions I am grateful to them They contributed their valuabletime without compensation and with the sole motivation to provide learning material and helpenhance the profession I would like to thank Saburo Muroga, who provided editorial advice, reviewedthe content of the book, made numerous suggestions, and encouraged me I am indebted to him as well

as to other members of the advisory board I would like to thank my colleague and friend Richard Dorffor asking me to edit this book and trusting me with this project Kristen Maus worked tirelessly on thefirst edition of this book and so did Nora Konopka of CRC Press I am also grateful to the editorial staff

of Taylor & Francis, Theresa Delforn and Allison Shatkin in particular, for all the help and hours spent

on improving many aspects of this book I am particularly indebted to Suryakala Arulprakasam and herstaff for a superb job of editing, which has substantially improved this book over the previous one

Vojin G OklobdzijaBerkeley, California

vi

Vojin G Oklobdzija is a fellow of the Institute of Electrical andElectronics Engineers and distinguished lecturer of the IEEE Solid-State Circuits and IEEE Circuits and Systems Societies He received hisPhD and MSc from the University of California, Los Angeles in 1978and 1982, as well as a Diplom-Ingenieur (MScEE) from the ElectricalEngineering Department, University of Belgrade, Yugoslavia in 1971.From 1982 to 1991, he was at the IBM T.J Watson Research Center

in New York where he made contributions to the development ofRISC architecture and processors In the course of this work heobtained a patent on register-renaming, which enabled an entirenew generation of superscalar processors

From 1988 to 1990, he was a visiting faculty at the University of California, Berkeley, while on leavefrom IBM Since 1991, Professor Oklobdzija has held various consulting positions He was a consultant

to Sun Microsystems Laboratories, AT&T Bell Laboratories, Hitachi Research Laboratories, FujitsuLaboratories, Samsung, Sony, Silicon Systems=Texas Instruments Inc., and Siemens Corp., where hewas also the principal architect of the Siemens=Infineon’s TriCore processor

In 1996, he incorporated Integration Corp., which delivered several successful processor and tion processor designs

encryp-Professor Oklobdzija has held various academic appointments, in addition to the one at the University

of California In 1991, as a Fulbright professor, he helped to develop programs at universities in SouthAmerica From 1996 to 1998, he taught courses in Silicon Valley through the University of California,Berkeley Extension, and at Hewlett–Packard He was visiting professor in Korea, EPFL in Switzerland andSydney, Australia Currently he is Emeritus professor at the University of California and Researchprofessor at the University of Texas at Dallas

He holds 14 U.S and 18 international patents in the area of computer architecture and design.Professor Oklobdzija is a member of the American Association for the Advancement of Science, andthe American Association of University Professors

He serves as associate editor for the IEEE Transactions on Circuits and Systems II; IEEE Micro; andJournal of VLSI Signal Processing; International Symposium on Low-Power Electronics, ISLPED; ComputerArithmetic Symposium, ARITH, and numerous other conference committees He served as associateeditor of the IEEE Transactions on Computers (2001–2005), IEEE Transactions on Very Large Scale ofIntegration (VLSI) Systems (1995–2003), the ISSCC Digital Program Committee (1996–2003), and thefirst Asian Solid-State Circuits Conference, A-SSCC in 2005 He was a general chair of the 13thSymposium on Computer Arithmetic in 1997

vii

He has published over 150 papers in the areas of circuits and technology, computer arithmetic, andcomputer architecture, and has given over 150 invited talks and short courses in the United States,Europe, Latin America, Australia, China, and Japan.

viii

Takayasu SakuraiUniversity of TokyoTokyo, JapanAlan SmithUniversity of California at BerkeleyBerkeley, California

Ian YoungIntel CorporationHillsboro, Oregon

ix

University of California at Los Angeles

Los Angeles, California

Vivek De

Intel Corporation

Hillsboro, Oregon

Gensuke GotoYamagata UniversityYamagata, JapanJames O HamblenGeorgia Institute of TechnologyAtlanta, Georgia

Hiroshi IwaiTokyo Institute of TechnologyYokohama, Japan

Roozbeh JafariUniversity of Texas at DallasDallas, Texas

Farzin Michael JahedToshiba America Electronic ComponentsIrvine, California

Shahram JamshidiIntel CorporationSanta Clara, CaliforniaEugene John

University of Texas at San AntonioSan Antonio, Texas

Yuichi KadoNIT Telecommunications TechnologyLaboratories

Kanagawa, JapanJames KaoIntel CorporationHillsboro, Oregon

xi

Santa Clara, California

John George Maneatis

True Circuits, Inc

Los Altos, California

Dejan Markovic´

University of California at Los Angeles

Los Angeles, California

Tammara Massey

University of California at Los Angeles

Los Angeles, California

University of California at Los Angeles

Los Angeles, California

Rakesh PatelIntel CorporationSanta Clara, California

Christian PiguetCentre Suisse d’Electronique et de MicrotechniqueNeuchatel, Switzerland

Kaushik RoyPurdue UniversityWest Lafayette, Indiana

Majid SarrafzadehUniversity of California at Los AngelesLos Angeles, California

Katsunori SenoSony CorporationTokyo, Japan

Kinyip SitIntel CorporationSanta Clara, California

Hendrawan SoelemanPurdue UniversityWest Lafayette, Indiana

Dinesh SomasekharIntel CorporationHillsboro, Oregon

Earl E Swartzlander, Jr

University of Texas at AustinAustin, Texas

xii

Tokyo, JapanYibin YeIntel CorporationHillsboro, Oregon

xiii

1 Trends and Projections for the Future of Scaling and Future Integration

Trends Hiroshi Iwai and Shun-ichiro Ohmi 1-1

2 CMOS Circuits

2.1 VLSI Circuits Eugene John 2-1

3 High-Speed, Low-Power Emitter Coupled Logic Circuits Tadahiro Kuroda 3-1

4 Price-Performance of Computer Technology John C McCallum 4-1

5 Semiconductor Memory Circuits Eugene John 5-1

6 Semiconductor Storage Devices in Computing and Consumer

Applications Farzin Michael Jahed 6-1

7 Timing and Clocking

xv

7.2 Latches and Flip-Flops Fabian Klass 7-33

8 Multiple-Valued Logic Circuits K Wayne Current 8-1

9 FPGAs for Rapid Prototyping James O Hamblen 9-1

10 Issues in High-Frequency Processor Design Kevin J Nowka 10-1

11 Computer Arithmetic

12 Design for Low Power Hai Li, Rakesh Patel, Kinyip Sit, Zhenyu Tang,

and Shahram Jamshidi 12-1

13 Low-Power Circuit Technologies Masayuki Miyazaki 13-1

14 Techniques for Leakage Power Reduction Vivek De, Ali Keshavarzi,

Siva Narendra, Dinesh Somasekhar, Shekhar Borkar, James Kao, Raj Nair,

and Yibin Ye 14-1

15 Dynamic Voltage Scaling Thomas D Burd 15-1

16 Lightweight Embedded Systems Foad Dabiri, Tammara Massey,

Ani Nahapetian, Majid Sarrafzadeh, and Roozbeh Jafari 16-1

17 Low-Power Design of Systems on Chip Christian Piguet 17-1

18 Implementation-Level Impact on Low-Power Design Katsunori Seno 18-1

19 Accurate Power Estimation of Combinational CMOS Digital Circuits

Hendrawan Soeleman and Kaushik Roy 19-1

20 Clock-Powered CMOS for Energy-Efficient Computing

Nestoras Tzartzanis and William Athas 20-1

xvi

SECTION V Testing and Design for Testability

21 System-on-Chip (SoC) Testing: Current Practices and Challenges

for Tomorrow R Chandramouli 21-1

22 Test Technology for Sequential Circuits H.T Vierhaus

and Zoran Stamenkovic´ 22-1

23 Scan Testing Chouki Aktouf 23-1

24 Computer-Aided Analysis and Forecast of Integrated Circuit Yield

Zoran Stamenkovic´ and N Stojadinovic´ 24-1

Index I-1

xvii

Fabrication

and Technology

Integration Trends Hiroshi Iwai and Shun-ichiro Ohmi 1-1

Future Prospects

and Yuichi Kado 2-1

I-1

1 Trends and Projections

for the Future

of Scaling and Future Integration Trends

to that of semiconductor technology, especially Silicon LSIs (Large Scale Integrated Circuits) SiliconLSIs provide us high speed=frequency operation of tremendously many functions with low cost, lowpower, small size, small weight, and high reliability In these 30 years, the gate length of the metal oxidesemiconductor field effect transistors (MOSFETs) has reduced 100 times, the density of DRAMincreased 500,000 times, and clock frequency of MPU increased 2,500 times, as shown in Table 1.1.Without such a marvelous progress of LSI technologies, today’s great success in information technologywould not be realized at all

The origin of the concept for solid-state circuit can be traced back to the beginning of last century, as

structure invented a concept of MOSFETs Then, 54 years ago, first transistor (bipolar) was realizedusing germanium In 1960, 2 years after the invention of integrated circuits (IC), the first MOSFET was

materials for electronic circuits It takes, however, more than several years until the Silicon MOSFETevolved to Silicon ICs and further grew up to Silicon LSIs The Silicon LSIs became popular in the

1-1

market from the beginning of 1970s as a 1 kbit DRAM and a 4 bit MPU (microprocessor) In the early1970s, LSIs started by using PMOS technology in which threshold voltage control was easier, but soonthe PMOS was replaced by NMOS, which was suitable for high speed operation It was the middle of1980s when CMOS became the main stream of Silicon LSI technology because of its capability for lowpower consumption Now CMOS technology has realized 512 Mbit DRAMs and 1.7 GHz clock MPUs,and the gate length of MOSFETs in such LSIs becomes as small as 100 nm.

Figure 1.2 shows the cross sections of NMOS LSIs in the early 1970s and those of present CMOS LSIs

basically composed of only five elements: Si, O, Al, B, and P Now, the structure becomes verycomplicated, and so many layers and so many elements have been involved

In the past 30 years, transistors have been miniaturized significantly Thanks to the miniaturization,the number of components and performance of LSIs have increased significantly Figures 1.3 and 1.4show the microphotographs of 1 kbit and 256 Mbit DRAM chips, respectively Individual tinyrectangle units barely recognized in the 16 large rectangle units of the 256 M DRAM correspond to

64 kbit DRAM It can be said that the downsizing of the components has driven the tremendousdevelopment of LSIs

Figure 1.5 shows the past and future trends of the downsizing of MOSFET’s parameters and LSI chipproperties mainly used for high performance MPUs Future trend was taken from ITRS’99 (Inter-national Technology Roadmap for Semiconductors) [2] In order to maintain the continuous progress ofLSIs for future, every parameter has to be shrunk continuously with almost the same rate as before

severe difficulties due to various kinds of expected limitations It was expected that huge effort would berequired in research and development level in order to overcome the difficulties

In this chapter, silicon technology from past to future is reviewed for advanced CMOS LSIs

TABLE 1.1 Past and Current Status of Advanced LSI Products

Year 2001 New Century for Solid-State Circuit

20th C

73 years since the concept of MOSFET

1928, J Lilienfeld, MOSFET patent

54 years since the 1st transistor

1947, J Bardeen, W Bratten, bipolar Tr 43-42 years since the 1st Integrated Circuits

1958, J Kilby, IC

1959, R Noice, Planar Technology

41 years since the 1st Si-MOSFET

1960, D Kahng, Si-MOSFET

38 years since the 1st CMOS

1963, CMOS, by F Wanlass, C.T Sah

31 years since the 1st 1 kbit DRAM (or LSI)

1970 Intel 1103

16 years since CMOS became the major technology

1985, Toshiba 1 Mbit CMOS DRAM FIGURE 1.1 History of LSI in 20th century.

1.2 Downsizing below 0.1 mm

In digital circuit applications, a MOSFET functions as a switch Thus, complete cut-off of leakagecurrent in the ‘‘off ’’ state, and low resistance or high current drive in the ‘‘on’’ state are required Inaddition, small capacitances are required for the switch to rapidly turn on and off When making thegate length small, even in the ‘‘off ’’ state, the space charge region near the drain—the high potentialregion near the drain—touches the source in a deeper place where the gate bias cannot control thepotential, resulting in a leakage current from source to drain via the space charge region, as shown inFig 1.6 This is the well-known, short-channel effect of MOSFETs The short-channel effect is oftenmeasured as the threshold voltage reduction of MOSFETs when it is not severe In order for a MOSFET

Si substrate

Field SiO2

ILD (Interlayer Dielectrics) (SiO2 + BPSG)

Al interconnects Passivation (PSG)

magnification

Poly Si gate electrode

Source/Drain

Layers

Source/Drain diffusion Gate oxide

Si substrate Field oxide Poly Si gate electrode Interlayer dielectrics Aluminum interconnects Passivation

Materials

Si, SiO2BPSG PSG Al Atoms

Si, O, Al,

P, B (H, N, CI)

W via plug

W contact plug CoSi2Low k ILD

Ultra-thin gate SiO2

0.1 mm CMOS LSI in 2001

Large number of layers, Many kinds of materials and atoms Gate SiO2

FIGURE 1.2 Cross-sections of (a) NMOS LSI in 1974 and (b) CMOS LSI in 2001.

Trends and Projections for the Future of Scaling and Future Integration Trends 1-3

to work as a component of an LSI, the capability of switching-off or the suppression of the short-channeleffects is the first priority in the designing of the MOSFETs In other words, the suppression of the short-channel effects limits the downsizing of MOSFETs.

In the ‘‘on’’ state, reduction of the gate length is desirable because it decreases the channel resistance ofMOSFETs However, when the channel resistance becomes as small as source and drain resistance,further improvement in the drain current or the MOSFET performance cannot be expected Moreover,

in the short-channel MOSFET design, the source and drain resistance often tends to even increase inorder to suppress the short-channel effects Thus, it is important to consider ways for reducing the totalresistance of MOSFETs with keeping the suppression of the short-channel effects The capacitances ofMOSFETs usually decreases with the downsizing, but care should be taken when the fringing portion is

dominant or when impurity concentration of the substrate is large in the short-channel transistordesign.

Thus, the suppression of the short-channel effects, with the improvement of the total resistance andcapacitances, are required for the MOSFET downsizing In other words, without the improvements ofthe MOSFET performance, the downsizing becomes almost meaningless even if the short-channel effect

is completely suppressed

To suppress the short-channel effects and thus to secure good switching-off characteristics ofMOSFETs, the scaling method was proposed by Dennard et al [3], where the parameters of MOSFETsare shrunk or increased by the same factor K, as shown in Figs 1.7 and 1.8, resulting in the reduction ofthe space charge region by the same factor K and suppression of the short-channel effects

is reduced to 1=K, the propagation delay time of the circuit reduces to 1=K, because the gate charge

j(mm)

Tox

equivalent (mm )

Id (mA/mm)

Wave length of electron (mm)

Tunneling limit in SiO2 (mm)

Bond length of Si atoms (Physical limit) (mm)

MPU clock frequency (MHz)

MPU chip size?imm

2 ?j

Number

of MPU tra nsistors

?iMtra nsistors?j

MPU maximum current ?imA) DRAM chip size (mm 2 )

ITRS Roadmap (at introduction)

Vdd (V) Drain Gate

FIGURE 1.6 Short channel effect at downsizing.

Trends and Projections for the Future of Scaling and Future Integration Trends 1-5

If the increase in the number of transistors is kept at K2, the power consumption of the LSI—which is

generation because the electric field across the gate oxide would have exceeded 4 MV=cm, which hadbeen regarded as the limitation in terms of TDDB (time-dependent break down)—recently themaximum field is going to be raised to high values, and because hot carrier induced degradationfor the short-channel MOSFETs would have been above the allowable level; however, now, it is not easy

to reduce the supply voltage because of difficulties in reducing the threshold voltage of the MOSFETs.Too small threshold voltage leads to significantly large subthreshold leakage current even at the gate

MOSFETs at the same ratio as the dimension reduction, the supply voltage would have been 0.08 V(¼5 V=60) and the threshold voltage would have been 0.0013 V (¼0.8 V=60), and thus the scalingmethod would have been broken down The voltage higher than that expected from the original

Drain Current: I d→ 1/K Gate area: S g = L g · W g→ 1/K 2

Gate capacitance: C g = a · S g/tox → 1/K Gate charge: Q g = C g · V g→ 1/K 2

Propagation delay time: tpd = a · Q g/d→ 1/K Clock frequency: f = 1/tpd → K

Chip area: Sc: set const → 1 Number of Tr in a chip: n → K 2

X, Y, Z: 1/K V: 1/K Na: K

1/K

1/K 1/K D

V/Na : 1/K

1/K I 0

V I: 1/K

FIGURE 1.8 Ideal scaling method.

scaling is one of the reasons for the increase of the power Increase of the number of transistors in a

decreases by factor 0.7 and the transistor area decreases by factor 0.5 (¼0.7 3 0.7) for every ation, and thus the number of transistors is expected to increase by a factor of 2 In reality, however,the increase cannot wait for the downsizing and the actual increase is by a factor of 4 The insufficientarea for obtaining another factor 2 is earned by increasing the chip area by a factor of 1.5 and further

gener-by extending the area in the vertical direction introducing multilayer interconnects, double polysilicon,and trench=stack DRAM capacitor cells

the direct-tunneling leakage limit of 3 nm The substrate impurity concentration (or the channel

source-substrate and drain-substrate junctions become highly doped pn junctions and act as tunneldiodes Thus, the isolation of source and drains with substrate cannot be maintained The thresholdvoltage has already decreased to 0.3–0.25 V and further reduction causes significant increase insubthreshold leakage current Further reduction of the threshold voltage and thus the further reduction

of the supply voltage are difficult

In 1990s, fortunately, those difficulties were shown to be solved somehow by invention of newtechniques, further modification of the scaling, and some new findings for short gate length MOSFEToperation In the following, examples of the solutions for the front end of line are described In 1993, firstsuccessful operation of sub-50 nm n-MOSFETs was reported [4], as shown in Fig 1.11 In the fabrication

TABLE 1.2 Real Scaling (Research Level)

V th lowering

FIGURE 1.9 Subthreshold leakage current at low Vth.

Trends and Projections for the Future of Scaling and Future Integration Trends 1-7

of the MOSFETs, 40 nm length gate electrodes were realized by introducing resist-thinning techniqueusing oxygen plasma In the scaling, substrate (or channel doping) concentration was not increased anymore, and the gate oxide thickness was not decreased (because it was not believed that MOSFETs withdirect-tunnelling gate leakage operates normally), but instead, decreasing the junction depth moreaggressively (in this case) than ordinary scaling was found to be somehow effective to suppress theshort-channel effect and thus to obtain good operation of sub-50 nm region Thus, 10-nm depth S=Djunction was realized by introduction of solid-phase diffusion by RTA from PSG gate sidewall In 1994, it

[5]—operate quite normally when the gate length is small This is because the gate leakage currentdecreases in proportion with the gate length while the drain current increases in inverse proportion withthe gate length As a result, the gate leakage current can be negligibly small in the normal operation ofMOSFETs The performance of 1.5 nm was record breaking even at low supply voltage

In 1993, it was proposed that ultrathin-epitaxial layer shown in Fig 1.13 is very effective to realizesuper retrograde channel impurity profiles for suppressing the short-channel effects It was confirmedthat 25 nm gate length MOSFETs operate well by using simulation [6] In 1993 and 1995, epitaxialchannel MOSFETs with buried [7] and surface [8] channels, respectively, were fabricated and high drain

FIGURE 1.10 Scaling limitation factor for Si MOSFET below 0.1mm.

FIGURE 1.11 Top view of 40 nm gate length MOSFETs [4].

current drive with excellent suppression of the short-channel effects were experimentally confirmed In

1995, new raised (or elevated) S=D structure was proposed, as shown in Fig 1.14 [10] In the structure,extension portion of the S=D is elevated with self-aligned to the gate electrode by using silicided silicon

reduced In 1991, NiSi salicide were presented for the first time, as shown in Fig 1.15 [10] NiSi has

a monosilicide, silicon consumption during the silicidation is small Silicidation can be accomplished atlow temperature These features are suitable for ultra-shallow junction formation For NiSi salicide,there was no narrow line effect—increase in the sheet resistance in narrow silicide line—and bridging

failure by the formation of silicide path on the gatesidewall between the gate and S=D NiSi-contact resist-

are suitable for reducing the source, drain, and gateresistance for sub-50 nm MOSFETs

The previous discussion provides examples of possiblesolutions, which the authors found in the 1990s for sub-

50 nm gate length generation Also, many solutions havebeen found by others In any case, with the possiblesolutions demonstrated for sub-50 nm generation aswell as the keen competitions among semiconductorchipmakers for high performance, the downsizingtrend or roadmap has been significantly acceleratedsince the late 1990s, as shown in Fig 1.16 The firstroadmap for downsizing was published in 1994 by SIA

NTRS’94 (National Technology Roadmap for ductors) [11]—at that time, the roadmap was not aninternational version On NTRS’94, the clock frequencywas expected to stay at 600 MHz in year 2001 andexpected to exceed 1 GHz in 2007 However, it hasalready reached 2.1 GHz for 2001 in ITRS 2000 [12]

Semicon-In order to realize high clock frequencies, the gatelength reduction was accelerated In fact, in theNTRS’94, gate length was expected to stay at 180 nm

FIGURE 1.12 Cross-sectional TEM image of 1.5 nm gate oxide [5].

Channel ion implantation

Selective Si epitaxial growth

Epitaxial film

MOSFET fabrication

Epitaxial channel

Epi Channel MOSFETs June 1993

FIGURE 1.13 Epitaxial channel [9].

Trends and Projections for the Future of Scaling and Future Integration Trends 1-9

in year 2001 and expected to reach 100 nm only in 2007, but the gate length is 90 nm in 2001 on ITRS

2000, as shown in Fig 1.16b

The real world is much more aggressive As shown in Fig 1.16a, the clock frequency of Intel’s MPUalready reached 1.7 GHz [12] in April 2001, and its roadmap for gate length reduction is unbelievablyaggressive, as shown in Fig 1.16b [13,14] In the roadmap, 30-nm gate length CMOS MPU with 70-nmnode technology is to be sold in the market in year 2005 It is even several years in advance comparedwith the ITRS 2000 prediction

With the increase in clock frequency and the decrease in gate length, together with the increase innumber of transistors in a chip, the tremendous increase in power consumption becomes the main issue

In order to suppress the power consumption, supply voltage should be reduced aggressively, as shown inFig 1.16c In order to maintain high performance under the low supply voltage, gate insulator thicknessshould be reduced very tremendously On NTRS’94, the gate insulator thickness was not expected toexceed 3 nm throughout the period described in the roadmap, but it is already 1.7 nm in products in 2001and expected to be 1.0 nm in 2005 on ITRS’99 and 0.8 nm in Intel’s roadmap, as shown in Fig 1.16d Interms of total gate leakage current of an entire LSI chip for use for mobile cellular phone, 2 nm is alreadytoo thin, in which standby power consumption should be minimized Thus, high K materials, which wereassumed to be introduced after year 2010 at the earliest on NTRS’94, are now very seriously investigated

S 4 D (Silicided Silicon-Sidewall Source and Drain) Structure

FIGURE 1.15 NiSi Salicide [10].

Introduction of new materials is considered not only for the gate insulator, but also almost for everyportion of the CMOS structures More detailed explanations of new technology for future CMOS will begiven in the following sections.

[4,5,14–19] The x-axis in the bottom represents corresponding year of the production to the gate length

[12] It should be noted that most of the published MOSFETs maintain the scaling relationship between

respectively obtained from the published data at the conferences From the data, it can be estimated that

the S=D extension resistance in the small gate length MOSFETs In order to suppress the short-channeleffects, the junction depth of S=D extension needs to be reduced aggressively, resulting in high sheetresistance This should be solved by the raised (or elevated) S=D structures This effect is moresignificantly observed in the operation of an 8-nm gate length EJ-MOSFET [20], as shown inFig 1.19 In the structure, S=D extension consists of inversion layer created by high positive bias applied

on a 2nd gate electrode, which is placed to cover the 8-nm, 1st gate electrode and S=D extension area

2010 0.065

0.35 0.25 0.18 0.13 0.10 0.07

? 1994

3 5 10

1

0.5

Year

0.14 0.100.080

Intel (2000)

(b) 0.01 0.1 1

Thus, reduction of S=D extension resistance will be another limiting factor of CMOS downsizing, which

with sufficient MOSFET performance There was a concern proposed in 1998 that TDDB (Time

gate insulator would be used until the 30 nm gate length generation for high-speed MPUs This is a bigchange of the prediction Until only several years ago, most of the people did not believe the possibility of

1 10 100

: almost within ITRS spec.

: outside of ITRS spec.

Toshiba

Intel Intel (plan)

However, even excellent characteristics of MOSFETs with high reliability was confirmed, total gateleakage current in the entire LSI chip would become the limiting factor It should be noted that

leakage current

used for high end MPUs [26] Furthermore, Intel has announced that total-chip gate leakage current of

can be used for product in 2005 [15]

Total gate leakage current could be minimized by providing plural gate oxide thicknesses in a chip,and by limiting the number of the ultra-thin transistors; however, in any case, such high gate leakagecurrent density is a big burden for mobile devices, in which reduction of standby power consumption is

a concern Thus, development of high dielectric constant (or high-k) gate insulator with small gateleakage current is strongly demanded; however, intensive study and development of the high-k gatedielectrics have started only a few years ago, and it is expected that we have to wait at least another fewyears until the high-k insulator becomes mature for use of the production

The necessary conditions for the dielectrics are as follows [27]: (i) the dielectrics remain in the phase at the process temperature of up to about 1000 K, (ii) the dielectrics are not radio-active, (iii) thedielectrics are chemically stable at the Si interface at high process temperature This means that nobarrier film is necessary between the Si and the dielectrics Considering the conditions, white columns inthe periodic law of the elements shown in Fig 1.20 remained as metals whose oxide could be used as the

use as the gate insulator of MOSFET from this point of view

(CET) were tested for the gate insulator of MOS diodes and MOSFETs and leakage current of several

(IEDM93)

IBM’99 (SOI) (IEDM99)

0.04

2030

0.008

(SSDM99) : with ITRS scaling parameters

: thicker gate insulator than ITRS

Intel’00 (IEDM00) Intel 2000 (plan)

FIGURE 1.19 Trend of drain current.

Trends and Projections for the Future of Scaling and Future Integration Trends 1-13

HfSixOy) or SiO2at the Si interface during the MOSFET fabrication process has been a serious problem.This interfacial layer acts to reduce the total capacitance and is thought to be undesirable for obtaininghigh performance of MOSFETs Ultrathin nitride barrier layer seems to be effective to suppress the

these interfacial layers were significantly degraded by several tens of percent, while with entire Zr silicate

interfacial silicate layer would help the mobility improvement as well as the gate leakage current

micro-crystals during the heat process [31,33]

this moment [33] There was no interfacial silicate layer formed, and mobility was not degraded at all

React with Si

Other failed reactions.

Reported since Dec 1999.

(MRS, IEDM, ECS, VLSI)

Plotted on the material given by J R Hauser

at IEDM Short Course on Sub-100 nm CMOS (1999) Ti

FIGURE 1.20 Metal oxide gate insulators reported since Dec 1998 [27].

RTCVD LPCVD

Zr alminate

Zr-Al silicate

FIGURE 1.21 Recently reported (a) high-k materials and (b) deposition methods.

The dielectric constant was 20–30 Another merit of the La2O3 insulator is that no micro-crystalformation was found in high temperature process of MOSFET fabrication [33] There is a strongconcern for its hygroscopic property, although it was reported that the property was not observed in

very easily form a silicate during the thermal process Thus, we have to watch the next report of the

leakage current [42] However, it was shown that significant film volume expansion by absorbing themoisture of the air was observed La and Pr are just two of the 15 elements in lanthanoids series.There might be a possibility that any other lanthanoid oxide has even better characteristics for thegate insulator Fortunately, the atomic content of the lanthanoids, Zr, and Hf in the earth’s crust is muchlarger than that of Ir, Bi, Sb, In, Hg, Ag, Se, Pt, Te, Ru, Au, as shown in Fig 1.22

controllability of the flatband voltage is very difficult This problem should be solved before it is used forthe production There is a possibility that Zr, Hf, La, and Pr silicates are used for the next generation gateinsulator with the sacrifice of the dielectric constant to around 10 [31,35,37] It was reported that thesilicate prevent from the formation of micro-crystals and from the degradation in mobility as described

[44–46], because it is relatively mature for use for silicon LSIs

FIGURE 1.22 Clarke number of elements.

Trends and Projections for the Future of Scaling and Future Integration Trends 1-15

1.4 Gate Electrode

Figure 1.23 shows the changes of the gate electrode of MOSFETs Originally, Al gate was used for theMOSFETs, but soon poly Si gate replaced it because of the adaptability to the high temperature processand to the acid solution cleaning process of MOSFET fabrication Especially, poly gate formation stepcan be put before the S=D (source and drain) formation This enables the easy self-alignment of S=D tothe gate electrode as shown in the figure In the metal gate case, the gate electrode formation shouldcome to the final part of the process to avoid the high temperature and acid processes, and thus self-alignment is difficult In the case of damascene gate process, the self-alignment is possible, but processbecomes complicated as shown in the figure [47] Refractory metal gate with conventional gate electrodeprocess and structure would be another solution, but RIE (Reactive Ion Etching) of such metals withgood selectivity to the gate dielectric film is very difficult at this moment

As shown in Fig 1.24, poly Si gate has a big problem of depletion layer formation This effect wouldnot be ignored when the gate insulator becomes thin Thus, despite the above difficulties, metal gate isdesirable and assumed to be necessary for future CMOS devices However, there is another difficulty forthe introduction of metal gate to CMOS For advance CMOS, work function of gate electrode should be

Poly Si

TiN, Mo etc

Conventional Damascene

ILD

CMP

FIGURE 1.23 Gate electrode formation change.

Poly Si

Depletion layer Inversion

layer

Depletion layer

Inversion layer

Positive bias

Effective thickness

FIGURE 1.24 Depletion in poly-Si gate.

selected differently for n- and p-MOSFETs to adjust the threshold voltages to the optimum values.Channel doping could shift the threshold voltage, but cannot adjust it to the right value with good

Si gate is used for PMOS In the metal gate case, it is assumed that two different metals should be usedfor N-and PMOS in the same manner as shown in Table 1.3 This makes the process further complicatedand makes the device engineer to hesitate to introduce the metal gate Thus, for the short-range—probably to 70 or 50 nm node, heavily doped poly Si or poly SiGe gate electrode will be used But in thelong range, metal gate should be seriously considered

Figure 1.25 shows the changes of S=D (source and drain) formation process and structure S=D becomesshallower for every new generation in order to suppress the short-channel effects Before, the extensionpart of the S=D was called as LDD (Lightly Doped Drain) region and low doping concentration wasrequired in order to suppress electric field at the drain edge and hence to suppress the hot-carrier effect.Structure of the source side becomes symmetrical as the drain side because of process simplicity.Recently, major concern of the S=D formation is how to realize ultra-shallow extension with lowresistance Thus, the doping of the extension should be done as heavily as possible and the activation

of the impurity should be as high as possible Table 1.4 shows the trends of the junction depth and sheet

TABLE 1.3 Candidates for Metal Gate Electrodes (unit: eV)

Low E Ion Imp.

Pocket/Halo

FIGURE 1.25 Source and drain change.

Trends and Projections for the Future of Scaling and Future Integration Trends 1-17

resistance of the extension requested by ITRS 2000 As the generation proceeds, junction depth becomesshallower, but at the same time, the sheet resistance should be reduced This is extremely difficult.

In order to satisfy this request, various doping and activation methods are being investigated As thedoping method, low energy implantation at 2–0.5 keV [48] and plasma doping with low energy [49] arethought to be the most promising at this moment The problem of the low energy doping is lower retaindose and lower activation rate of the implanted species [48] As the activation method, high temperaturespike lamp anneal [48] is the best way at this moment In order to suppress the diffusion of the dopant,and to keep the over-saturated activation of the dopant, the spike should be as steep as possible Laseranneal [50] can realize very high activation, but very high temperature above the melting point at thesilicon surface is a concern Usually laser can anneal only the surface of the doping layer, and thus deeperportion may be necessary to be annealed by the combination of the spike lamp anneal

In order to further reduce the sheet resistance, elevated S=D structure of the extension is necessary, asshown in Fig 1.26 [6] Elevated S=D will be introduced at the latest from the generation of sub-30 nm

TABLE 1.4 Trend of S =D Extension by ITRS

S 4 D

100 200 300 400 500

FIGURE 1.26 Elevated source and drain.

gate length generation, because sheet resistance of S=D will be the major limiting factor of the deviceperformance in that generation.

Salicide is a very important technique to reduce the resistance of the extrinsic part of S=D—resistance

of deep S=D part and contact resistance between S=D and metal Table 1.5 shows the changes of the

promising because of its superior nature of smaller silicon consumption at the silicidation reaction [10]

Channel doping is an important technique not only for adjusting the threshold voltage of MOSFETsbut also for suppressing the short-channel effects As described in the explanation of the scaling method,the doping of the substrate or the doping of the channel region should be increased with the downsizing

of the device dimensions; however, too heavily doping into the entire substrate causes several problems,such as too high threshold voltage and too low breakdown voltage of the S=D junctions Thus, theheavily doping portion should be limited to the place where the suppression of the depletion layer isnecessary, as shown in Fig 1.27 Thus, retrograde doping profile in which only some deep portion is

TABLE 1.5 Physical Properties of Silicides

S

Depletion region

D

Highly doped region FIGURE 1.27 Retrograde profile.

Trends and Projections for the Future of Scaling and Future Integration Trends 1-19