Model-Based Design for Embedded Systems- P23 doc

Dynamic power in optical interconnect is furtherreduced with the smaller overall circuit transistors used in this analysis.. Since different tech-nology domains, such as electrical digit

Platform for Model-Based Design of Integrated Multi-Technology Systems 637

Using static and dynamic power information, the total energy can be culated (Figure 19.14)

cal-The overall power is shown to be reduced between S1 and S2 by tors of between 2 and 4 The greatest reduction is achieved at higher linklengths, which is the expected context for the use of such optical links For

fac-S2, power reduction can be considered to be a major argument in favor of

optical interconnect For S1, it is clear that the static power comparison isthe weak point for optical interconnect, because of continuous biasing of thesource (avoiding turn-on times to achieve the required bit rate) and of thereceiver circuit (the circuit bandwidth is directly related to quiescent biascurrent) The reduction in source threshold current and in detector capaci-

tance in S2has a significant impact on both these factors, to the extent that thestatic power in optical links, while still higher than that of electrical intercon-nect, is no longer dominant Dynamic power in optical interconnect is furtherreduced with the smaller overall circuit transistors used in this analysis Thetotal power comparison shows power reduction factors between 5x and 10xfor link lengths above 10 mm and for the two most advanced technologynodes It is likely that comparisons using technologies with transistor gatelengths below 32 nm will further improve this comparison since on the elec-trical side the static power dissipation will increase with leakage current Wecan thus consider that the optical device improvements constitute the mainpath to the solution to the following recommendation: “Power, and partic-ularly static power, is a key performance metric to optimize during explo-ration of optical interconnect device specifications.” This is an illustration ofthe type of feedback our approach can give to photonic device engineers

19.5 Conclusions and Ideas for the Future

In this chapter, we have looked at several aspects of heterogeneous designmethods in the context of increasing diversification of integration technolo-gies The rationale and analysis of the situation in terms of technological evo-lution and severe gaps in design technology show a clear need for advances

in this domain The experimental RuneII heterogeneous design platformaddresses some of these needs—in particular we have shown how designprocesses can be formalized over multiple abstraction levels and multipledomains using a common model for design knowledge formulation calledAMS/MT IP To address the need to represent this knowledge at higherabstraction levels in order to retain compatibility with system-level designmethods, we have demonstrated the feasibility of the use of UML and estab-lished parallels between the UML concepts and widely used concepts inAMS/MT descriptions We have successfully used these concepts to buildclass diagrams for functional and structural models of integrated opticallink component libraries, and implemented a synthesis scenario to explore,

in a quite detailed way, the available design space over a number of verydifferent dimension types This design method and technology is partic-ularly useful for the repetitive design of fixed optical link structures sub-ject to varying design constraints, technology parameters, and performance

Platform for Model-Based Design of Integrated Multi-Technology Systems 639

requirements We have illustrated the direct application of our approach foroptical link synthesis and technology performance characterization by ana-lyzing optical link performance for two sets of photonic component parame-ters and three CMOS technology generations Importantly for technologicaldevelopment, the results of such analyses can generate useful feedback fromsystem designers to component designers

In our view, the next major step in technological evolution for SoC cerns 3D integration This approach, exploiting the vertical dimension, pro-vides an opportunity to continue to achieve the performance levels predicted

con-by the extrapolation of Moore’s law, but using a different technologicalapproach The main impact is to enable the construction of highly complexsystems (e.g., multiple core data-processing systems with multiple memorybanks in close spatial proximity; highly heterogeneous systems using mul-tiple technologies for specific functional layers) while reducing the cost ofcommunication by several orders of magnitude The direct consequences ofthis approach are to (1) improve isochronous signal coverage and (2) allowevolution toward modular integrated systems Such an approach should also

in the long term enable novel vertical interconnect solutions (e.g., embeddedrepeaters, vertical switches, etc.) While by no means technologically simple,

it does represent a major design paradigm shift away from the conventionalapproach of traditional Moore’s law scaling toward “equivalent scaling” and

“functional diversity” through unconventional approaches

In this context, several tradeoff situations can be clearly shown to requireheterogeneous design methods, which cannot as yet be processed by existingtools Some examples are given here

• Tradeoffs for data-processing systems using, for example, 45 nmCMOS for processor cores and a specific technology (Flash–DRAM) formemory While the gain over conventional planar architectures is clear(high core-memory bandwidth and high memory capacity leading toreduction/elimination of cache structure, enabling orders of magni-tude improvements in processing time for algorithms requiring highdata-rate memory access), the organization of the memory and its spa-tial organization in relation to achievable through-silicon via (TSV)density and characteristics, and to the number and size of processorcores, has to be explored

• Partitioning in transformations from a planar chip to a 3D architecture

It will, for example, be necessary to explore comparisons between acomplete system on chip built from an aggressive planar CMOS tech-nology and a technological partition between using the same aggres-sive CMOS technology for data processing, but a less aggressive, morestable CMOS technology for I/O functions, analog, power, voltage reg-ulators to achieve interfacing and to compensate for variability, etc.The tradeoffs here concern cost, variability, performance, power, andprocess simplification

• Tradeoffs for mobile computing nodes in a 3D context using, forexample, an aggressive CMOS technology for processor cores, specificadvanced technology for memory, mature technology for analog, and

a specific technology for RF (e.g., passive RF MEMS) Here, the focus is

on overall power minimization exploiting the reduced communicationcost between the data-processing layer(s) (interpreting receivedsymbols with more complex interpolation functions) and the RF layer(relaxed constraints on RF MEMS tunability and speed based on algo-rithm efficiency)

Acknowledgment

This work was partially funded by the European FP6 IST program underPICMOS FP6-2002-IST-1-002131

References

[BIN2005] P R A Binetti et al., A compact detector for use in photonic

interconnections on CMOS ICs, in Proceedings of the Symposium

[CAR2004] C T Carr, T M McGinnity, and L J McDaid, Integration of

UML and VHDL-AMS for analogue system modeling, BCS

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[CHA2004] V Chaudhary, M Francis, W Zheng, A Mantooth, and L

Lemaitre, Automatic generation of compact semiconductor

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waveguides, Japanese Journal of Applied Physics, 43(3), 646–647,

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[FUJ2000] R Fujita, R Ushigome, and T Baba, Continuous wave lasing in

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μA, Electronics Letters, 36(9), 790–790, 2000

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[GIE2005] G Gielen et al., Analog and digital circuit design in 65 nm

CMOS: End of the road? in Proceedings of the Design Automation

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design flow for SoC applications, Proceedings of the International

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(ITRS), Sematech, 2007 http://www.itrs.net

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1174, 1994

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Gaffiot, Predictive design space exploration of maximum

band-width CMOS photoreceiver preamplifiers, in IEEE International

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[OCO2006] I O’Connor, F Tissafi-Drissi, G Revy, and F Gaffiot,

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syn-thesis of integrated optical interconnect, IEEE Transactions on

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2007

CAD Tools for Multi-Domain Systems

on Chips

Steven P Levitan, Donald M Chiarulli, Timothy P Kurzweg, Jose A Martinez, Samuel J Dickerson, Michael M Bails, David K Reed, and Jason M Boles

CONTENTS

20.1 Introduction 644

20.2 Chatoyant Multi-Domain Simulation 646

20.2.1 System Simulation in Chatoyant 646

20.2.2 Device and Component Models 647

20.2.3 Simulation Issues 649

20.2.4 Electrical and Optoelectronic Models 650

20.2.4.1 Example Modeling of CMOS Circuits 652

20.2.5 Mechanical Models 652

20.2.6 Optical Propagation Models 657

20.2.6.1 Gaussian Models 658

20.2.6.2 Scalar Diffractive Models 659

20.2.6.3 Angular Spectrum Technique 663

20.2.7 Simulations and Analysis of Optical MEM Systems 666

20.2.7.1 Full Link Example 667

20.2.7.2 Optical Beam Steering/Alignment System 668

20.2.7.3 Angular Spectrum Optical Simulation of the Grating Light Valve 674

20.3 HDL Co-Simulation Environment 679

20.3.1 Architecture 680

20.3.1.1 System Generator 680

20.3.1.2 Runtime Environment: Application of Parallel Discrete Event Simulation 681

20.3.1.3 Conservative versus Optimistic Synchronization 682

20.3.1.4 Conservative Synchronization Using UNIX IPC Mechanisms 683

20.3.2 Co-Simulation of Experimental Systems 685

20.3.2.1 Fiber Image Guide 685

20.3.2.2 Smart Optical Pixel Transceiver 685

20.3.2.3 FIG Runtimes 687

20.3.2.4 SPOT Runtimes 688

20.4 Summary 689

20.4.1 Conclusions 690

Acknowledgments 691

References 691

20.1 Introduction

In the last several years there has been much success in the realm ofmulti-domain, mixed-signal system on chip (SoC) technology Devices rang-ing from heterogeneous multi-core processors to micro-electromechanicalsystems (MEMS) to labs-on-chips are becoming highly integrated intochip-scale packages However, the complexity of this multi-technology inte-gration increases the difficulty of verifying such systems Since different tech-nology domains, such as electrical (digital and analog), optical (free-spaceand fiber), and mechanical (micro and macro), coexist in one package, therehas emerged a need for tools that can verify such heterogeneous systems.For these integrated micro-systems the goal is to model large numbers ofboth linear and nonlinear components with sufficient speed and accuracy

to explore the design space at the system level Beyond functional design,mixed-technology tools, working at the system level, must support the tra-ditional models of performance (e.g., speed, power, and area) as well as thespecial needs of mixed-technology systems This means being able to analyzesuch things as crosstalk, noise, and mechanical tolerance in an interactiveenvironment, and leads to the requirement of a computationally efficient yetaccurate mixed-technology simulation framework These problems are exac-erbated by the need to model the behavior of the controlling digital hardwareand/or software and the feedback between these two worlds Most impor-tantly, the tools must be able to capture the interaction of these realms inorder to support the designer in making both architectural and technologicaltradeoffs

These requirements emphasize the need for high-level models for optical,electronic, and electromechanical components, accurate and computationallyefficient analog simulation, and an interface to traditional digital simulationand embedded software development tools To date, no single CAD tool hasbeen able to completely model the complexity of these multi-domain systems

on chips (MDSoCs) Current MDSoC design methodology is to use a ety of “point tools” for each domain present in the design, and then stitchtogether the results using an additional tool This process is both time con-suming and inefficient

vari-Therefore, the need to perform high-level system simulations in a singleframework has driven both academia and industry to the development of

“system simulation” environments Since most of these support top-downdesign, the focus is on hardware and software codesign and verification.Some examples of commercially available products include Seamless fromMentor Graphics, Incisive Simulator Products from Cadence, and MultiSimfrom Electronics Workbench Many academic tools have also been developedsuch as Ptolemy [1] from the University of California at Berkeley, Pia [2] from

CAD Tools for Multi-Domain Systems on Chips 645

the University of Washington, and CoSim [3] from the TIMA Laboratory atthe Institut National Polytechnique Grenoble and SGS-Thomson

Most of these simulation environments target hardware–softwareco-simulation and rely on other simulators to perform tasks such as mechan-ical finite element analysis (FEA), optical propagation analysis (e.g., RSoft),and circuit-level simulation (e.g., SPICE) Some of the modern tools, such asSystem Vision from Mentor Graphics, allow for complete system modelingand simulation in mechanical and mixed-signal electrical domains, but donot support optical or fluidic systems

In this chapter we introduce a tool that can simulate and thus ify the behavior of MDSoCs from the system architectural level down tothe physical level of such technologies This is accomplished by using themixed-domain, mixed-signal simulation environment, Chatoyant [4], and acommercial mixed-language HDL simulator, ModelSim The combination ofthese two simulators is accomplished using UNIX-style inter-process com-munication (IPC) as an implementation method for parallel discrete event(DE) simulation

ver-The methodology here is similar to the work presented in an earlier ter by Lee and Zheng [5] However, we have developed our models hierar-chically such that lower-level “component” models support continuous timesemantics, while composition of those models is done with discrete timesemantics Components pass complex messages among themselves under aglobal simulation framework Similar to the ideas of Gheorghe, Nicolescu,and Boucheneb in this volume [6], message semantics are defined by com-mon message classes Additionally, conversion between these analog mod-els and the multivalued digital models of a hardware description language(HDL) simulator is mediated by a set of predefined semantic rules

chap-The rest of this chapter is organized as follows: It begins with the tigation of methods for modeling digital free-space optoelectronic systems.These are systems that incorporate electronic digital and analog components,optoelectronic interface devices, such as laser and detector arrays, and free-space optical interconnects that are composed of passive and active opticalelements These models have been successfully incorporated into an opto-electronic system-level design tool called Chatoyant [4,7–9] We present thefeatures of Chatoyant that are useful in the modeling, simulation, and anal-ysis of MDSoCs Next, we introduce electrical, mechanical, and optical mod-els that are used as building blocks in multi-domain system design We thenpresent the analog/digital co-simulation environment and discuss issues insynchronization and signal conversion between the analog domains, man-aged by Chatoyant, and the digital domain, managed by ModelSim Finally,

inves-we show the utility of the co-simulation environment with several examplesystems

20.2 Chatoyant Multi-Domain Simulation

Chatoyant is a mixed-domain, mixed-signal simulation environment oped at the University of Pittsburgh It is capable of simulating MEMS andoptical MEMS or MOEMS at a system and architectural level This permitsdesign space exploration by examining the effects of variations in componentparameters on system performance and the interaction of these componentsacross technology domains For example, one can model the small adsorp-tion of optical power in a MEMS mirror, and how that power, as heat, causesthe mirror to deform That deformation, in turn, could degrade the quality

devel-of the analog signal that is modulating the light beam used for chip-to-chipcommunications between a processor and L3 cache in a 3D optoelectronicpackage Of course, the degraded signal could be recovered with good ana-log circuitry, but it could also have error correcting codes embedded in dig-ital data Some typical questions a system-level designer would ask in thiscase are these: Where should they invest more design, fabrication effort, andproduct expense? Should it be better mirrors, lower power optics with betteranalog signal processing, or more bits of ECC code? Design exploration andtradeoff analysis of this nature motivated the development of Chatoyant

20.2.1 System Simulation in Chatoyant

The Chatoyant environment is a series of multipurpose libraries that are builtupon the Ptolemy framework from the University of California, Berkeley.Ptolemy provides the basic infrastructure for different domains of simulationsuch as dynamic data flow (DDF), static data flow (SDF), and discrete event(DE) Chatoyant builds upon the simulation domains provided by Ptolemy

by adding components that perform analog netlist simulation, optical eling and analysis, and mechanical elemental analysis [10]

mod-Chatoyant is based on a methodology of system-level architecture design

In this methodology, architectures are defined in terms of models for

“modules,” the “signals” that pass between them, and the “dynamics” ofthe system behavior For electrical, mechanical, and optical systems, sig-nals are represented as electronic waveforms, mechanical deformations, andmodulated carriers, (i.e., beams of light) Using the characteristics of thesesignals, we define models for the system components in terms of the man-ner in which they transform the characteristic parameters of these signals.Chatoyant’s component models are written in C++ with sets of user-definedparameters for the characteristics of each module instance

Component models are based on three modeling techniques The first is

a “derived model” technique where analytic models are used based on anunderlying physical model of the device These can be very abstract “0th-order” models, or more complex models involving time varying functions,

CAD Tools for Multi-Domain Systems on Chips 647

internal state, or memory The second class of models is based on cal measurements from fabricated devices These models use measured dataand interpolation techniques to directly map input signal values to outputvalues The third technique is reduced-order or response surface models Forthese models, we use the results of low-level simulations, such as finite ele-ment solvers, or simulators, and generate a reduced-order model, that coversthe range of operating points for the component We have implemented thistechnique using a variety of methods from a polynomial curve fit, or simpleinterpolation over the range of operation, to nonlinear model order reduction[11,12]

empiri-We have successfully used all three of these methods to create four ponent libraries: The optoelectronic library, which includes devices such

com-as vertical cavity surface emitting lcom-asers (VCSELs), multiple quantum well(MQW) modulators, and p-i-n detectors The optical library contains compo-nents such as refractive and diffractive lenses, lenslets, mirrors, and aper-tures The electrical library includes CMOS drivers and transimpedanceamplifiers, and the mechanical library contains beams, plates, and mechani-cal assemblies such as scratch drive actuators (SDA) and deformable mirrors.Signal information is carried between modules using a C++ “messageclass.” To maximize our modeling flexibility, the signals in Chatoyant arecomposite types, representing the attributes of position and orientation forboth optical and mechanical signals, voltages and impedances for electronicsignals, and wave front, phase, and intensity for optical signals The compos-ite type is extensible, allowing us to add new signal characteristics as needed.The advantage of using such a class is that one single message contains opti-cal, electrical, or mechanical information, and each component type-checksthe data, extracting the relevant information The message class also carriestime information for each message in the stream of data

The DE simulation scheduler allows modeling of multi-dynamic tems where every component can alter the rate of consumed/produced dataduring simulation The scheduler also provides the system with bufferingcapability This allows the system to keep track of all the messages arriving

sys-at one module when multiple input streams of dsys-ata are involved

Before the discussion of individual signal models and to further stand the development of our system-level simulation tool, we first introduceour device and component modeling methodology

under-20.2.2 Device and Component Models

In our methodology, we make a distinction between device-level andcomponent-level modeling Device-level models focus on explicitly model-ing the processes within the physical geometry of a device such as fields,fluxes, stresses, and thermal gradients For component-level models thesedistributed effects are characterized in terms of device parameters, and

the models focus on the relationships between these parameters and statevariables (e.g., optical intensity, phase, current, voltage, displacement, ortemperature) as a set of linear or nonlinear differential equations In theelectronic domain these are often called “small signal models” or “circuitmodels.”

Circuit-level (or more generally, component-level) modeling techniquescan be used for optoelectronic device modeling, but, for most models, thedegree of accuracy does not match that required for performance analysis inthese types of devices Fast transient phenomena, the dependencies on thephysical geometry of the device, and large-signal operation are generally notwell characterized by these kinds of models Device-level simulation tech-niques offer the degree of accuracy required to model fast transients (e.g.,chirp), fabrication geometry dependencies, and steady-state solutions in theoptical device [13]; however, modeling these processes requires specializedtechniques and large computational resources that produce results that arenot compatible with simulators required for other domains For instance, it isdifficult to model the behavior of a laser in terms of carrier population densi-ties, and at the same time, the emitted light in terms of electromagnetic fieldpropagation

There are two obvious techniques to deal with this problem of devicesimulation versus circuit simulation The first is the use of two levels of sim-ulation, a device-level simulation for each unique domain, coupled to a com-mon circuit-level simulation that coordinates the results of each However,for the case of device and circuit co-simulation, this technique has all thedrawbacks previously mentioned for the device-level simulation with theadditional computational resources required to coordinate analog simula-tors, which means not just in making time-stamps match but to force them toconverge to a common point of operation [14,15]

Rather, our approach is to increase the accuracy of the circuit-level(component-level) models That is, to incorporate the transient solution,along with other second order effects, of the device analysis within thecircuit-level simulation This is accomplished by creating circuit models forthese higher order effects and incorporating them into the circuit model

of the optoelectronic device Different methodologies can be used to late the device-level expressions, which characterize the semiconductordevice operation (e.g., Poisson’s, carrier current, and carrier continuity equa-tion) into a set of temporal linear/nonlinear differential equations [13,16].The advantage of having this representation is that we can simulate elec-tronic and optoelectronic models in a single mixed-domain component-levelsimulator

trans-These enhanced component models can then fit in a DE simulationengine, since convergence of the analog models is compartmentalized ineach device The result is an abstract representation of the system consist-ing of a set of loosely coupled modules interchanging information as energysignals However, this approach brings the challenge of choosing which

CAD Tools for Multi-Domain Systems on Chips 649

circuit/component modeling techniques will be optimal for accurate and fastcharacterization of the different modules involved in this system

20.2.3 Simulation Issues

Traditional circuit simulators based on numerical integration solvers offerthe required accuracy to solve linear and nonlinear DE systems; however,they are too computationally expensive to consider for evaluating individualmodules in a mixed-domain framework [17,18] In the linear case, success-ful low order reduction techniques have been used to model high-densityinterconnection networks with excellent computational efficiency [19–22] Inthe nonlinear case, however, the success is only partial Work has been con-ducted to apply reduction techniques to obtain macro-models for the inter-connection section and use them in circuit simulators, such as SPICE [23], as

a way to simplify the computational task carried out by such solvers [18,22].Merging both techniques maintains the accuracy offered by circuit simula-tors, but also the problems associated with them

Two problems with this technique are the difficulties guaranteeing theconvergence of the solution and the relatively high computational load Pio-neer nonlinear network modeling using piecewise models in a timing simu-lator RSIM [24] was conducted by Kao and Horowitz [25] While well suitedfor delay estimation in dense nonlinear networks, the limited complexity

of models and tree analysis technique used do not allow piecewise linear(PWL) timing analyzers to simulate higher order effects that are of signifi-cant importance in the modeling of typical optoelectronic devices

The fact that the density of the network generated for modeling ofour optoelectromechanical devices is moderate allows us to consider PWLmodeling merged with linear numerical analysis as a way to achieve thedesired accuracy with a lower computational demand More importantly, theamount of feedback between active devices in such models is limited whencompared with dense VLSI networks, which makes the scheduling task fea-sible even for increased numbers of regions of operation for each device.For simulation, we perform a linear numerical analysis in order to solvethe differential equation necessary to obtain an accurate solution, usingpiecewise modeling to overcome the iteration process encountered in theintegration technique used in traditional circuit simulators for the nonlinearcase Linearizing the behavior of the nonlinear devices by regions of opera-tion simplifies the computational task to solve the system This also allows us

to trade accuracy for speed Most importantly, PWL models for these devicesallow us to integrate mechanical, electrical, and optical components in thesame simulation We have successfully used this technique to model electric,optical, and mechanical components, and are currently expanding this samemethodology to incorporate fluid models These models will be discussed inthe next section

20.2.4 Electrical and Optoelectronic Models

Our optoelectronic modeling is accomplished as shown in Figure 20.1 Given

a device, such as an optical transmitter, we perform linear and nonlinear block decomposition of the circuit model of the device This decomposes thedesign into a linear multiport subblock section and nonlinear subblocks Thelinear multiport subblock can be thought of as characterizing the intercon-nection network or parasitics while the nonlinear subblocks characterize theactive devices

sub-Then, modified nodal analysis (MNA) [26] is used to create a matrix resentation for the device, as shown in Figure 20.2 In this figure, [S] is the

rep-storage element matrix, [G] is the conductance matrix, [x] is the vector of

state variables, [b] is a connectivity matrix, [u] is the excitation vector, and [I]

is the current vector

The linear subblock elements can be directly matched to this tation, but the nonlinear elements need to first undergo a further trans-formation We perform piecewise modeling of the active devices for eachnonlinear subblock When we form each nonlinear subblock, an MNA tem-plate is used for each device in the network The use of piecewise models isbased on the ability to change these models for the active devices depending

represen-on the changes in crepresen-onditirepresen-ons in the circuit, and thus the regirepresen-ons of operatirepresen-on.The templates generated can be integrated to the general MNA contain-ing the linear components adding their matrix contents to their correspond-ing counterparts This process is shown in Figure 20.2 for the S matrix Thissame composition is done for the other matrices The size of each of the

template

Modified nodal analysis MNA composition

Linear solver (s domain) g

u

FIGURE 20.1

Piecewise modeling for electrical/optoelectrical devices (From Kurzweg,

T.P et al., J Model Simul Micro-Syst., 2, 21, 2001 With permission.)