BCF STATUS,C ; get ready to add ADDWF Lobyte ; restore low byte BTFSC STATUS,C ; Carry into high byte?. INCF Hibyte ; yes - add carry to high byte ADDWF Hibyte ; ..high byte ; Subtract
Trang 1; SUBROUTINES ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; INCLUDE "LCD2.INC" ; Include display routines
; -; Convert 16 bit binary result to 5 digits
; -conv MOVF CCPR1L,W ; Get high byte
MOVWF Lobyte ; and store MOVF CCPR1H,W ; Get low byte MOVWF Hibyte ; and store MOVLW 06 ; Correction value BCF STATUS,C ; prepare carry flag ADDWF Lobyte ; add correction BTFSC STATUS,C ; and carry INCF Hibyte ; in required CLRF Tents ; clear ten thousands register CLRF Thous ; clear thousands register CLRF Hunds ; clear hundreds register CLRF Tens ; clear tens register CLRF Ones ; clear ones register
; Subtract 10000d (2710h) and count sub10 MOVLW 010 ; get low byte to sub BSF STATUS,C ; get ready to subtract SUBWF Lobyte ; sub 10h from low byte BTFSC STATUS,C ; borrow required?
GOTO sub27 ; no - sub high byte MOVF Hibyte,F ; yes - check high byte BTFSS STATUS,Z ; zero?
GOTO take1 ; no - take borrow MOVLW 010 ; yes - load low byte to add BCF STATUS,C ; get ready to add ADDWF Lobyte ; restore low byte GOTO subE8 ; next digit take1 DECF Hibyte ; take borrow sub27 MOVLW 027 ; get high byte to sub BSF STATUS,C ; get ready to subtract SUBWF Hibyte ; sub from high byte BTFSS STATUS,C ; borrow taken?
GOTO done1 ; yes - restore remainder INCF Tents ; no - count ten thousand GOTO sub10 ; sub 10000 again done1 MOVLW 010 ; restore
BCF STATUS,C ; get ready to add ADDWF Lobyte ; restore low byte BTFSC STATUS,C ; Carry into high byte? INCF Hibyte ; yes - add carry to high byte
ADDWF Hibyte ; high byte
; Subtract 1000d (03E8) and count subE8 MOVLW 0E8 ; get low byte to sub
BSF STATUS,C ; get ready to subtract SUBWF Lobyte ; sub from low byte BTFSC STATUS,C ; borrow required?
GOTO sub03 ; no - do high byte MOVF Hibyte,F ; yes - check high byte BTFSS STATUS,Z ; zero?
GOTO take2 ; no - take borrow MOVLW 0E8 ; load low byte to add BCF STATUS,C ; get ready to add ADDWF Lobyte ; restore low byte GOTO sub64 ; next digit take2 DECF Hibyte ; take borrow sub03 MOVLW 03 ; get high byte BSF STATUS,C ; get ready to subtract SUBWF Hibyte ; sub from high byte BTFSS STATUS,C ; borrow taken?
GOTO done2 ; yes - restore high byte INCF Thous ; no - count ten thousand GOTO subE8 ; sub 1000 again done2 MOVLW 0E8 ; restore
BCF STATUS,C ; get ready to add ADDWF Lobyte ; restore low byte BTFSC STATUS,C ; Carry into high byte? INCF Hibyte ; yes - add carry to high byte
ADDWF Hibyte ; high byte
Program 6.3 Continued
Trang 2; Subtract 100d (064h) and count
sub64 MOVLW 064 ; get low byte BSF STATUS,C ; get ready to subtract SUBWF Lobyte ; sub from low byte BTFSC STATUS,C ; borrow required?
GOTO inchun ; no - inc count MOVF Hibyte,F ; yes - check high byte BTFSS STATUS,Z ; zero?
GOTO take3 ; no - take borrow MOVLW 064 ; load low byte to add BCF STATUS,C ; get ready to add ADDWF Lobyte ; restore low byte GOTO subA ; next digit take3 DECF Hibyte ; take borrow inchun INCF Hunds ; count hundred GOTO sub64 ; sub 100 again
; Subtract 10d (0Ah) and count, leaving remainder
subA MOVLW 0A ; get low byte to sub BSF STATUS,C ; get ready to subtract SUBWF Lobyte ; sub from low byte BTFSS STATUS,C ; borrow required?
GOTO rest4 ; yes - restore byte INCF Tens ; no - count one hundred GOTO subA ; and repeat
rest4 ADDWF Lobyte ; restore low byte MOVF Lobyte,W ; copy remainder
MOVWF Ones ; to ones register
; -
; Display period in microseconds
; - disp BSF Select,RS ; Set display data mode MOVLW 'T' ; Time period CALL send ; Display it MOVLW ' ' ; Space CALL send ; Display it MOVLW '=' ; Equals CALL send ; Display it MOVLW ' ' ; Space CALL send ; Display it
; Supress leading zeros
MOVF Tents,F ; Check digit BTFSS STATUS,Z ; zero?
GOTO show1 ; no - show it MOVF Thous,F ; Check digit BTFSS STATUS,Z ; zero?
GOTO show2 ; no - show it MOVF Hunds,F ; Check digit BTFSS STATUS,Z ; zero?
GOTO show3 ; no - show it MOVF Tens,F ; Check digit BTFSS STATUS,Z ; zero?
GOTO show4 ; no - show it MOVF Ones,F ; Check digit BTFSS STATUS,Z ; zero?
GOTO show5 ; no - show it
; Display digits of period
show1 MOVLW 030 ; Load ASCII offset ADDWF Tents,W ; Add digit value CALL send ; Display it show2 MOVLW 030 ; Load ASCII offset ADDWF Thous,W ; Add digit value CALL send ; Display it show3 MOVLW 030 ; Load ASCII offset ADDWF Hunds,W ; Add digit value CALL send ; Display it show4 MOVLW 030 ; Load ASCII offset ADDWF Tens,W ; Add digit value CALL send ; Display it show5 MOVLW 030 ; Load ASCII offset ADDWF Ones,W ; Add digit value CALL send ; Display it
Program 6.3 Continued
Trang 3SUMMARY 6
• The calculator demo performs single-digit arithmetic, using a keypad input and LCD display
• The output pulse generator uses hardware timer compare mode and a virtual oscilloscope to display the output
• Input period measurement uses the timer in capture mode and a virtual sig-nal generator to provide the input
1 Describe briefly how the keypad code is generated in the CALC application (3)
2 State the advantages of using an include file for the LCD driver routines in
; Show fixed characters
MOVLW ' ' ; Space CALL send ; Display it MOVLW 'u' ; micro CALL send ; Display it MOVLW 's' ; secs CALL send ; Display it MOVLW ' ' ; Space CALL send ; Display it MOVLW ' ' ; Space CALL send ; Display it
; Home cursor
BCF Select,RS ; Set display command mode MOVLW 0x80 ; Code to home cursor CALL send ; Do it
RETURN ; done
; -
; MAIN LOOP
; - start CALL inid ; Initialise display
BANKSEL PIE1 ; Select Bank 1 BSF PIE1,CCP1IE ; Enable capture interrupt BANKSEL PORTD ; Select Bank 0
BCF PIR1,CCP1IF ; Clear CCP1 interrupt flag loop CALL conv ; Convert 16 bits to 5 digits CALL disp ; Display period in microsecs GOTO loop
END ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Program 6.3 Continued
Trang 43 Outline the process required to display the negative result of a subtraction
4 State the meaning of the term ‘capture’ mode in an MCU timer (3)
5 Explain why the main PULSE program consists of only one statement (3)
6 Explain why the initial value in the timer preload registers in the PULSE
7 Explain why the ‘INCF CCPR1H’ instruction is needed in PULSE (3)
8 Describe briefly the role of the carry flag in the division process (3)
9 Explain the meaning of the term ‘compare’ mode in an MCU timer (3)
10 Identify the Timer 1 interrupt flag by register and bit label (3)
11 Describe the process for converting an 8-bit binary number to three ASCII
12 Describe the process for converting 16-bit binary into 5-digit BCD (5)
ASSIGNMENTS 6
6.1 BCD Addition
Outline a process to read a sequence of decimal keys into the MCU which is terminated with the ‘⫹’ key A further sequence of digits is terminated with the
‘⫽’ key The numbers must then be added and the result displayed Take ac-count of the fact that the numbers may not be the same length Do not write a source code program
6.2 CCP Control
Refer to the PIC 16F877 data manual Check the setup codes for capture and compare modes, and identify the function of each bit in the control registers initialised in the demo programs Then check the setup of the interrupt in each program, and again identify the function of each relevant bit in the control reg-isters Explain the significance of each setup option Why is the use of the hardware timer helpful in these applications? Consider if there are any alter-native methods to achieve the same results
Trang 56.3 Pulse Detection
A remote control receiver module generates a pulse whose length is controlled
by the lever position on the transmitter console The controller in the receiving system needs to determine the pulse length as short, mid-length or long Outline a routine to check if an input pulse is longer than 1.4 ms, shorter that 1.2 ms, or in between these limits, switching on a ‘long’ or ‘short’ output bit accordingly, with neither for a mid-length pulse
Trang 6Analogue Interfacing
Many control applications require the measurement of analogue variables, such as voltage, temperature, pressure, speed and so on Selected PIC MCUs incorporate analogue inputs, which are connected to an analogue to digital converter (ADC); this outputs a 10-bit binary representation of an input volt-age This result is then accurate to 1 part in 1024 (210), better than 0.1% at full scale, and precise enough for most purposes In some cases, it is only neces-sary to use 8 bits of the conversion, which gives an accuracy of 1 part in 256 (<0.5%)
In this chapter, programs to handle 8-bit and 10-bit data will be presented, and the additional software overhead required to achieve the higher accuracy can be seen The ADC is controlled from special function registers ADCON0 and ADCON1, and can generate a peripheral interrupt if required The output from the converter is stored in ADRESH (analogue to digital conversion result, high byte) and ADRESL (low byte)
8-bit Conversion
The processing for an 8-bit result is simpler, so this will be described first The ADC converts an analogue input voltage in the range 0–2.55 V to 10-bit binary, but only the upper 8 bits of the result are used, giving a resolution of
10 mV per bit (1/256⫻ 2.56 V)
Trang 78-bit Conversion Circuit
A test circuit to demonstrate 8-bit conversion and display is shown in Figure 7.1 The 16F877 MCU has eight analogue inputs available, at RA0, RA1, RA2, RA3, RA5, RE0, RE1 and RE2 These have alternate labels AN0–AN7 for this function RA2 and RA3 may be used as reference voltage inputs, setting the minimum and maximum values for the measured voltage range These inputs default to analogue operation, so the register ADCON1 has to be initialised explicitly to use these pins for digital input or output
INPUT & OUTPUT
The test voltage input at RA0 (analogue input AN0) is derived from a pot across the 5 V supply A reference voltage is provided at RA3 (AN3), which sets the maximum voltage to be converted, and thus the conversion factor required in the software The minimum value defaults to 0 V The 2.7 V zener diode provides a constant reference voltage; it is supplied via a current limit-ing resistor, so that the zener operates at the current specified for optimum voltage stability This is then divided down across the reference voltage pot RV1 and a 10k fixed resistor The range across the pot is about 2.7–2.4 V, and
is adjusted for 2.56 V, which gives a convenient conversion factor The LCD is connected to Port D to operate in 4-bit mode and display the voltage, as described in Chapter 4
Trang 8ADC OPERATION
A block diagram of the ADC module is shown in Figure 7.2 The inputs are connected to a function selector block which sets up each pin for analogue or digital operation according to the 4-bit control code loaded into the A/D port configuration control bits, PCFG0–PCFG3 in ADCON1 The code used, 0011, sets Port E as digital I/O, and Port A as analogue inputs with AN3 as the positive reference input
The analogue inputs are then fed to a multiplexer which allows one of the eight inputs to be selected at any one time This is controlled by the three ana-logue channel select bits, CHS0–CHS2 in ADCON0 In this case, channel 0 is selected (000), RA0 input If more than one channel is to be sampled, these select bits need to be changed between ADC conversions The conversion is triggered by setting the GO/DONE bit, which is later cleared automatically to indicate that the conversion is complete
ADC CLOCK
The speed of the conversion is selected by bits ADSC1 and ADSC0 The ADC operates by successive approximation; this means that the input voltage is fed
to a comparator, and if the voltage is higher than 50% of the range, the MSB
of the result is set high The voltage is then checked against the mid-point of the remaining range, and the next bit set high or low accordingly, and so on for
10 bits This takes a significant amount of time: the minimum conversion time
is 1.6 s per bit, making 16 µs for a 10-bit conversion The ADC clock speed must be selected such that this minimum time requirement is satisfied; the MCU clock is divided by 2, 8 or 32 as necessary Our simulated test circuit is clocked at 4 MHz This gives a clock period of 0.25 s We need a conversion time of at least 1.6 s; if we select the divide by 8 option, the ADC clock period will then be 8 ⫻ 0.25 = 2 s, which is just longer than the minimum required The select bits are therefore set to 01 (Figure 7.2 (b))
SETTLING TIME
The input of the ADC has a sample and hold circuit, to ensure that the voltage sampled is constant during the conversion process This contains an RC low-pass filter with a time constant of about 20 s Therefore, if the input voltage changes suddenly, the sample and hold circuit will take time to respond This needs to be taken into account, depending on the type of signal being measured
If sampling speed is not critical, a settling time delay of at least 20 s should be included in the conversion sequence In the test circuit, this is not a problem
RESULT REGISTERS
When the conversion is complete, the result is placed in the result register pair,
Trang 9(a)
(b)
GO/DONE, ADON
Conversion frequency select ADC start, ADC enable ADCON1 0000 0011 ADFM, PCFG3-0 Result justify, ADC input mode control
(c)
ADFM = 1 Right justified
ADFM = 0 Left justified
R = Result bits
- + Analogue
to Digital Converter
ADC MUX
ADC Control Registers (ADCON0, ADCON1)
Channel select bits
Analogue
Inputs
RA0 RA1 RA2 RA3 RE0 RE1 RE2
External reference voltages
Select external
or internal reference voltage.
Input Function Select
Set mix of analogue
or digital
DONE
Divider
Clock rate select
System clock
Vss Vdd
Vadc
Internal reference voltages
RA3
RA2
ADRESH ADRESL
ADIF
0000 00RR RRRR RRRR
ADRESH ADRESL
Figure 7.2 ADC operation: (a) ADC block diagram; (b) ADC control registers; (c) result
regis-ters configuration
Trang 10and the ADIF interrupt flag is set Since the result is only 10 bits, the posi-tioning in the 16-bit result register pair can be selected, so that the high 8 bits are in ADRESH (left justified), or the low 8 bits are in ADRESL (right justi-fied) (Figure 7.2 (c)) Obviously, to retain 10-bit resolution, both parts must be processed, so right justification will probably be more convenient in this case
If only 8 bits resolution is required, the process can be simplified If the result
is right justified, the low 8 bits in ADRESL will record the low bits of the conversion, meaning that only voltages up to 25% of the full range will be processed, but at full resolution If the result is left justified, the high byte will be processed, which will represent the full voltage range, but at reduced resolution
In our test circuit, the reference voltage is 2.56 V, and the justify bit ADFM
= 0, selecting left justify Only ADRESH then needs to be processed, giving re-sults for the full range at 8-bit resolution, which is about 1% at mid-range The result will be shown on the LCD as 3 digits, 0.00–2.55 The test input pot gives 0–5 V, but only 0–2.50 will be displayed Over range inputs will be displayed
as 2.55 V
8-bit Conversion Program
The test program is outlined in Figure 7.3, and the source code listed in Program 7.1 The output port and ADC control registers are initialised in the first block, with the LCD include file providing the display initialisation, and driver routines The main loop contains subroutine calls to read the ADC input, convert from binary to BCD and display it The routine to read the ADC sets the GO/DONE bit and then polls it until it is cleared at the end of the conver-sion The 8-bit result from ADRESH is converted to three BCD digits by the subtraction algorithm described previously Full-scale input is 255, which is displayed as 2.55 V
10-bit Conversion
Figure 7.4 shows a circuit, which demonstrates 10-bit, full resolution, analogue
to digital conversion The reference voltage circuit now provides a reference of 4.096 V, giving a wider range of 0–4.095 V With this reference voltage, and a maximum binary result of 1023 (210−1), the conversion output will increase at
4 mV per bit The result is displayed as a 4-digit fixed point decimal
The reference voltage circuit is a little different from the 8-bit circuit The zener voltage is divided down using fixed-value resistors, and the final voltage tweaked by adjusting the current to the zener This gives a finer adjustment