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EURASIP Journal on Wireless Communications and NetworkingVolume 2006, Article ID 12945, Pages 1 16 DOI 10.1155/WCN/2006/12945 Parametric Conversion Using Custom MOS Varactors Howard Chan

EURASIP Journal on Wireless Communications and Networking

Volume 2006, Article ID 12945, Pages 1 16

DOI 10.1155/WCN/2006/12945

Parametric Conversion Using Custom MOS Varactors

Howard Chan, 1 Zhongbo Chen, 1 Sebastian Magierowski, 1 and Krzysztof (Kris) Iniewski 2

1 Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada T2N 1N4

2 Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4

Received 14 October 2005; Revised 17 April 2006; Accepted 18 April 2006

The possible role of customized MOS varactors in amplification, mixing, and frequency control of future millimeter wave CMOS RFICs is outlined First, the parametric conversion concept is revisited and discussed in terms of modern RF communications systems Second, the modeling, design, and optimization of MOS varactors are reconsidered in the context of their central role

in parametric circuits Third, a balanced varactor structure is proposed for robust oscillator frequency control in the presence of large extrinsic noise expected in tightly integrated wireless communicators Main points include the proposal of a subharmonic pumping scheme based on the MOS varactor, a nonequilibrium elastance-voltage model, optimal varactor layout suggestions, custom 0.13 μm-CMOS varactor design and measurement, device-level balanced varactor simulations, and parametric circuit

evaluation based on measured device characteristics

Copyright © 2006 Howard Chan et al This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited

1 INTRODUCTION

Variable capacitors can play a very rich role in

radio-fre-quency (RF) transceivers In this paper we examine their use

in two key front-end functions: amplification and frequency

control Parametric amplification, a relatively uncommon

technique, is promoted in this paper Improvements to this

method are proposed by the incorporation of customized

MOS varactors in place of the traditional junction varactor

Also, we discuss modifications to the MOS varactor in the

context of its traditional role as a frequency control element

Anticipating a growing problem with interference between

IC elements sharing one substrate, a four-terminal

differen-tial structure intended to desensitize voltage-controlled

oscil-lators (VCOs) to large extrinsic noise variations is described

The paper is organized as follows First a narrow

out-line of the history and status of parametric amplification is

given inSection 2 A more detailed discussion of

paramet-ric circuit operation, improvements, and possible

incorpo-ration in a front-end transceiver is discussed in Section 3

Since the varactor constitutes the heart of parametric

sys-tems, Section 4 outlines the key integrated varactor

struc-tures, compares them based on two key merit figures, and

in-troduces potential device-level augmentations InSection 5

we return to parametric circuits and, with the results of

Section 4, estimate the performance possibilities for an

inte-grated setting Frequency control, the second key topic of this

report, is discussed inSection 6 This is approached from the

device level, where the advantage and limitations of employ-ing a modified common-mode rejection varactor structure

in a voltage-controlled oscillator (VCO) are discussed

2 PARAMETRIC CONVERSION: HISTORICAL REMARKS

Parametric circuits closely tie frequency conversion to am-plification and therefore can seamlessly account for the mix-ing function of front ends as well We broadly refer to them

as parametric converters in this work They are primarily known for their low-noise behavior and ability to operate at high frequencies

As implied by its name, parametric conversion involves the modulation of a system’s parameters as in the damped oscillatory equation below:

¨x + γ ˙x + ω2

1 +p(t)

Given a pumping disturbance at twice the oscillator’s natural frequency,

p(t) = A psin

2ω0t

A subharmonic (relative to the pump) response

x(t) = A s e αtsinω t (3)

can be solicited whereα ranges between positive and

neg-ative values depending on the oscillator damping and the

strength of the pumping signal It is commonly

acknowl-edged that such sustained parametric oscillations were first

observed by Michael Faraday In 1831 he reported the rise of

subharmonic oscillation as part of experiments on

acousti-cally pumped Chladni plates [1] In 1957, following

sugges-tions by Suhl [2] and Weiss [3], he reported the realization

of an experimental solid-state microwave amplifier

exploit-ing the parametric principle Notable among a large

num-ber of intermediate contributions is Hartley’s work on

elec-tromechanical parametric amplifiers [4,5] and Barrow’s fully

active parametric vacuum tube implementation [6] This

space has been a subject of interest in the MEMS arena for

low-frequency, precision sensing applications such as atomic

force microscopy [7,8] where the low-noise properties of

parametric systems are of particular benefit However, the

use of parametric amplification in terrestrial communication

systems is extremely rare Recently, a discrete time

paramet-ric circuit in a 0.25 μm-CMOS technology was reported [9]

The circuit took particular advantage of the three-terminal

inversion mode MOS varactor, but focused on low-frequency

applications in the 100 kHz range

The absence of parametric converters from the

commu-nications mainstream is mainly due to the superior utility

of transistor-based circuits for “low-” frequency commercial

applications Since the performance of parametric circuits

is less dependent on the lateral dimensions (and hence

de-lay) of their components, a key advantage of this approach is

its ability to operate at higher frequencies early in the

nology life cycle However, improvements in transistor

tech-nology steadily encroached on the high-frequency reserve of

parametric circuits thus marginalizing this advantage Since

more remote regions of the spectrum were better

accommo-dated by maser and laser amplifiers, a loss of interest in the

parametric circuit approach followed

Today, as personal commercial communications

applica-tions migrate to more exotic frequency domains, a niche for

the parametric circuit may resurface This may especially be

the case for low-profile millimeter wave electronics intended

for dense sensor or distributed network applications Size

and power constraints exclude many of today’s molecular

amplifiers (although integration progress has been

substan-tial [10]) from consideration while performance, power, and

approaching physical limits have relegated millimeter wave

applications to the domain of expensive IC technologies

3 PARAMETRIC CONVERSION: TECHNICAL REMARKS

Conventional electronic transistor amplifiers operate by

us-ing a small signal to modulate the resistance of a switch that,

in turn, mediates the coupling between a large DC supply

and a load Amplification is achieved because the coupling

is proportional to the small input signal and is efficient

be-cause, ideally, the supply does not influence the modulated

resistance Alternatively, parametric amplifiers utilize a

non-linear reactance (in this paper we consider only capacitive

re-actances) through which an AC supply “energizes” a small

signal More specifically, a small signal deposits charge on a capacitor An AC “pump” increases the potential energy of this charge by increasing the capacitance, the pumped charge

is then siphoned off to a load

Immediately it is apparent that by foregoing resistive cou-pling such an amplification principle sidesteps, at least in part, thermal fluctuations and holds inherent noise behavior advantages A handy “existance theorem” of sorts for para-metric converters is available in the form of the Manley-Rowe relations [11]

∞



m =0

∞



n =−∞

mP m,n

m f s+n f p =0,

∞



n =0

∞



m =−∞

nP m,n

m f s+n f p =0

(4)

The ideal circuit used to derive the Manley-Rowe relations is shown inFigure 1 These relations constrain the power,P m,n, absorbed by a nonlinear capacitor at frequenciesm f s+n f p

that is driven by two sources operating at frequencies f s(the signal source) and f p (the pump source) The relations are fundamental in that they are based on the principle of en-ergy conservation (zero total average power flowing into the capacitor) and are independent of the capacitance-voltage (CV) characteristics (aside from assuming no hysteresis in the voltage); the relations are limited in that they do not ac-count for losses in the varactor which have a substantial im-pact on practical implementations

The raw circuit performance encapsulated by Manley-Rowe relations needs to be constrained in order to realize practical functions like upconversion (signal at f samplified and mixed to higher frequencies) or downconversion (sig-nal atf samplified and mixed to lower frequencies) or simply straight amplifiers (signal atf samplified atf s) The common way of doing this is to encase the capacitance in a multimode cavity From a lumped circuit perspective, this means con-necting the capacitance to some assembly of resonators

3.1 Upper-sideband upconverter

We imagine the nonlinear capacitor locked in a resonant con-figuration that allows power to flow only at frequencies f s,f p, and f u = f s+f p For this scenario equation (4) is simplified to

P1,0

f s + P1,1

f s+f p = P s

f s +P u

P0,1

f p

+ P1,1

f s+ f p = P p

f p

+P u

As stated earlier the pump is our energy source in this circuit,

it is responsible for a positive power flow,P p, into the capaci-tor According to (6) this means that the power,P u, at f umust

be negative, hence flowing out of the capacitor and available

E s

Figure 1: The ideal parametric converter used to derive the Manley-Rowe relations Ideal impedance filters allow only a single tone to flow through any one branch

to a load From (5) the circuit has the operating power gain

Gup= P u

P s = f u

A more physical description of USBUC operation may

shed more light on its behavior The potential energy of the

charge that a small signal deposits on a capacitor can be

in-creased by separating that charge Work is needed to do this

and this work is periodically supplied from a pump circuit

Under this condition, when a load extracts this charge from

the capacitor, it will have access to higher energy carriers

Gain is achieved However, the work used to energize the

mediating capacitor increases the energy needed by the

in-put signal to charge it again Thus, the circuit is naturally at

an advantage when pumping and energy extraction are done

quickly compared to the dynamics of the signal input (i.e.,

when the capacitor signal is oversampled)

Thus the higher the output frequency (hence pump),

the greater the circuit gain This configuration, the

upper-sideband upconverter (USBUC), is well suited for

high-frequency transmission For instance, under ideal conditions,

converting a 6 MHz signal to a 60 GHz carrier promises a

40 dB operating power gain making the circuit more

attrac-tive for millimeter wave applications Note that, under the

ideal described by (5) and (6) (i.e., lossless varactor and

perfect resonator), the gain is completely independent of

the pumping power Analysis and simulations of the impact

wrought by varactor losses on circuit gain are presented in

Section 5 Of course the maximum available output power is

limited by the size of the input and pump signals For a small

input signal and f u  f swe have a maximum output power

of approximatelyP p /2 hence an efficiency of 50% As f s

in-creases the efficiency improves, but the gain drops

Accounting for losses in the surrounding filter (cavity)

network by itself does not directly influence the ideal gain

prediction Rather, as highlighted by Rowe [12], the

band-width of the converter is compromised Assuming that the

pump’s action on the nonlinear varactor introduces a

time-varying incremental capacitance between the USBUC’s f s

and f uports of

Cpump(t)=

∞



n =−∞

C n e j2πn f p t (8)

the bandwidth to signal-frequency ratio (γup/ f s) becomes [12]

γup

f s = C1

C0



2f u

Returning to the previous example, to accommodate a signal

of 10 MHz bandwidth converted from a 6 MHz to a 60 GHz center frequency requires aC1/C0ratio of less than 1/80 This bodes extremely well for the pump For a well-designed MOS varactor it is not unreasonable to expect a 50% variation aroundC0, that is, assuming the common empirical MOS model we expect

CMOS= C0+C0

2 tanh

3

2vpump

≈ C0+3C0

4 vpump, (10) where the latter approximation is based on the assumption of

a small pump voltage This is confirmed by the smallC1/C0

requirements of our example From (9) and (10), a peak-to-peak pump voltage of only 16 mV is needed to sufficiently perturb the varactor so that a 10 MHz bandwidth is estab-lished This must be tempered with the fact that in this case the pump needs to operate at 60 GHz which is not out of the question for production level technologies (albeit a sig-nificant stretch for CMOS) exploiting distributed operation [13], frequency doubling [14], or second-harmonic gener-ation [15] Further, it is possible to redesign the pumping scheme of the parametric converter to continue meeting the Manley-Rowe predictions while operating with a pump at lower frequencies This is discussed inSection 3.3

The benefits available to the USBUC become serious im-pairments when considering this topology for a receiver’s downconversion block The substantial gain available to the upconverter (7) becomes a tremendous loss as, naturally,

f u  f sfor downconverters Fortunately, a large variety in parametric conversion topologies exists, some of which do allow for gain in the downconversion arrangement One such topology is discussed presently

3.2 Lower-sideband downconverter

The lower-sideband downconverter (LSBDC) is one para-metric topology capable of amplifying a signal mixed down

to the intermediate frequency (IF) or baseband (BB) In this

case, the converter’s cavity is aligned such that power only

at f s (the RF signal), f p, and f d = f p − f s (the

down-converter signal) can flow through the circuit To obtain a

low-frequency output, the constraints f p > f s (otherwise

an upper-sideband downconverter is realized) and f p < 2 f s

(otherwise a lower-sideband upconverter (LSBUC) is

real-ized) must hold Returning to the Manley-Rowe relations we

get

P1,0

f s

+ P1,−1

f s − f p = P s

f s − P d

f d =0, (11)

P0,1

f p

+ P −1,1

− f s+ f p = P p

f p

+P d

f d =0 (12) Adding (11) and (12) results in

P p

f p

+P s

which, given that the pump power flows into the circuit,

im-plies that power emerges from the converter’s input (signal)

port despite an input signal being fed into the receiver (e.g.,

from an antenna) Hence, the impedance of the LSBDC’s

sig-nal port is negative Similarly, (12) states that the pump

en-ergy causes power to emerge from the downconversion port

as well Being related to the power emerging from the

sig-nal port (see (11)) this implies that the downconversion port

impedance is also negative The LSBDC doubles as a

reflec-tion amplifier

The operation of this circuit can be summarized as

fol-lows The pump generates the highest frequency “signal” in

the circuit Thus, unlike the USBUC, on average it can couple

power from the signal port (RF) to the downconversion port

(IF) and vice versa As with the USBUC, the power coupling

and amplification is mitigated by work done by the pump in

changing the varactor capacitance Since the pump switches

only slightly faster than the signal, it transfers a relatively

small amount of the input power into the downconversion

port’s IF frequency However, being much higher than IF, the

pump taps, amplifies, and converts a great deal of the IF back

to RF (as predicted by (11)) Part of the larger input signal is

then tapped once again by the pump and fed into the

down-conversion port A positive feedback is established and the

circuit functions as a regenerative amplifier Thus the pump

power emerges as RF and IF frequencies from the

respec-tive ports which now have a negarespec-tive input resistance The

more power that is pumped into the circuit is, the higher the

quality factor,Q, of the RF and IF modes is Thinking of the

input as a forcing signal on these modes we can

automati-cally see that the higher theQ, the higher the signal gain, but

the lower the bandwidth Nonetheless, for signals centered

around millimeterwave carriers, the LSBDC topology has a

lot of relative bandwidth performance to sacrifice What is a

drawback to this circuit, however, is that an excess of pump

power leads to instabilities (overcompensation of loss) and,

simultaneously, a greater sensitivity to component variations

(thus increasing the likelihood of instability) However, the

advantage remains the potentially low-noise behavior about

which the Manley-Rowe relations say nothing We return to

this inSection 5

BB

USBUC

RF

Figure 2: A simple transmit chain employing the USBUC

3.3 Parametric transmit and receive chains

How can parametric converters be assembled into the transceiver chain? Since they combine oscillator, mixer, and amplifier functions under essentially one circuit, they hold the potential to form the basis for a diverse set of radio sys-tems

Perhaps the most straightforward application is the use of

an USBUC as a low-voltage upconverter of BB or IF signals to millimeter RF For minimal complexity and power consump-tion, the design inFigure 2can be used This diagram sug-gests interfacing the USBUC directly to the antenna which,

if the antenna is sufficiently narrowband, can serve as the upper-sideband bandpass filter Employing a standard two-terminal varactor structure in this topology will impose ex-tra gain limiting—significant upconverted signal amplitudes can induce lower-sideband signals to flow (i.e.,ω p − ω s) thus returning power back to the input source A simple alterna-tive is to use the USBUC as an upconverting mixer and pre-amplifier and leave the final millimeter wave amplification to

a dedicated high-frequency (and high-cost) power amplifier Alternatively, a double-balanced varactor structure (as de-scribed inSection 4.3in the context of VCO frequency con-trol) can be used in an attempt to desensitize the varactor ca-pacitance to variations in the upconverted signal frequency Another transmitter topology shown inFigure 3 incor-porates a degenerate local oscillator (LO) in a heterodyne US-BUC architecture In this case, the gain of the USUS-BUC is dis-tributed over several stages The benefit of such a partition

is reaped by the pump which can potentially be generated

in a staged fashion as well InFigure 3the staged pump is built out of degenerate parametric converters In degenerate converters, the signal (i.e., the LO) acts simultaneously as the input and the pump A self-mixing occurs which naturally results in a signal at twice the input frequency As shown, two such stages attached back-to-back can produce a signal

at four times the driving pump frequency (with the need of a high power output atω p) and be combined with a multistage USBUC to gradually upconvert a signal fromω sto 7ωp+ω s Since parametric circuits couple power from low to high frequencies, the receiver’s downconversion function obvi-ously poses a problem As already described, the LSBDC gets around this by employing positive feedback which can give substantial gain at the expense of sensitivity A possible re-ceiver topology employing a LSBDC is shown in Figure 4 Since the circuit functions as a reflection amplifier for both

RF and IF frequencies, a circulator is included to prevent

BB ω s

USBUC

RF

LO

Degenerate

Figure 3: Multistage USBUC transmitter with degenerate pump

RF

LSBDC

IF

ADC

ADC

Figure 4: Receive chain using a LSBDC as a mixer and amplifier

re-radiation and help maintain stability A number of

op-tions are available even within the basic LSBDC receiver

Most simply it can be treated as a low-noise amplifier (LNA)

and the amplified RF signal tapped out of the circulator to the

remainder of the radio In this case we benefit simply from

the large gain and low-noise performance of the

paramet-ric converter Any standard downconversion architecture or

subsampling techniques can be employed afterwards

Com-pared to integrated transistor LNAs operating in the

mi-crowave region this benefit is marginal at best However, at

millimeter wave frequencies the improvements for

amplifica-tion, noise, and power consumption become marked (at least

compared to production-level CMOS technology) Using the

downconversion port is another possibility, in this case

tak-ing advantage of the LSBDC’s conversion properties

along-side its low-noise performance The difficulty in this case is

gain, as the downconversion gain is increased, the

regenera-tive design becomes difficult to stabilize under practical

con-ditions

An obvious issue with parametric converters is the high

pump frequency needed to transfer power As a result, a

number of high-frequency pump generation and conversion

techniques have already been mentioned Another approach

is to reconfigure the varactor structure for subharmonic

pumping Subharmonic pumping refers to an arrangement

in which a certain pumping frequency transfers energy at the

same rate as would a higher pumping frequency

The subharmonic pumping suggestion does not pose an

immediate violation of the Manley-Rowe relations Rather,

one means of its realization is to simply utilize one of the

higher pumped capacitance harmonics [16] Herein, the

more abrupt MOS CV characteristics (compared to the junc-tion varactor) can be of substantial benefit For example, imagine a varactor pumped such that part of its Fourier se-ries expansion from (8) is

C A(t)= · · ·+C −2 e − j2ω p t+C −1 e − jω p t+C0+C1e jω p t

+C2e j2ω p t+· · ·

(14) Another varactor,C B, pumped 180◦ out of phase relative to

C Acan be described with

C B(t)= · · ·+C −2 e − j2(ω p t+π)+C −1 e − j(ω p t+π)+C0

+C1e j(ω p t+π)+C2e j2(ω p t+π)+· · · (15)

CombiningC AandC B,

C A(t) + CB(t)= · · ·+C −2 e − j2ω p t+ 2C0+C2e j2ω p t+· · ·,

(16) leads to a net capacitance variation occurring at twice the actual pump rate The schematic of a differentially driven subharmonic scheme based on this approach is shown in

Figure 5 For subharmonic pumping to actually work here the varactors,C AandC B, must both have the same terminal (either gate or source) connected to the circuit proper Aside from exciting the second harmonic, the differential pump-ing scheme allows the circuit to operate without a dedicated pump filter despite the use of two-terminal varactors Al-ternatively, if the orientation of one varactor is flipped (i.e., terminal connections reversed or a complementary structure used) the subharmonic pumping effect is removed The ben-efit of this connection, however, is the isolation of any pump frequencies from the signal and output ports allowing the fil-tering at these terminals to be significantly relaxed

A more extreme attempt at subharmonic pumping em-ploying a four-phase excitation scheme is sketched inFigure

6 In this case a ring oscillator (an injection locked oscillator can be used for better purity) generates differential in-phase and quadrature signals Altogether four pump signals offset

by 90◦are available Each pumping signal is sent to a separate varactor with CV characteristics identical to the other three Given sufficiently nonlinear (i.e., abrupt) CV characteristics

Di fferential pump

+

+

+

Signal source

Figure 5: A differential subharmonic pumping scheme

0 Æ

180 Æ

90 Æ

270 Æ

Figure 6: A possible four-phase subharmonic pumping scheme

the net capacitance seen between the signal (ωs) and

upcon-version (ωu) terminals of the varactor will vary at four times

the injected pumping frequency Of course, at this harmonic,

a large degradation in capacitance can be expected

compro-mising the benefit of low pumping frequencies

4 VARACTOR STRUCTURES

Since the late 1950’s the junction diode has served as the de

facto standard for all electronic parametric amplifiers

How-ever, in parametric structures, and for oscillator frequency

control, the junction diode is generally inferior to MOS

var-actor structures Since the most vigorous research on

elec-tronic parametric circuits predates the rise of MOS

technol-ogy, they have only sporadically been considered in the

con-text of modern electronic technologies (and their

applica-tions); [9] is a rare example In this section we look closer

at the key varactor characteristics and design options for RF

frequency control and parametric conversion

4.1 Elastance model

An important advance in customized MOS varactor

technol-ogy for RF applications was taken when CMOS processes

n-well

Figure 7: A sketch of an n-type (referring to the body doping)

accumulation-mode varactor’s cross-section

began to accommodate the accumulation-mode varactor [17,18] (Figure 7) This simplified the device bias scheme

as compared to the more common inversion-mode varac-tor and simultaneously lowered its resistive losses and para-sitic contributions As a frequency tuning element the advan-tages of the accumulation-mode varactor compared to the junction diode were clear, a largeCmax/Cminratio, an abrupt capacitive transition implying only the need for low tuning voltages, an isolated bias scheme, and acceptable Q

Opti-mization of these characteristics for LC-VCOs are straight-forward: one must increase the Cmax/Cmin, and reduce re-sistive losses For parametric circuits a more detailed assess-ment is necessary

First, unlike Manley-Rowe, a more accurate analysis of parametric circuit behavior must account for losses in the varactor To this end a rough but physically realistic pumped varactor model employs a nonlinear capacitance in series with a resistance,R s As emphasized by Penfield and Rafuse [19] this varactor model sidesteps the difficulties and inac-curacies that emerge when a parallel RC equivalent is used

or when the series resistance is incorporated into source and load impedances The terminal characteristics of this physi-cally motivated model are best described with the relation

v(t) =

S(t)i(t)dt + R s(t)i(t) (17) This equation directly catalogues the influence of the pump voltage on the varactor as a whole However, it contains a rel-atively obscure varactor measure, the incremental elastance,

S(t).1 A rough approximation of a MOS varactor elastance per unit area is given by

S

V GS



= Q sd



V GS



e  s N d + 1

whereC oxis the oxide capacitance,e is the electronic charge,

 sis the permittivity of the semiconductor,N d is the donor

1 For the remainder of the paper we refer toS(t) as simply the elastance,

with the incremental properties of this value remaining implicit As with the capacitance of nonlinear devices, practical measurement techniques allow the extraction of only incremental properties.

doping in the semiconductor (a uniformly doped n-type

accumulation-mode varactor is assumed), andQ sdis the

de-pletion charge in the semiconductor body The dede-pletion

charge itself is modeled semi-empirically with

Q sd = e  s

C ox N d

1 +4VMOS

γ2 −1



whereγ is the device body factor and

VMOS=1

2



V GS − V FB

2

+δ −V GS − V FB



. (20) The above follows a modeling technique reported in [20]

and, as in that work, incorporates a small smoothing factor,

δ This correction is used since the transition from full

accu-mulation to flat-band is not rigorously accounted for here

With such factors present it is best to consider this model as

a rough design guide A detailed account of the varactor

de-vice physics in compact model form is described in [21] for

example The value of the simple model described here lies in

its direct exposure of the relations between performance and

device characteristics.Section 4.2discusses this, along with

device losses, in detail

A comparison of this approximation to the normalized

CV and SV characteristics extracted from a full charge-based

analysis [22] as well as a simple tanh curve fit is presented

inFigure 8 As shown, the tanh curve, a popular approach in

empirical compact CV models, underestimates the elastance

in depletion We return to this point inSection 4.2

4.2 Figures of merit

The elastance characteristics must be considered along with

device losses in estimating the impact of integrated MOS

technology on parametric performance Penfiled and Rafuse

[19] highlighted two figures of merit, the cutoff frequency

f c = Smax− Smin

and the modulation ratio

m n = | S n |

Smax− Smin. (22) The cutoff frequency, which we can express in more familiar

varactor measures as

f c = Cmax− Cmin

2πRs CmaxCmin

reflects only the influence that device properties bear on the

circuit Ideally, f c marks the maximum frequency at which

it is worth pumping the capacitor Conversely, the

modula-tion ratio encompasses several contribumodula-tions The

numera-tor,| S n |, indicates the size of the elastance harmonic at the

pumping frequencyn · f p That is, assuming small-signal

con-ditions, we can treat the elastance as a linear time-varying

component controlled by the pump

S(t) =

∞



n =−∞

S n e j2πn f p t (24)

This is the elastance analog to (8) The elastance harmonics are influenced by three things: the bias of the pumping sig-nal, the amplitude of the pumping sigsig-nal, and the steepness

of the varactor’s elastance characteristics The steeper the SV curve is, the more efficient the pump is in relaying its energy

to the varactor As shown in (18) and (19) a large impact on the abruptness of the elastance characteristic can be made by reducing the channel doping This necessarily increases the series losses, but at a rate proportional toN d, while the SV slope increases withN2

d Similarly, we can see from (19) that

a decrease in the gate capacitance per unit area,C ox, also con-tributes to an improvement in the SV slope This also comes with the benefit of allowing larger pumping signals to be ap-plied across the gate oxide

These relationships run in a direction counter to the changes employed in scaling MOS devices Nonetheless the variety present in most modern MOS technologies presents some room for optimization For instance, many CMOS pro-cesses offer devices of various oxide thickness and channel doping A plot of the SV characteristics extracted from S-parameter measurements on accumulation-mode devices in

a 0.13 μm-CMOS technology with varying channel doping and oxide thickness is shown inFigure 9 In this case only devices with a marginal difference in oxide thickness were examined As expected, a lower channel doping results in a steeper SV characteristic The measured 4-to-1 ratio between

Smax andSmin is about 2.5 times greater than that available from a junction diode The two channel doping levels (nom-inal and high) are obtained by employing threshold adjust implants intended for the variety of NMOS and PMOS de-vices offered in the technology Unfortunately, a fourth ex-periment employing one of the available counterdoping im-plants and intended to have the lowest channel doping was not correctly processed at the foundry This, correctly com-bined with the thick-oxide option available in most CMOS technologies, constitutes the most direct approach to device customization for parametric circuit applications

Of note in the measurement results is the manner in which the elastance characteristic saturates in the depletion region This is a characteristic encompassed by the tanh fit example included in Figure 8 but not the basic model of (18) The disparity between the predicted and measured elas-tance characteristics at large depletion bias can be traced

to the fact that the varactor measurements were done with

a small-signal, high-frequency (5 GHz) perturbation atop a slowly stepped bias—a common high-frequency CV extrac-tion technique [23] Such a set-up allows minority charge

to respond to the bias settings thus preventing the onset

of deep depletion as naturally included by the basic model However, in parametric circuit applications we can expect a large-signal, high-frequency pump voltage to continuously excite the MOS varactor Thus, the equilibrium bias condi-tions present during measurement hardly apply for pumped varactors This supports the elastance predictions of the basic varactor model, but a convincing answer requires an analysis beyond the scope of this paper

As highlighted by the merit relations, SV performance alone is not a sufficient device selection criterion Careful

tanh fit

Full charge model

Approximate model

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

C ox

(a) Capacitance-voltage characteristics

tanh fit Full charge model Approximate model

1

1.5

2

2.5

3

3.5

4

4.5

5

(b) Elastance-voltage characteristics

Figure 8: Comparing the rough semi-empirical model to a complete charge-based description and a tanh fit

High doping, nominalt ox

Nominal doping, lowt ox

Nominal doping andt ox

0.4

0.6

0.8

1

1.2

1.4

1.6

Figure 9: Elastance measurements for accumulation-mode

varac-tors with varying degrees of channel doping in a 0.13 μm-CMOS

technology

consideration must be given to the reduction of series

losses as attested by (23) For designers, with little control

over the varactor’s physical characteristics, layout becomes

paramount here Without considering special layout

tech-niques (such as differential excitation [24]), four controls are

available: gate length (Lg), gate width (Wg), finger number

(Nf), and number of stripes/segments (Ns) These combine

to give an active varactor area ofL g · W g · N f · N s To clarify, a varactor consists ofN sstripes in parallel, each containingN f

fingers, in turn, each finger has dimensionsW g andL g We must consider what arrangement of these terms maximizes

f c This requires finding the right balance between layout in-fluence on series resistance and capacitance properties The series resistance can be divided into two main con-tributors, one is a constant value and is associated with the silicided poly gate, contacts, and via resistance on the ter-minals The other contributor is associated with the channel material and is bias, doping, and frequency dependent For the accumulation-mode varactor with one finger, its series RC components can be modeled as inFigure 10, where

R cg andR csd are the contact and via resistances on the poly gate and n+ diffusion pickups (source/drain), respectively, andR gis the gate polysilicon resistance Underneath the gate, the channel resistance is denoted byRch, whileR wis the resis-tance of then+diffusion bulk pickups and the well Cvaris the equivalent series capacitance of each finger The model of the varactor with multiple fingers is shown inFigure 11, where

R s f gandR s f sdare the series resistance between two fingers For the gate resistance, if the gate poly of each finger is joined from both sides of source/drain, the equivalent poly resistance of one finger is

R g = 1

12· W g

L g · R g −sh, (25) whereR g −shis the gate’s sheet resistance On the other hand, for the channel and well resistance we have

Rch,R w∝ L g

W · Rch,w −sh (26)

Gate R cg R g Cvar

Figure 10: Model of a single-finger varactor

R s f g R cg R g Cvar

R csd R s f sd

R s f g R cg R g Cvar

R csd R s f sd

.

.

.

Figure 11: Model of a parallel multiple-finger varactor

Being lower doped and unsilicided, the sheet resistance of the

well and bulk, Rch,w −sh, is greater than that of the

polysili-con This suggests that one would use the minimum

chan-nel length to reduce the body contribution to the series

re-sistance However, due to their inverse dependence on finger

dimensions some tradeoff between the influence of (25) and

(26) on the series resistance is present This tradeoff affects

the setting forW g andL g, but it is not the only

considera-tion

As shown in (23) we want to maximizeCmax, minimize

Cmin, and minimize R s Somewhat arbitrarily choosing a

minimum practical value ofCmin=100 fF (in anticipation of

parasitic effects and process variations) we are left to consider

howL g,W g,N f, andN sinfluence the remaining two

charac-teristics, obviously this complicates selection based purely on

anR g-Rchtradeoff For instance, minimizing L g · W g

maxi-mizes theN f · N sproduct and therefore reducesR s, but at the

cost of increasing the relative parasitic capacitance

contribu-tion and hence a reduccontribu-tion inCmax− Cmin

Another important consideration is the contact and

in-terconnect resistance introduced between fingers (Rs f g and

R s f sd in Figure 11) and stripes This is often ignored when

assessing device resistance, but can certainly be influential

WithR s f g andR s f sdthe equivalent resistance will not be

re-duced simply as a function of 1/Nf AsN f is increased the

series resistance will eventually saturate due to the

contribu-tions of the interfinger conneccontribu-tions,R s f gandR s f sd

Getting a sense of how the characteristicsL g, W g,N f,

andN sinfluence f cis greatly aided by the availability of

ver-ilogA based compact models such as the one described in

[21] Since these models account for both physical and

lay-out characteristics a broad comparison between designs can

Table 1: Cutoff frequencies for varactor with Wg = 1μm, L g =

0.24 μm, and area=43.2 μm2

N f N s Cmax(f F) Cmin(f F) R s(Ω) f c(GHz)

Table 2: Cutoff frequencies for varactor with Wg =1.41 μm, L g =

0.34 μm, and area=43.2 μm2

N f N s Cmax(f F) Cmin(f F) R s(Ω) f c(GHz)

Table 3: Cutoff frequencies for varactor with Wg = 2μm, L g =

0.48 μm, and area=43.2 μm2

N f N s Cmax(f F) Cmin(f F) R s(Ω) f c(GHz)

be made Employing empirically based compact models the

f cfor a variety of accumulation-moden-type varactors

(ex-cited in a single-ended manner) is shown in Tables1 3 The total active area (Lg · W g · N f · N s =43.2 μm2) is the only value that all designs have in common It is chosen such thatCmin remains above 100 fF over the relevant region of operation (VGS ranges from−1 V to 1 V).Table 1 summa-rizes the results for varactors consisting of minimum unit area (i.e.,W g · L g) elements,Table 2shows the results for de-vices composed of twice the minimum unit area, andTable 3

summarizes the characteristics of varactors composed of four times minimum unit area elements Note that all R s have been calculated for 5 GHz excitations A layout dependent self-resonance frequency could not be extracted as the model did not account for inductive parasitics although it should be noted that self-resonant frequencies do not necessarily pose a problem for parametric circuits The self-resonant frequency can be exploited as one of the modes of interest in the para-metric circuit

The f cvalues shown are certainly optimistic as the com-pact models do not account for the effects that would limit device performance at such frequencies, nevertheless they are useful as a relative measure of the best device type Judging

by thef cresults, it is best to use an intermediate unit area that ably juggles two conflicting characteristics: parasitic capaci-tance and series resiscapaci-tance For a given total area, as the unit

W g =2μm, L g =0.48 μm

0

200

400

600

800

1000

1200

f c

Figure 12: Plot of varactor cutoff frequencies versus number of

stripes for a 43.2 μm2(total active area) varactor

area shrinks, more devices in parallel imply a smaller total

resistance As can be seen in all cases, this is best achieved

by keeping N f and N s on the same order Unfortunately,

the capacitance of small unit areas contains a higher relative

proportion of parasitic capacitance This lowersCmax− Cmin

which ends up hurting the f c Attempts to get around this by

increasing the unit area will be frustrated by an increase in

series resistance simply due to a decrease in the parallel

con-nection count The simulated cutoff frequencies associated

with these varactors are plotted inFigure 12as a function of

stripe count As can be seen, f cis relatively forgiving of unit

size, but quite sensitive toN f andN sdistributions

Measured results are available to double-check the CV

characteristics of the scalable varactor model The

experi-mental varactor design has unit widths and lengths of 5μm

and 0.42μm, respectively, which are arranged into N s = 5

parallel stripes ofN f = 20 gate fingers each InFigure 13,

the CV curve obtained from the model is plotted

along-side the CV data obtained from a high-frequency (5 GHz)

S-parameter characterization of the varactor It is observed

that the CV characteristic of the fabricated device matches

very closely with the scalable model (at the frequency of

ex-traction)

We will attempt to tailor this varactor design for

para-metric circuits by changing the number of stripes from 5 to 1

The implications of this change on the device characteristics

and USBUC and LSBDC are explored in detail inSection 5

Even though reducingN swill shift the CV curve down and

decrease theCmax− Cmin (as shown inFigure 13),Cminhas

also been reduced thus increasing f c The large change in

ca-pacitance characteristics fromN s = 5 toN s =1 affects the

performance quality of the parametric converter but not the

substance of its operation, unlike, for example, that of a VCO,

whose center frequency and tuning range would be severely

N s =1: model

N s =5: measurement

N s =5: model

0

0.5

1

1.5

2

2.5

Figure 13: Comparison of measurement results to compact model predictions

+

+

Figure 14: Schematic of common-mode cancellation varactor

impacted The only requirement imposed in this work is that

Cminexceed 100 fF, which has been satisfied

4.3 Composite structures

Besides refining layout, useful varactor customization can be achieved by connecting devices for optimal excitation An example of this is the work reported in [24] where varac-tors subject to differential excitation (e.g., in a differential VCO) profit from a virtual ground connection which re-duces the effective series losses Another possibility is the common-mode rejection architecture [25] In this case, var-actors are arranged such that they respond symmetrically to differential excitations, but in an antisymmetrical manner to common-mode excitations thus damping the latter’s influ-ence This can be useful for both parametric converters (al-lowing large signal operation) and VCOs (removal of supply disturbances) A discussion of the latter is given inSection 6

A schematic of the proposed varactor circuit is shown

inFigure 14 In effect, this arrangement resembles the basic

Of... and high) are obtained by employing threshold adjust implants intended for the variety of NMOS and PMOS de-vices offered in the technology Unfortunately, a fourth ex-periment employing one of