Bài tập thiết kế logic số hay
Trang 11.Bộ MUX 8-1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux_v3 is
port(
D_in : in std_logic_vector(7 downto 0);
sel :in std_logic_vector (2 downto 0);
y :out std_logic );
end Mux_v3;
architecture Behavioral of Mux_v3 is
begin
with sel select
y <= D_in(0) when "000",
D_in(1) when "001",
D_in(2) when "010",
D_in(3) when "011",
D_in(4) when "100",
D_in(5) when "101",
D_in(6) when "110",
D_in(7) when others;
end Behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_mux_v2 IS
END test_mux_v2;
ARCHITECTURE behavior OF
test_mux_v2 IS
COMPONENT MUX_8V2
PORT(
D_IN : IN std_logic_vector(7 downto
0);
SEL : IN std_logic_vector(2 downto
0);
Y_OUT : OUT std_logic
);
END COMPONENT;
signal D_IN : std_logic_vector(7
downto 0) := (others => '0');
signal SEL : std_logic_vector(2 downto
0) := (others => '0');
signal Y_OUT : std_logic;
BEGIN
uut: MUX_8V2 PORT MAP (
D_IN => D_IN,
SEL => SEL,
Y_OUT => Y_OUT
);
D_in<="11001001";
sel <=”000”, ”001” after 20ns, “010”
after 40ns, “011” after 60ns, “100” after
80ns;
END;
2.Bộ DEMUX 1-8
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Demux_v1 is Port ( D : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0));
end Demux_v1;
architecture Behavioral of Demux_v1 is begin
process(D,Sel) begin case (sel)is when "000"
=>y<=(0=>D,others=>‟0‟);
when "001"
=>y<=(1=>D,others=>‟0‟);
when "010"
=>y<=(2=>D,others=>‟0‟);
when "011"
=>y<=(3=>D,others=>‟0‟);
when "100"
=>y<=(4=>D,others=>‟0‟);
when "101"
=>y<=(5=>D,others=>‟0‟);
when "110"
=>y<=(6=>D,others=>‟0‟);
when others
=>y<=(7=>D,others=>‟0‟);
end case;
end process;
end Behavioral;
Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_dmuxv1 IS END test_dmuxv1;
ARCHITECTURE behavior OF test_dmuxv1 IS
COMPONENT Demux_v1 PORT(
D : IN std_logic;
sel : IN std_logic_vector(2 downto 0);
Y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal D : std_logic := '0';
signal sel : std_logic_vector(2 downto 0) := (others => '0');
signal Y : std_logic_vector(7 downto 0);
BEGIN uut: Demux_v1 PORT MAP (
D => D, sel => sel,
Y => Y );
D<='1', „0‟ after 30ns, „1‟ after 60ns, „0‟
after 80ns, „1‟ after 200ns;
sel<="000", “001” after 100ns;
END;
3.Giải mã BCD-7Seg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_7seg is Port ( input : in STD_LOGIC_VECTOR (3 downto 0);
output : out STD_LOGIC_VECTOR (6 downto 0));
end BCD_7seg;
architecture Behavioral of BCD_7seg is begin
output<="1111110" when input = x"0"
else "0110000" when input = x"1" else "1101101" when input = x"2" else "1111001" when input = x"3" else "0110011" when input = x"4" else "1011011" when input = x"5" else "1011111" when input = x"6" else "1110000" when input = x"7" else "1111111" when input = x"8" else "1111011" when input = x"9" else "1110111" when input = x"A" else "0011111" when input = x"B" else "1001110" when input = x"C" else "0111101" when input = x"D" else "1001111" when input = x"E" else "0000001" ;
end Behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_BCD IS END test_BCD;
ARCHITECTURE behavior OF test_BCD IS
COMPONENT BCD_7seg PORT(input : IN std_logic_vector(3 downto 0);
output : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
signal input : std_logic_vector(3 downto 0) := (others => '0');
signal output : std_logic_vector(6 downto 0);
BEGIN uut: BCD_7seg PORT MAP ( input => input,
output => output );
input <= x"0",x"1" after 10 ns ,x"3" after
30 ns ,x"4" after 50 ns ; END;
4.Mã hóa n-to-2 n với n=3
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use
IEEE.STD_LOGIC_UNSIGNED.ALL; Entity encoder_n_2n is
Port (X: in STD_LOGIC_VECTOR (2 downto 0);
Y: out STD_LOGIC_VECTOR (7 downto 0); End encoder_n_2n;
Architecture Behavioral of encoder_n_2n
is Begin Y<=”00000001” when (X=”000”) else “00000010” when (X=”001”) else “00000100” when (X=”010”) else “00001000” when (X=”011”) else “00010000” when (X=”100”) else “00100000” when (X=”101”) else “01000000” when (X=”110”) else “10000000”;
End behavioral;
TestBench
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL; Use
IEEE.STD_LOGIC_UNSIGNED.ALL; Use IEEE.NUMERIC_STD.ALL; Entity test_encoder_n_2n is End test_encoder_n_2n;
Architecture behavior of test_encoder_n_2n is Component encoder_n_2n Port (X: in std_logic_vector (2 downto 0);
Y: out std_logic_vector (7 downto 0)
);
End component;
Signal X: std_logic_vector (2 downto 0) := (others => „0‟);
Signal Y: std_logic_vector (7 downto 0); Signal clk: std_logic :=‟0‟;
Begin Uut: encoder_n_2n PORT MAP(
X=>X, Y=>Y );
Clk<=not clk after 1ns;
Process (clk) Begin
Trang 2If (clk‟event and clk=‟1‟) then
X<=X+1;
End if;
End process;
End;
5.Mã hóa ưu tiên 8-3 hoạt động ở mức
tích cực cao
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use
IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity uutien_encoder is
Port (y: in std_logic_vector (7 downto
0);
Z: out std_logic_vector (2
downto 0);
End uutien_encoder;
Architecture behavioral of
uutien_encoder is
Begin
Process (y)
Begin
If y(0)=‟1‟ then z<=”000”;
Elsif y(1)=‟1‟ then z<=”001”;
Elsif y(2)=‟1‟ then z<=”010”;
Elsif y(3)=‟1‟ then z<=”011”;
Elsif y(4)=‟1‟ then z<=”100”;
Elsif y(5)=‟1‟ then z<=”101”;
Elsif y(6)=‟1‟ then z<=”110”;
Elsif y(7)=‟1‟ then z<=”111”;
End if;
End process;
End behavioral;
TestBench
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use
IEEE.STD_LOGIC_UNSIGNED.ALL;
Use IEEE.NUMERIC_STD.ALL;
Entity test_encoder_uutien is
End test_encoder_uutien;
Architecture behavior of
test_encoder_uutien is
Component encoder_uutien
Port (Y: in std_logic_vector (7 downto
0);
Z: out std_logic_vector (2
downto 0)
);
End component;
Signal Y: std_logic_vector (7 downto 0)
:= (others => „0‟);
Signal Z: std_logic_vector (2 downto 0);
Begin
Uut: uutien_encoder PORT MAP(
Y=>Y,
Z=>Z
);
Y<=”00001110”;
End;
6.Bộ tính toán số học ALU cơ bản dùng các toán tử trong VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_dongian is Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
cin : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end ALU_dongian;
architecture Behavioral of ALU_dongian
is signal y_lg,y_art:std_logic_vector(7 downto 0);
begin ALU_unit: process(sel,a,b) begin
case sel is when "0000"=>y_lg<= not a;
when "0001"=>y_lg<= not b;
when "0010"=>y_lg<= a and b;
when "0011"=>y_lg<= a or b;
when "0100"=>y_lg<= a nand b;
when "0101"=>y_lg<= a xor b;
when "0110"=>y_lg<= a nor b;
when "0111"=>y_lg<= a xnor b;
when "1000"=>y_art<= a;
when "1001"=>y_art<= a+1;
when "1010"=>y_art<= a -1;
when "1011"=>y_art<= b;
when "1100"=>y_art<= b+1;
when "1101"=>y_art<= b-1;
when "1110"=>y_art<= a + b;
when others=>y_art<= a + b + cin;
end case;
end process;
y<=y_lg when sel(3)='0' else y_art ; end Behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY testALU IS END testALU;
ARCHITECTURE behavior OF testALU
IS COMPONENT ALU_dongian PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
cin : IN std_logic;
sel : IN std_logic_vector(3 downto 0);
y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal a : std_logic_vector(7 downto 0) := (others => '0');
signal b : std_logic_vector(7 downto 0) := (others => '0');
signal cin : std_logic := '0';
signal sel : std_logic_vector(3 downto 0) := (others => '0');
signal y : std_logic_vector(7 downto 0);
BEGIN uut: ALU_dongian PORT MAP (
a => a,
b => b, cin => cin, sel => sel,
y => y );
cin<='0';
a <="00000011";
b <="00001000";
sel <="1110";
END;
7.Bộ cộng 8bit có dấu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity congcodau is port (A: in std_logic_vector (7 downto 0);
B: in std_logic_vector (7 downto 0);
Ci: in std_logic;
Co: out std_logic;
E: in std_logic);
End congcodau;
Architecture behavioral of congcodau is Signal A1, B1, C1, S1: std_logic_vector (7 downto 0) := x”00”;
Signal sel: std_logic_vector (1 downto 0);
Signal dau: std_logic :=‟0‟;
Begin Sel<=A(7)&B(7);
C1(0)<=Ci;
A1(6 downto 0) <= A(6 downto 0);
B1(6 downto 0) <= B(6 downto 0);
Process (A1, B1, sel) Begin
Case sel is When “11”=>s1<=A1+B1-C1;
dau<=‟1‟;
When “00”=>s1<=A1+B1+C1;
dau<=‟0‟;
When “10”=>if(A1>B1) then S1<=A1-B1-C1; dau<=‟1‟;
Else S1<=B1-A1+C1;
dau<=‟0‟;
End if;
When others=>if(A1>=B1) then S1<=A1-B1+C1; dau<=‟0‟;
Else S1<=B1-A1-C1; dau<=‟1‟;
End if;
End case;
End process;
Process (E, dau, s1, A, B) Begin
If (E=‟1‟) then s(6 downto 0) <= s1(6 downto 0); s(7)<=dau; Co<=S1(7); End if;
Else s<=(others=>‟Z‟); Co<=‟Z‟; End if;
End process;
End behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;
Entity tb is End tb;
Architecture behavioral of tb is Component congcodau Port(
A: in std_logic_vector (7 downto 0);
B: in std_logic_vector (7 downto 0);
S: out std_logic_vector (7 downto 0);
Ci: in std_logic;
Co: out std_logic;
E: in std_logic;
);
End component;
Signal A: std_logic_vector (7 downto 0) := (others=>‟0‟);
Signal B: std_logic_vector (7 downto 0) := (others=>‟0‟);
Signal Ci: std_logic := „0‟;
Signal E: std_logic := „0‟;
Signal S: std_logic_vector (7 downto 0); Signal Co: std_logic;
Begin Uut: congcodau PORT MAP(
A=>A, B=>B, S=>S, Ci=>Ci, Co=>Co, E=>E );
E<=‟1‟;
Ci<=‟0‟;
A<=”10000101”, “00000011” after 100ns;
B<=”10000011”;
End;
Trang 38.Bộ cộng 8bit ko dấu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity congkodau is
port (A: in std_logic_vector (7 downto
0);
B: in std_logic_vector (7
downto 0);
S: out std_logic_vector (7
downto 0);
Ci: in std_logic;
Co: out std_logic;
E: in std_logic);
End congkodau;
Architecture behavioral of congkodau is
Signal A1, B1, C1, S1: std_logic_vector
(8 downto 0) := ”000000000”;
Begin
C1(0)<=Ci;
A1(7 downto 0) <= A;
B1(7 downto 0) <= B;
S1<=A1+B1+C1;
Process (E)
Begin
If (E=‟1‟) then
S<=S1(7 downto 0);
Co<=S1(8);
Else S<=(others=>‟Z‟; Co<=‟Z‟;
End if;
End process;
End behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
Entity tb_kodau is
End tb_kodau;
Architecture behavioral of tb_kodau is
Component congkodau
Port(
A: in std_logic_vector (7
downto 0);
B: in std_logic_vector (7
downto 0);
S: out std_logic_vector (7
downto 0);
Ci: in std_logic;
Co: out std_logic;
E: in std_logic;
);
End component;
Signal A: std_logic_vector (7 downto 0)
:= (others=>‟0‟);
Signal B: std_logic_vector (7 downto 0)
:= (others=>‟0‟);
Signal Ci: std_logic := „0‟;
Signal E: std_logic := „0‟;
Signal S: std_logic_vector (7 downto 0);
Signal Co: std_logic;
Begin Uut: cong8bit PORT MAP(
A=>A, B=>B, S=>S, Ci=>Ci, Co=>Co, E=>E );
E<=‟1‟, „0‟ after 100ns;
Ci<=‟0‟, „1‟ after 50ns;
A<=x”15”, x“37” after 10ns, x”10” after 50ns, x”25” after 70ns;
B<=x”17”, x”30” after 10ns, x”28” after 50ns, x”13” after 70ns;
End;
9.So sánh 2 số 8bit ko dấu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity ss8bit is Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
FL : out STD_LOGIC;
FB : out STD_LOGIC;
FN : out STD_LOGIC;
FK : out STD_LOGIC;
FLB : out STD_LOGIC;
FNB : out STD_LOGIC);
end ss8bit;
architecture Behavioral of ss8bit is signal F:std_logic_vector(5 downto 0);
begin (FL,FB,FN,FK,FLB,FNB)<=F;
process(sel,a,b) begin case sel is
when "000" => if (a > b) then
F <="100000";
else
F <="000000";
end if;
when "001" => if (a = b) then
F <="010000";
else
F <="000000";
end if;
when "010" => if (a < b) then
F <="001000";
else
F <="000000";
end if;
when "011" => if (a /= b) then F <="000100";
else
F <="000000";
end if;
when "100" => if (a >= b) then F <="000010";
else
F <="000000";
end if;
when "101" => if (a <= b) then F <="000001";
else
F <="000000";
end if;
when others => f<="000000";
end case;
end process;
end Behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY testss_8bit IS END testss_8bit;
ARCHITECTURE behavior OF testss_8bit IS
COMPONENT ss8bit PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
sel : IN std_logic_vector(2 downto 0);
FL : OUT std_logic;
FB : OUT std_logic;
FN : OUT std_logic;
FK : OUT std_logic;
FLB : OUT std_logic;
FNB : OUT std_logic );
END COMPONENT;
signal a : std_logic_vector(7 downto 0) := (others => '0');
signal b : std_logic_vector(7 downto 0) := (others => '0');
signal sel : std_logic_vector(2 downto 0) := (others => '0');
signal FL : std_logic;
signal FB : std_logic;
signal FN : std_logic;
signal FK : std_logic;
signal FLB : std_logic;
signal FNB : std_logic;
BEGIN uut: ss8bit PORT MAP (
a => a,
b => b, sel => sel,
FL => FL,
FB => FB,
FN => FN,
FK => FK, FLB => FLB, FNB => FNB );
a<="11111100";
b<="11110000";
sel<="001";
END;
10.Bộ đếm nhị phân 8bit đếm tiến+lùi
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL; Entity dem_tien_lui is
Port (clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic; X: in std_logic_vector (7 downto 0);
Y: out std_logic_vector (7 downto 0);
F: out std_logic );
End dem_tien_lui;
Architecture behavioral of dem_tien_lui
is Signal count: std_logic_vector (7 downto 0) := x”00”;
Signal F1: std_logic:=‟0‟;
Begin Process (clk, reset, load, set, up_down, count)
Begin If(clk‟event and clk=‟1‟) then
If reset=‟1‟ then count<=x”00”; Else
If set=‟1‟ then count<=x”ff”; Else
If load=‟1‟ then count<=X; Else
If (up_down=‟1‟) then
If (count=x”ff”) then
Count<=x”00”;
F1<=‟1‟;
Else count<=count+1;
F1<=‟0‟;
End if;
Elsif (up_down=‟0‟) then
If count=x”00” then count<=x”ff”; F1<=‟1‟;
Else count<=count-1; F1<=‟0‟; End if;
End if;
End if;
End if;
End if;
End if;
End process;
Process (CE, count) Begin
If (CE=‟1‟) then y<=count; F<=F1; Else y<=(others=>‟Z‟); F<=‟Z‟; End if;
End process;
Trang 4End behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
Entity test_tien_lui is
End test_tien_lui;
Architecture behavior of test_tien_lui is
Component dem_tien_lui
Port(clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic;
X: in std_logic_vector (7
downto 0);
Y: out std_logic_vector (7
downto 0);
F: out std_logic
);
End component;
Signal clk: std_logic := „0‟;
Signal reset: std_logic := „0‟;
Signal load: std_logic := „0‟;
Signal set: std_logic := „0‟;
Signal CE: std_logic := „0‟;
Signal up_down: std_logic := „0‟;
Signal X: std_logic_vector (7 downto 0)
:= (others=>‟0‟);
Signal Y: std_logic_vector (7 downto 0);
Signal F: std_logic;
Begin
Uut: dem_tien_lui PORT MAP(
Clk=>clk,
Reset=>reset,
Load=>load,
Set=>set,
CE=>CE,
Up_down=>up_down,
X=>X,
Y=>Y,
F=>F,
);
Clk<=not clk after 1ns;
CE<=‟1‟, „0‟ after 2000ns;
Reset<=‟0‟, „1‟ after 520ns, „0‟ after
530ns;
Set<=‟0‟, „1‟ after 530ns, „0‟ after 540ns;
Load<=‟0‟, „1‟ after 540ns, „0‟ after
550ns;
X<=x”f0”;
Up_down<=‟1‟, „0‟ after 1500ns;
End;
11.Đếm tiến nhị phân 8bit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity dem_tien is Port (clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic;
X: in std_logic_vector (7 downto 0);
Y: out std_logic_vector (7 downto 0);
F: out std_logic );
End dem_tien;
Architecture behavioral of dem_tien is Signal count: std_logic_vector (7 downto 0) := x”00”;
Signal F1: std_logic:=‟0‟;
Begin Process (clk, reset, load, set, count) Begin
If(clk‟event and clk=‟1‟) then
If reset=‟1‟ then count<=x”00”;
Else
If set=‟1‟ then count<=x”ff”;
Else
If load=‟1‟ then count<=X;
Else
If (count=x”ff”) then
count=x”00”; F1<=‟1‟;
Else count<=count+1; F1<=‟0‟;
End if;
End if;
End if;
End if;
End if;
End process;
Process (CE, count) Begin
If (CE=‟1‟) then y<=count; F<=F1;
Else y<=(others=>‟Z‟); F<=‟Z‟;
End if;
End process;
End behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
Entity test_tien is End test_tien;
Architecture behavior of test_tien is Component dem_tien
Port(clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic;
X: in std_logic_vector (7 downto 0);
Y: out std_logic_vector (7 downto 0);
F: out std_logic );
End component;
Signal clk: std_logic := „0‟;
Signal reset: std_logic := „0‟;
Signal load: std_logic := „0‟;
Signal set: std_logic := „0‟;
Signal CE: std_logic := „0‟;
Signal up_down: std_logic := „0‟;
Signal X: std_logic_vector (7 downto 0) := (others=>‟0‟);
Signal Y: std_logic_vector (7 downto 0);
Signal F: std_logic;
Begin Uut: dem_tien PORT MAP(
Clk=>clk,
Reset=>reset, Load=>load, Set=>set, CE=>CE, X=>X, Y=>Y, F=>F, );
Clk<=not clk after 1ns;
CE<=‟1‟, „0‟ after 2000ns;
Reset<=‟0‟, „1‟ after 520ns, „0‟ after 530ns;
Set<=‟0‟, „1‟ after 530ns, „0‟ after 540ns;
Load<=‟0‟, „1‟ after 540ns, „0‟ after 550ns;
X<=x”f0”;
End;
12.Đếm lùi nhị phân 8bit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity dem_lui is Port (clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
X: in std_logic_vector (7 downto 0);
Y: out std_logic_vector (7 downto 0);
F: out std_logic );
End dem_lui;
Architecture behavioral of dem_lui is Signal count: std_logic_vector (7 downto 0) := x”00”;
Signal F1: std_logic:=‟0‟;
Begin Process (clk, reset, load, set, count) Begin
If(clk‟event and clk=‟1‟) then
If reset=‟1‟ then count<=x”00”;
Else
If set=‟1‟ then count<=x”ff”; Else
If load=‟1‟ then count<=X; Else
If (count=x”00”) then count=x”ff”; F1<=‟1‟; Else count<=count-1; F1<=‟0‟;
End if;
End if;
End if;
End if;
End if;
End process;
Process (CE, count) Begin
If (CE=‟1‟) then y<=count; F<=F1; Else y<=(others=>‟Z‟); F<=‟Z‟; End if;
End process;
End behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;
Entity test_lui is End test_lui;
Architecture behavior of test_lui is Component dem_lui
Port(clk: in std_logic;
Reset: in std_logic; Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
X: in std_logic_vector (7 downto 0);
Y: out std_logic_vector (7 downto 0);
F: out std_logic );
End component;
Signal clk: std_logic := „0‟;
Signal reset: std_logic := „0‟;
Signal load: std_logic := „0‟;
Signal set: std_logic := „0‟;
Signal CE: std_logic := „0‟;
Signal up_down: std_logic := „0‟; Signal X: std_logic_vector (7 downto 0) := (others=>‟0‟);
Signal Y: std_logic_vector (7 downto 0); Signal F: std_logic;
Begin Uut: dem_tien PORT MAP(
Clk=>clk,
Reset=>reset, Load=>load, Set=>set, CE=>CE, X=>X, Y=>Y,
Trang 5F=>F,
);
Clk<=not clk after 1ns;
CE<=‟1‟, „0‟ after 2000ns;
Reset<=‟0‟, „1‟ after 520ns, „0‟ after
530ns;
Set<=‟0‟, „1‟ after 530ns, „0‟ after 540ns;
Load<=‟0‟, „1‟ after 540ns, „0‟ after
550ns;
X<=x”f0”;
End;
13.Bộ đếm thập phân (2 digits) chế độ
đếm tiến+lùi mode 100 có Reset, Load
đồng bộ
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity digit100 is
Port (clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic;
Hc_in: in std_logic_vector (3
downto 0);
Hdv_in: in std_logic_vector (3
downto 0);
Hc_out: out std_logic_vector
(3 downto 0);
Hdv_out: out std_logic_vector
(3 downto 0);
);
End digit100;
Architecture behavioral of digit100 is
Signal hc1, hdv1: std_logic_vector (3
downto 0) := x”0”;
Begin
Process (clk, reset, set, load, up_down,
hc1, hdv1)
Begin
If (clk‟event and clk=‟1‟) then
If reset=‟1‟ then hc1<=x”0”;
hdv1<=x”0”;
elsif set=‟1‟ then hc1<=x”9”;
hdv1<=x”9”;
elsif load=‟1‟ then hc1<=hc_in;
hdv1<=hdv_in;
elsif up_down=‟1‟ then
if hdv1=9 then hdv1<=x”0”;
if hc1=9 then hc1<=x”0”;
else hc1<=hc1+1;
end if;
else hdv1<=hdv1+1;
end if;
elsif up_down=‟0‟ then
if hdv1=0 then hdv1<=x”9”;
if hc1=0 then hc1<=x”9”;
else hc1<=hc1-1;
end if;
else hdv1<=hdv1-1;
end if;
end if;
end if;
End process;
Process (hdv1, hc1, ce) Begin
If (ce=‟1‟) then hc<=hc1; hdv<=hdv1;
Else hc<=(others=>‟Z‟);
hdv<=(others=>‟Z‟);
End if;
End process;
End behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
Entity test_digit100 is End test_digit100;
Architecture behavior of test_digit100 is Component digit100
Port(clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic;
Hc_in: in std_logic_vector (3 downto 0);
Hdv_in: in std_logic_vector (3 downto 0);
Hc: out std_logic_vector (3 downto 0);
Hdv: out std_logic_vector (3 downto 0);
);
End component;
Signal clk: std_logic := „0‟;
Signal reset: std_logic := „0‟;
Signal load: std_logic := „0‟;
Signal set: std_logic := „0‟;
Signal CE: std_logic := „0‟;
Signal up_down: std_logic := „0‟;
Signal hc_in: std_logic_vector (3 downto 0) := (others =>‟0‟);
Signal hdv_in: std_logic_vector (3 downto 0) := (others =>‟0‟);
Signal hc: std_logic_vector (3 downto 0);
Signal hdv: std_logic_vector (3 downto 0);
Constant clk_period: time := 1us;
Begin Uut: digit100 PORT MAP(
Clk=>clk,
Ce=>ce, Reset=>reset, Set=>set, Load=>load, Up_down=>up_down, Hc_in=>hc_in, Hdv_in=>hdv_in, Hc=>hc, Hdv=>hdv
);
Clk<=not clk after 1ns;
Ce<=‟1‟, ‟0‟ after 500ns;
Reset<=‟0‟, „1‟ after 150ns, „0‟ after 170ns;
Set<=‟0‟, „1‟ after 170ns, „0‟ after 175ns;
Load<=‟0‟, „1‟ after 175ns, „0‟ after 180ns;
Up_down<=‟1‟, „0‟ after 300ns;
Hc_in<=x”2”;
Hdv_in<=x”4”;
End;
14.Bộ đếm thập phân (2 digits) chế độ đếm tiến+lùi mode 100 có Reset, Load
ko đồng bộ
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity digit100_kodongbo is Port (clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic;
Hc_in: in std_logic_vector (3 downto 0);
Hdv_in: in std_logic_vector (3 downto 0);
Hc: out std_logic_vector (3 downto 0);
Hdv: out std_logic_vector (3 downto 0);
);
End digit100_kodongbo;
Architecture behavioral of digit100_kodongbo is Signal hc1, hdv1: std_logic_vector (3 downto 0) := x”0”;
Begin Process (clk, reset, set, load, up_down, hc1, hdv1)
Begin
If reset=‟1‟ then hc1<=x”0”;
hdv1<=x”0”;
elsif set=‟1‟ then hc1<=x”9”;
hdv1<=x”9”;
elsif load=‟1‟ then hc1<=hc_in;
hdv1<=hdv_in;
elsif clk‟event and clk=‟1‟ then
if up_down=‟1‟ then
if hdv1=9 then hdv1<=x”0”;
if hc1=9 then hc1<=x”0”;
else hc1<=hc1+1;
end if;
else hdv1<=hdv1+1;
end if;
else
if hdv1=0 then hdv1<=x”9”;
if hc1=0 then hc1<=x”9”;
else hc1<=hc1-1;
end if;
else hdv1<=hdv1-1;
end if;
end if;
end if;
End process;
Process (hdv1, hc1, ce) Begin
If (ce=‟1‟) then hc<=hc1; hdv<=hdv1; Else hc<=(others=>‟Z‟);
hdv<=(others=>‟Z‟);
End if;
End process;
End behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;
Entity test_kodongbo is End test_kodongbo;
Architecture behavior of test_kodongbo
is Component digit100_kodongbo Port(clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic; Hc_in: in std_logic_vector (3 downto 0);
Hdv_in: in std_logic_vector (3 downto 0);
Hc: out std_logic_vector (3 downto 0);
Hdv: out std_logic_vector (3 downto 0);
);
End component;
Signal clk: std_logic := „0‟;
Signal reset: std_logic := „0‟;
Signal load: std_logic := „0‟;
Signal set: std_logic := „0‟;
Signal CE: std_logic := „0‟;
Signal up_down: std_logic := „0‟; Signal hc_in: std_logic_vector (3 downto 0) := (others =>‟0‟);
Signal hdv_in: std_logic_vector (3 downto 0) := (others =>‟0‟);
Signal hc: std_logic_vector (3 downto 0); Signal hdv: std_logic_vector (3 downto 0);
Constant clk_period: time := 1us; Begin
Uut: digit100_kodongbo PORT MAP(
Clk=>clk, Ce=>ce, Reset=>reset, Set=>set, Load=>load,
Trang 6Up_down=>up_down,
Hc_in=>hc_in,
Hdv_in=>hdv_in,
Hc=>hc,
Hdv=>hdv
);
Clk<=not clk after 1ns;
Ce<=‟1‟, ‟0‟ after 500ns;
Reset<=‟0‟, „1‟ after 150ns, „0‟ after
170ns;
Set<=‟0‟, „1‟ after 170ns, „0‟ after 175ns;
Load<=‟0‟, „1‟ after 175ns, „0‟ after
180ns;
Up_down<=‟1‟, „0‟ after 300ns;
Hc_in<=x”2”;
Hdv_in<=x”4”;
End;
15.Đếm tiến ko đồng bộ (thập phân)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity digit100_kodongbo is
Port (clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic;
Hc_in: in std_logic_vector (3
downto 0);
Hdv_in: in std_logic_vector (3
downto 0);
Hc: out std_logic_vector (3
downto 0);
Hdv: out std_logic_vector (3
downto 0);
);
End digit100_kodongbo;
Architecture behavioral of
digit100_kodongbo is
Signal hc1, hdv1: std_logic_vector (3
downto 0) := x”0”;
Begin
Process (clk, reset, set, load, up_down,
hc1, hdv1)
Begin
If reset=‟1‟ then hc1<=x”0”;
hdv1<=x”0”;
elsif set=‟1‟ then hc1<=x”9”;
hdv1<=x”9”;
elsif load=‟1‟ then hc1<=hc_in;
hdv1<=hdv_in;
elsif clk‟event and clk=‟1‟ then
if hdv1=9 then hdv1<=x”0”;
if hc1=9 then hc1<=x”0”;
else hc1<=hc1+1;
end if;
else hdv1<=hdv1+1;
end if;
end if;
End process;
Process (hdv1, hc1, ce) Begin
If (ce=‟1‟) then hc<=hc1; hdv<=hdv1;
Else hc<=(others=>‟Z‟);
hdv<=(others=>‟Z‟);
End if;
End process;
End behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
Entity test_kodongbo is End test_kodongbo;
Architecture behavior of test_kodongbo
is Component digit100_kodongbo Port(clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic;
Hc_in: in std_logic_vector (3 downto 0);
Hdv_in: in std_logic_vector (3 downto 0);
Hc: out std_logic_vector (3 downto 0);
Hdv: out std_logic_vector (3 downto 0);
);
End component;
Signal clk: std_logic := „0‟;
Signal reset: std_logic := „0‟;
Signal load: std_logic := „0‟;
Signal set: std_logic := „0‟;
Signal CE: std_logic := „0‟;
Signal up_down: std_logic := „0‟;
Signal hc_in: std_logic_vector (3 downto 0) := (others =>‟0‟);
Signal hdv_in: std_logic_vector (3 downto 0) := (others =>‟0‟);
Signal hc: std_logic_vector (3 downto 0);
Signal hdv: std_logic_vector (3 downto 0);
Constant clk_period: time := 1us;
Begin Uut: digit100_kodongbo PORT MAP(
Clk=>clk, Ce=>ce, Reset=>reset, Set=>set, Load=>load, Up_down=>up_down, Hc_in=>hc_in, Hdv_in=>hdv_in, Hc=>hc, Hdv=>hdv );
Clk<=not clk after 1ns;
Ce<=‟1‟, ‟0‟ after 500ns;
Reset<=‟0‟, „1‟ after 150ns, „0‟ after 170ns;
Set<=‟0‟, „1‟ after 170ns, „0‟ after 175ns;
Load<=‟0‟, „1‟ after 175ns, „0‟ after 180ns;
Hc_in<=x”2”;
Hdv_in<=x”4”;
End;
16.Đếm lùi ko đồng bộ (thập phân)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity digit100_kodongbo is Port (clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic;
Hc_in: in std_logic_vector (3 downto 0);
Hdv_in: in std_logic_vector (3 downto 0);
Hc: out std_logic_vector (3 downto 0);
Hdv: out std_logic_vector (3 downto 0);
);
End digit100_kodongbo;
Architecture behavioral of digit100_kodongbo is Signal hc1, hdv1: std_logic_vector (3 downto 0) := x”0”;
Begin Process (clk, reset, set, load, up_down, hc1, hdv1)
Begin
If reset=‟1‟ then hc1<=x”0”;
hdv1<=x”0”;
elsif set=‟1‟ then hc1<=x”9”;
hdv1<=x”9”;
elsif load=‟1‟ then hc1<=hc_in;
hdv1<=hdv_in;
elsif clk‟event and clk=‟1‟ then
if hdv1=0 then hdv1<=x”9”;
if hc1=0 then hc1<=x”9”;
else hc1<=hc1-1;
end if;
else hdv1<=hdv1-1;
end if;
end if;
End process;
Process (hdv1, hc1, ce) Begin
If (ce=‟1‟) then hc<=hc1; hdv<=hdv1;
Else hc<=(others=>‟Z‟);
hdv<=(others=>‟Z‟);
End if;
End process;
End behavioral;
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;
Entity test_kodongbo is End test_kodongbo;
Architecture behavior of test_kodongbo
is Component digit100_kodongbo Port(clk: in std_logic;
Reset: in std_logic;
Load: in std_logic;
Set: in std_logic;
CE: in std_logic;
Up_down: in std_logic; Hc_in: in std_logic_vector (3 downto 0);
Hdv_in: in std_logic_vector (3 downto 0);
Hc: out std_logic_vector (3 downto 0);
Hdv: out std_logic_vector (3 downto 0);
);
End component;
Signal clk: std_logic := „0‟;
Signal reset: std_logic := „0‟;
Signal load: std_logic := „0‟;
Signal set: std_logic := „0‟;
Signal CE: std_logic := „0‟;
Signal up_down: std_logic := „0‟; Signal hc_in: std_logic_vector (3 downto 0) := (others =>‟0‟);
Signal hdv_in: std_logic_vector (3 downto 0) := (others =>‟0‟);
Signal hc: std_logic_vector (3 downto 0); Signal hdv: std_logic_vector (3 downto 0);
Constant clk_period: time := 1us; Begin
Uut: digit100_kodongbo PORT MAP(
Clk=>clk, Ce=>ce, Reset=>reset, Set=>set, Load=>load, Up_down=>up_down, Hc_in=>hc_in, Hdv_in=>hdv_in, Hc=>hc, Hdv=>hdv );
Clk<=not clk after 1ns;
Ce<=‟1‟, ‟0‟ after 500ns;
Reset<=‟0‟, „1‟ after 150ns, „0‟ after 170ns;
Set<=‟0‟, „1‟ after 170ns, „0‟ after 175ns; Load<=‟0‟, „1‟ after 175ns, „0‟ after 180ns;
Hc_in<=x”2”;
Trang 7Hdv_in<=x”4”;
End;
17.Đèn giao thông ngã tư sở
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dgt is
port( clk,rst,set: in std_logic;
L1,L2: out std_logic_vector(2
downto 0));
end dgt;
Architecture behavioral of dgt is
type my_state is(RG,RY,GR,YR);
signal seg,next_seg:my_state;
constant Trg: integer:=30;
constant Try: integer:=5;
constant Tgr: integer:=30;
constant Tyr: integer:=5;
signal cter,T: integer:='0';
signal clk_1s:std_logic:= '0';
begin
process(clk)
begin
if clk'event and clk='1' then
if rst='1' then cter<='0';
else
if (cter='9') then clk_1s='1'; cter<='0' ;
else cter<= cter+1; clk_1s='0';
end if;
end if;
end if;
end process;
syns: process(clk_1s)
begin
if (clk_1s'event and clk_1s='1') then
if (rst='1') then seg<= RG; T<=0;
else seg<=next_seg;
if T=69 then T<=0;
else T<= T+1;
end if;
end if;
end if;
end process;
comb:process(seg,clk_1s,T)
begin
case seg is
when RG=> if T=Trg-1 then
next_seg<= RY;
end if;
when RY => if T= Try+ Trg -1
then next_seg<= GR;
end if;
when GR => if T=Tgr+Try+Trg-1
then next_seg<=YR;
end if;
when YR => if
T=Tyr+Tgr+Try+Trg-1 then
next_seg<=RG;
end if;
end case;
end process;
outs:process(seg,set)
begin
if set='1' then
case seg is when RG=> L1<= '100'; L2<= '001';
when RY=> L1<= '100'; L2<= '010';
when GR=> L1<= '001'; L2<= '100';
when YR =>L1<= '010'; L2<= '100';
end case;
else case seg is when RG=> L1<= '010'; L2<= '010';
when RY=> L1<= '010'; L2<= '010';
when GR=> L1<= '010'; L2<= '010';
when others => L1<= '010'; L2<=
;010';
end case end if;
end process;
end behavioral;
TestBench
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity dgt_tb is end dgt_tb;
architecture behavioral of dgt_tb is component dgt
port ( clk,rst,set:in std_logic;
L1,L2:out std_logic_vector(2 downto 0));
end component;
signal clk: std_logic: ='0';
signal rst: std_logic:='0';
signal set: std_logic:='0';
signal L1 :std_logic_vector(2downto 0);
signal L2 :std_logic_vector(2 downto 0);
constant clk_period:time='1us';
begin uut:dgt port map(
clk=>clk, rst=>rst, set=>set, L1=> L1, L2=>L2);
clk<= not clk after 2ns;
set<='1';
end;
18.Máy bán nước ngọt
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
Use IEEE.std_logic_unsigned.all;
Entity sell_coca is;
Port ( clk : in std_logic;
Cancel : in std_logic;
Coca :out std_logic;
Repay: out std_logic_vector(1 down to 0);
Pay:out std_logic_vector( 1 down to 0)
);
End sell_coca;
Architecture behavioral of sell_coca is
Type status is (s0,s1,s2,s3,s4,s5,s6);
Signal seg, next_seg:
status:=s0;
Signal flag: std_logic:=‟0‟;
Begin cap nhat trang thai
Syn:
Process(cancel,clk) Begin
If(cancel=‟1‟)then seg<=s0;
Elsif(clk‟event and clk=‟1‟) then
Seg<=next_seg;
End if;
End process;
Dieu kien chuyen trang thai Comb: Process(seg,pay,flag) Begin
Case seg is When s0=>
If (pay=1)then next_seg<=s1;
Elsif(pay=2)then next_seg<=s2;
Elsif(pay=3)then next_seg<=s3;
End if;
When s1=>
If (pay=1) then next_seg<=s2;
Elsif(pay=2) then next_seg<=s3;
Elsif(pay=3) then next_seg<=s4;
End if;
When s2=>
If(pay=1) then next_seg<=s3;
Elsif(pay=2) then next_seg<=s4;
Elsif(pay=3)then next_seg<=s5;
End if;
When s3=>
If(pay=1) then next_seg<=s4;
Elsif(pay=2)then next_seg<=s5;
Elsif(pay=3)then next_seg<=s6;
End if;
When s4=> if flag=‟1‟then next_seg<=s0;end if;
When s5=>if flag=‟1‟ then next_seg<=0
;end if;
When s6=>if flag=‟1‟ then next_seg<=s0;end if;
End case;
End process;
dau ra Output:
Process(seg) Begin If(seg=s4) then coca<=‟1‟;repay<=”00”;flag<=‟1‟;
Elsif(seg=s5)then coca<=‟1‟;repay<=”01”;flag<=‟1‟;
Elsif(seg=s6) then coca<=‟1‟;repay<=”10”;flag<=‟1‟;
Else coca<=‟0‟; repay<=”00”;flag<=‟0‟
End if;
End process;
End behavioral;
TestBench
Library IEEE;
Use IEEE.std_logic_1164.all; Use IEEE.numeric.all;
Use IEEE.std_logic_unsigned.all; Entity tb_coca is
End tb_coca;
Architecture behavioral of tb_coca is component sell_coca
Port ( clk : in std_logic;
Cancel : in std_logic;
Coca :out std_logic;
Repay: out std_logic_vector(1 down to 0);
Pay:out std_logic_vector( 1 down to 0) );
End component;
inputs Signal clk:std_logic:=‟0‟;
Signal cancel:std_logic:=‟0‟;
Signal pay:std_logic_vector(1 down to 0):=(others=>‟0‟);
outputs Signal coca:std_logic_;
Signal pay:std_logic_vector(1 down to 0);
check period definitions Constant clk_period:time:=1us; Begin
instantiate the unit under test(uut) Uut: sell_coca port map(
Clk=>clk, Cancel=>cancel, Coca=>coca, Repay=>repay, Pay=>pay, );
Cancel<=‟0‟;
Clk<=not clk after 1ns;
Pay<=”00”, “01” after 30ns, “00” after 31ns,”10” after 60ns,”00” after 61s,”10”after 90ns,”00” after 91ns,”11” after 350ns,”00” after 351ns,”11” after 370ns,”00” after 371ns;
End;