A computer system consists of hardware, system programs, and application programs figs 4

THE SECURITY ENVIRONMENT 9.2 BASICS OF CRYPTOGRAPHY 9.3 USER AUTHENTICATION 9.4 ATTACKS FROM INSIDE THE SYSTEM 9.5 ATTACKS FROM OUTSIDE THE SYSTEM 9.6 PROTECTION MECHANISMS 9.7 TRUSTED SYSTEMS 9.8 RESEARCH ON SECURITY 9.9 SUMMARY

4.4 PAGE REPLACEMENT ALGORITHMS

4.5 MODELING PAGE REPLACEMENT ALGORITHMS 4.6 DESIGN ISSUES FOR PAGING SYSTEMS

4.7 IMPLEMENTATION ISSUES

4.8 SEGMENTATION

4.9 RESEARCH ON MEMORY MANAGEMENT

4.10 SUMMARY

User program

Operating

system in

RAM

Operating system in RAM

Operating system in ROM

Device drivers in ROM

Fig 4-1 Three simple ways of organizing memory with an ing system and one user process Other possibilities also exist

Partition 4

Partition 3

Partition 2

Partition 1 Operating system

200K 800K

Fig 4-2 (a) Fixed memory partitions with separate input queuesfor each partition (b) Fixed memory partitions with a single inputqueue

50% I/O wait

80% I/O wait

20% I/O wait 100

Fig 4-3 CPU utilization as a function of the number of processes

in memory

Arrival

time

CPU minutes needed 1

CPU idle CPU busy CPU/process

.80 20 20

.64 36 18

.51 49 16

.41 59 15

.3 3 3 3

.9 9 9

.1

.1 7 Job 2 starts

;;

A B

(c)

Operating system

;

A B C

(d)

Time

Operating system

(e)

D Operating system

;;

;

;

B C

(f)

D Operating system

;

A C

Fig 4-5 Memory allocation changes as processes come into

memory and leave it The shaded regions are unused memory

(a) (b)

Operating system

Room for growth

Room for growth

B-Stack

A-Stack B-Data

A-Data B-Program

Fig 4-6 (a) Allocating space for a growing data segment

(b) Allocating space for a growing stack and a growing data ment

The MMU sends physical

addresses to the memory

Memory management unit

controller

Bus

Fig 4-9 The position and function of the MMU Here the MMU

is shown as being a part of the CPU chip because it commonly isnowadays However, logically it could be a separate chip and was

in years gone by

address

space

Physicalmemoryaddress

Page frame

XXXX7X5XXX340612

Fig 4-10 The relation between virtual addresses and physicalmemory addresses is given by the page table

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000 000 000 000 111 000 101 000 000 000 011 100 000 110 001 010

0 0 0 0 1 0 1 0 0 0 1 1 1 1 1

to output

Virtual page = 2 is used

as an index into the

virtual address (8196)

Outgoing physical address (24580)

(b)

Top-level page table

Second-level page tables

To pages

Page table for the top 4M of memory

6 5 4 3 2 1 0 1023

6 5 4 3 2 1 0

1023

Bits 10 10 12

PT1 PT2 Offset

Fig 4-12 (a) A 32-bit address with two page table fields

(b) Two-level page tables

Page frame number

Traditional page

table with an entry

for each of the 2 52

pages

256-MB physical memory has 2 16

0 Indexed

by hash on virtual page

Virtual page

Page frame

Fig 4-15 Comparison of a traditional page table with an invertedpage table

Page loaded first

Most recently loaded page 0

A

3 B

7 C

8 D

12 E

14 F

15 G

18 H

(b)

A is treated like a newly loaded page 3

B

7 C

8 D

12 E

14 F

15 G

18 H

20 A

Fig 4-16 Operation of second chance (a) Pages sorted in FIFO

order (b) Page list if a page fault occurs at time 20 and A has its R

bit set The numbers above the pages are their loading times

When a page fault occurs, the page the hand is pointing to is inspected.

The action taken depends

on the R bit:

R = 0: Evict the page

R = 1: Clear R and advance hand

1 0 0 0 0

2 1 1 0 0

3 1 1 0 0 Page

(c)

0 0 1 1 0

1 0 0 1 0

2 0 0 0 0

3 1 1 1 0 Page

(d)

0 0 1 1 1

1 0 0 1 1

2 0 0 0 1

3 0 0 0 0 Page

(e)

0 0 1 1 1

1 0 0 1 1

2 0 0 0 0

3 0 0 1 0

(g)

0 0 0 0

1 0 0 0

1 1 0 0

1 1 1 0

(h)

0 0 0 1

1 0 0 1

1 1 0 1

0 0 0 0

(i)

0 0 1 1

1 0 1 1

0 0 0 0

0 0 1 0

(j)

0 0 1 1

1 0 1 1

0 0 0 1

0 0 0 0 Page

Fig 4-18 LRU using a matrix when pages are referenced in theorder 0, 1, 2, 3, 2, 1, 0, 3, 2, 3

Fig 4-19 The aging algorithm simulates LRU in software.

Shown are six pages for five clock ticks The five clock ticks arerepresented by (a) to (e)

k

Fig 4-20 The working set is the set of pages used by the k most recent memory references The function w(k, t) is the size of the working set at time t.

Information about

2204 Current virtual time

2003 1980 1213 2014 2020 2032 1620 Page table

1 1 1 0 1 1 1 0

Time of last use

Page referenced

during this tick

Page not referenced

during this tick

R (Referenced) bit

Scan all pages examining R bit:

if (R == 1) set time of last use to current virtual time

if (R == 0 and age > τ ) remove this page

if (R == 0 and age ≤ τ ) remember the smallest time

Fig 4-21 The working set algorithm

2204 Current virtual time

Fig 4-22 Operation of the WSClock algorithm (a) and (b) give

an example of what happens when R = 1 (c) and (d) give an example of R = 0.

Fig 4-24 Belady’s anomaly (a) FIFO with three page frames.

(b) FIFO with four page frames The P’s show which page

refer-ences cause page faults

Reference string

0 0 0 0 0 0

P Page faults

Fig 4-25 The state of the memory array, M, after each item in the

reference string is processed The distance string will be discussed

in the next section

# times

6 occurs in distance string

Fig 4-27 Computation of the page fault rate from the distance

string (a) The C vector (b) F vector.

A0 A1 A2 A3 A4 A5 B0 B1 B2 A6 B4 B5 B6 C1 C2 C3

Age 10 7 5 4 6 3 9 4 6 2 5 6 12 3 5 6

Fig 4-28 Local versus global page replacement (a) Original figuration (b) Local page replacement (c) Global page replace-ment

MOVE 6 2

1000

1002

1004

Opcode First operand Second operand

16 Bits MOVE.L #6(A1), 2(A0)

} } }

Fig 4-32 An instruction causing a page fault

2 1

3 6

6 4 3

0

5 1

7 2

Pages

Page table

Swap area

(b)

Disk map

Fig 4-33 (a) Paging to a static swap area (b) Backing up pagesdynamically

Disk Main memory

External pager

Fault handler

User process

MMU handler

1 Page

fault

6 Map page in

4 Page arrives

3 Request page

Fig 4-34 Page fault handling with an external pager

Space currently being used by the parse tree Free

Virtual address space

Symbol table

Symbol table has bumped into the source text table

Address space

allocated to the

Source text Constant table Call stack

Fig 4-35 In a one-dimensional address space with growing tables,one table may bump into another

table

Source text

Constants

Parse tree

Call stack

Segment

0

Segment 1

Segment 2

Segment 3

Segment 4

Consideration Paging Segmentation Need the programmer be aware

that this technique is being used?

How many linear address

spaces are there?

Can the total address space

exceed the size of physical

memory?

Can procedures and data be

distinguished and separately

protected?

Can tables whose size fluctuates

be accommodated easily?

Is sharing of procedures

between users facilitated?

Why was this technique

To get a large linear address space without having to buy more physical memory

To allow programs and data to be broken

up into logically independent address spaces and to aid sharing and protection

Fig 4-37 Comparison of paging and segmentation

Segment 0 (4K)

Segment 7 (5K)

Segment 2 (5K)

Segment 5 (4K)

(3K)

Segment 3

(4K) (3K)

Segment 0 (4K)

Segment 7 (5K)

Segment 2 (5K)

Segment 3 (8K)

Segment 3

(8K)

Segment 0 (4K)

Segment 7 (5K)

Segment 2 (5K) (3K)

Segment 5 (4K) (3K)

(4K)

Segment 0 (4K)

Segment 7 (5K)

Segment 2 (5K)

Segment 6 (4K)

Segment 5 (4K) (10K)

Fig 4-38 (a)-(d) Development of checkerboarding (e) Removal

of the checkerboarding by compaction

(a)

(b)

Main memory address

of the page table

Segment length (in pages)

Segment 6 descriptor Segment 5 descriptor Segment 4 descriptor Segment 3 descriptor Segment 2 descriptor Segment 1 descriptor Segment 0 descriptor Descriptor segment

36 bits

Page 2 entry Page 1 entry Page 0 entry Page table for segment 1

Page 2 entry Page 1 entry Page 0 entry Page table for segment 3

Fig 4-39 The MULTICS virtual memory (a) The descriptor ment points to the page tables (b) A segment descriptor Thenumbers are the field lengths

seg-Segment number Page

number

Offset within the page

Address within the segment

Fig 4-40 A 34-bit MULTICS virtual address

Segment number Page

Descriptor segment

Segment

number

Page number

MULTICS virtual address

Page table

Page

Word

Offset

Fig 4-41 Conversion of a two-part MULTICS address into a mainmemory address

number

Virtualpage

Pageframe

Comparison

field

Protection Age

Is thisentryused?

12

721

012

Read/writeRead onlyRead/write

Execute onlyExecute only

13102

79

111011

Fig 4-42 A simplified version of the MULTICS TLB The

existence of two page sizes makes the actual TLB

more complicated

0 = GDT/1 = LDT Privilege level (0-3)Bits 13 1 2

Fig 4-43 A Pentium selector

Privilege level (0-3)

Relative address 0

32 Bits

Fig 4-44 Pentium code segment descriptor Data segments differslightly

Descriptor Base address Limit Other fields

32-Bit linear address

+

Fig 4-45 Conversion of a (selector, offset) pair to a linearaddress

Page table entry points

to word

Page frame Word

Kernel 0 1 2 3 Level

Typical uses of the levels