Performance evaluation of neural network based channel detection for stt mram

Performance Evaluation of Neural Network Based Channel Detection for STT MRAM Performance Evaluation Of Neural Network Based Channel Detection For STT MRAM Chi Dinh Nguyen1, Phong Duy Nguyen2, Anh Tua[.]

Performance Evaluation Of Neural Network-Based

Channel Detection For STT-MRAM

Chi Dinh Nguyen1, Phong Duy Nguyen2, Anh Tuan Nguyen2, Nghia Xuan Pham3, and Khoa Dang Nguyen4

1Faculty of Computing Fundamentals, FPT University, Hanoi 13113, Vietnam

2TPBank IT Center, Ruby Plaza Tower, 44 Le Ngoc Han, Hanoi 100000, Vietnam

3Faculty of Radio - Electronics Engineering, Le Quy Don Technical University, Hanoi 100000, Vietnam

4Faculty of Electrical and Electronic Engineering, Phenikaa University, Hanoi 12116, Vietnam Email: chind3@fe.edu.vn*, {phongnd2, anhnt75}@tpb.com.vn, nghiapx@mta.edu.vn, khoa.nguyendang@phenikaa-uni.edu.vn

Abstract—In this study, we evaluate the performance of neural

network-based channel detection under the support of spares

coding for spin-torque transfer magnetic random access memory

(STT-MRAM) Due to its unique features, such as high density,

high endurance, and high-speed input/output, the STT-MRAM is

considered to have a significant opportunity in the consumer

electronics market for the Internet of Things (IoT) field and

artificial intelligence (AI) applications Yet, the reliability of

STT-MRAM is significantly degraded due to the influence of both write

and read errors A proposed scheme that the user signal is encoded

by sparse codes and detected by the RNN-based detector is

evaluated in this paper Improvements over the conventional

detection are shown through simulation results

Keywords—multilevel coding, modulation coding, holographic

storage, intersymbol interference

I INTRODUCTION The explosive growth of the IoT and AI-aided devices has

spurred the development of vast and reliable data storage In

recent years, flash memory, with its advantages of small size and

energy efficiency, has been considered the most successful

product which dominates the nonvolatile memory (NVM)

market However, one of the significant disadvantages of flash

memory is its limited lifespan It means flash memory has a

limited number of program/erase (P/E) cycles, and the reliability

of devices is significantly degraded as the P/E indicator exceeds

the limit Moreover, NOR flash memory cannot scale beyond 28

nm [1] Many emerging storage technologies that could soon

become the next-generation data storage technology are being

explored One of the most notable names is spin-torque transfer

magnetic random access memory (STT-MRAM) This memory

technology uses the spin of electrons for storage instead of their

charge

An STT-MRAM device consists of two main elements, a

magnetic tunnel junction (MTJ) and an nMOS transistor [2] The

nMOS transistor operates in the role of an access control part,

whereas the MTJ is a storage one The MTJ includes two

ferromagnetic layers and one ultrathin tunneling oxide layer

One of the ferromagnetic layers, named a reference layer, is

fixed in its orientation magnetization The other layer, called a

free layer, can change its orientation magnetization Based on

the relative magnetization state of the ferromagnetic layers, the

user data is stored in the MTJ cell In particular, if there are

antiparallel (AP) magnetization directions between the reference

layer and free layer, the MTJ, in a high resistance state, presents

a bit logic of "1." In the case of the parallel (P) magnetization directions, the MTJ, in a low resistance state, represents a bit logic of "0." Fig 1 illustrates a typical STT-MRAM cell structure of one-transistor-one-MTJ (1T1M) and its switching For write and read operations, a passing current through the MTJ is deployed in STT-MRAM In particular, if the bit line (BL) and word line (WL) are fed to the supply voltage while the source line (SL) is grounded, the current goes from the free layer

to the reference layer for writing 0 In the reversed case, if the

BL is grounded while the WL and SL are fed to the supply, the current is reversed for writing 1 For a read operation, the access transistor is first to turn on A relatively small read current in the same direction as the write current is passed through the MTJ The resulting voltage is compared with a reference voltage value

to determine the current logic level stored in the MTJ

a)

b) Fig 1 1T1M a) 1 to 0 transition b) 0 to 1 transition

Free layer Reference layer Oxide barrier

SL

BL

WL

SL

BL

WL

Write current

Free layer Reference layer Oxide barrier

SL

BL

WL

SL

BL

WL

Write current

STT-MRAM offers fascinating advantages such as

remarkable endurance, high reliability, and nanosecond

write/read speeds, useful in many AI and IoT applications

However, STT-MRAM still needs to solve its challenges to

ensure reliability during operation As the control and storage

components of the STT-MRAM are varied, plus the influence of

the inherent heat in the system, it leads to the formation of errors

in both the write and read processes Specifically, reading errors

occur when the memory cell resistance is incorrectly sensed

during the reading or caused by accidental flipping of MTJ A

prominent feature in STT-MRAM devices is the asymmetric

write error rate for write errors In particular, the error rate for 0

to 1 switching is much larger than for 1 to 0 switching It should

also be added that the channel detector does not know the causes

of deviations from the nominal values of memory readback

signals As a result, the performance in detecting the received

signal under the effect of offset is very severe The error

propagation can occur and adversely affects the quality of the

decoder

In order to solve the challenges of STT-MRAM, besides

optimizing the production process, it is necessary to apply

advanced coding and detecting techniques Constrained codes

and error correction codes (ECC) have long been developed in

data storage devices These codes all contribute to significantly

improving the reliability of information storage devices Some

of the proposed novel constrained codes for next-generation

storage devices have been presented [3-6] More complex ECC

techniques such as [7-9] have also been proposed recently

Moreover, 64/71-rate regular Hamming code and 64/72-rate

extended Hamming codes were suggested for STT-MRAM [2],

[10] Many advanced techniques have been proposed to improve

channel detection [11-16]

In recent years, the application of learning algorithms has

flourished and achieved many remarkable achievements

Machine learning and deep learning [17] are used in many fields

such as computer vision, natural language processing, image

processing, and many other areas This study proposes a model

that implements sparse encoding for user data and uses neural

network-based detection to detect the received signal The

obtained results show a significant improvement in detection

and decoding performance

The remainder of this paper is organized as follows The

cascaded STT-MRAM channel model is introduced in Section

II The proposed scheme is presented in Section III Simulation

results and discussion are shown in Section IV Finally, the

concluding remarks are shown in Section V

II CASCADED CHANNEL MODEL

This study adopts the STT-RAM cascaded channel model

suggested by Cai and Immink [2] to simulate the STT-MRAM

channel The channel model is briefly addressed as follows Let

𝑃1, 𝑃0, and 𝑃𝑟 denote the write error rate for 0 → 1 switching,

the write error rate for 1 → 0 switching, and the read disturb

error rate, respectively The significant deterioration in system

performance is largely due to the influence of these error rates

In general, the cascaded channel model combines write error and

read error models together A block diagram of the cascaded

channel model with write-0 direction is shown in Fig 2 The

write error is modelled by a binary asymmetric channel (BAC)

The read disturb error is modeled using a Z channel The read

decision error is modeled by a Gaussian mixture channel (GMC), where a Gaussian variable 𝑅0 given its mean and variance of 𝜇0 and 𝜎0 is represented for low resistance and a Gaussian variable 𝑅1 given its mean and variance of 𝜇1 and 𝜎1 has represented a high resistance, respectively The error probabilities for the BAC channel are given by 𝑃0 2 and 𝑃1 2,

respectively As shown in Fig 2, the signal c, the output of the

encoder, is passed through the wire error model BAC, the read disturb error model Z, and the GMC model in turn It is

straightforward to recognize that we can further combine the

BAC and Z channels to simplify the model The crossover

probabilities after combination can be expressed as follows,

𝑝0=𝑃0

2 (1 − 𝑃𝑟); 𝑝1=

𝑃1

2 + (1 −

𝑃1

2) 𝑃𝑟

𝑞0= (1 −𝑃0

2) +

𝑃0

2 𝑃𝑟; 𝑞1= (1 −

𝑃1

2) (1 − 𝑃𝑟) (1) III PROPOSED SCHEME

In fact, the write error events occur if the switching currents are not enough as the required ones before the MTJ switching completes This means the 0 → 1 switchings or 1 → 0 switchings may not be accomplished As reported in [15], the write failure

is asymmetric The failure probability of 0 → 1 switchings is higher than that of 1 → 0 switchings The conventional ECCs, such as Hamming and BCH code, offer the same error correcting capability for both bit-flipping directions [18] In other words, these codes do not seem to be the best solutions for handling asymmetric errors for STTMRAM systems Therefore, we use

a sparse code 7/9 suggested in [19] to overcome the asymmetric write failure rate of STT-MRAM It is important to note that the codewords at the output encoder only weight 2 and 4 For channel detection, we implement the recurrent neural network (RNN) to perform neural network channel detection

Fig 2 Cascaded STT-MRAM channel

1 1

1 1

1 1

Gaussian mixture channel

Read disturb error model

Write error model

Combined model

T ABLE I N ETWORK S ETTING F OR T HE P ROPOSED RNN A RCHITECTURE

Training samples 𝟓 × 𝟏𝟎 𝟒𝑵

Initializer Xavier uniform

The RNN-based detector is an advantageous technique in

processing sequential data RNN has memory to store previous

result information As a result, RNN can use this information to

improve the quality of tasks involving time-sequential data The

7/9 sparse code encodes the user signal at the transmitter The

signal is then stored in memory cells The output of the

STT-MRAM channel 𝒓 , which is the resistor values 𝒓 =

{𝑟𝑖,1, 𝑟𝑖,2, 𝑟𝑖,3, … , 𝑟𝑖,𝑁}, where N is the number of neurons at the

input layer, is fed into the RNN detector The output of the RNN

can be expressed as a function of the RNN input and the network

parameters 𝒉 as follows,

𝒄̂ = 𝑓(𝒓, 𝒉) (2) The job of the RNN is to find the most optimal network

parameters 𝒉∗, sometimes called a hypothesis, such that the loss

function, which represents the relationship between the model's

predicted outcome and the actual value, to be minimized It

means,

𝒉∗= arg min

𝒉 𝑳(𝒄, 𝒄̂ ) (3) where 𝑳 is the loss function The model's prediction results are

closer to the actual value as this loss function is minimized For

the RNN configuration, we use two hidden layers with a

rectified linear unit (ReLU) activation function The output layer

is a fully-connected layer with a sigmoid activation function

This study uses a gated recurrent unit (GRU) as the RNN cell

The RNN architecture is shown in Fig 3 The other system

configuration parameters of the RNN are shown in Table 1

IV SIMULATION RESULTS AND DISCUSSION

Experimental parameters for an STT-RAM cell are taken

from [2] The values of 𝜇0= 1 𝑘Ω and 𝜇1= 2 𝑘Ω , and

𝜎0⁄𝜇0= 𝜎1⁄𝜇1 The severity of the read decision errors can be

adjusted by changing the ratio The larger this value of 𝜎0⁄𝜇0 (and hence 𝜎1⁄𝜇1), the more severe the read decision errors, In this study, we adopt a fixed wire error rate of 𝑃1= 2 × 10−4 [2] For the offset effect, we consider an offset of resistance caused by the increase of temperature, which only occurs with the high resistance state 𝑅1 The offset is regarded as a Gaussian distribution where its mean and standard deviation are 𝜇𝑜𝑓𝑠 and

𝜎𝑜𝑓𝑠, respectively

The machine learning library Keras [20], with TensorFlow [21] as its back-end, is used in this study We perform the model training offline After training and evaluation processes, the network parameters 𝒉∗is used to detect the channel STT-MRAM output The signal at the transmitter is encoded 7/9 so that the output codewords always have weights of 2 and 4 At the receiver, the signal is decoded by a maximum likelihood decoder The block diagram of the system is shown in Fig 4

We first evaluate the quality of the RNN for each epoch during the training process The setup for simulation is at

𝜎0⁄𝜇0= 10%, 𝜇𝑜𝑓𝑠 = −0.2 𝑘Ω, and 𝜎𝑜𝑓𝑠⁄𝜇1= 4% As can

be seen in Fig 5, the RNN learns very fast After two epochs, BER performance converges

We consider the STT-MRAM channel model with and without offset in the subsequent simulations To evaluate the performance of the proposed model, we compare the proposed model with the case of the user signal without encoding and the

Fig 3 Diagram of RNN architecture for the NN-based detection

Dense

Sigmoid

GRU

Dense Sigmoid

Dense Sigmoid

Dense Sigmoid

Fig 5 RNN performance according to epoch

Fig 4 Block diagram of the system

case of the user signal with encoding but using a traditional

threshold channel detector The results are obtained at the

detector and decoder outputs The simulation results are shown

in Figs 6 and 7 It is observed that the system's performance is

improved significantly if the 7/9 sparse code encodes the user

signal In the case of using a traditional threshold detector,

however, the performance at the output of the decoder becomes

significantly worse The cause of this effect is a propagation

error Error bits at the detector output cause more severe error

bursts during decoding Consequently, the performance at the

output of the decoder is degraded For the case of the proposed

model, the performance of both detector and decoder has been

improved significantly The effect of error propagation is

eliminated This improvement is because the RNN detector

provides outstanding performance, which significantly reduces

the errors at the detector output However, as the channel

performance deteriorates, this value of 𝜎0⁄𝜇0 increases, the

detector performance degrades, and the performance of the

detector and decoder tends to converge Fig 7 shows the performance of the proposed model under the influence of offset The effect of propagation errors can be easily discerned using the traditional channel detector The proposed scheme provides much superior performance even with offset effects However, the same as the case without offset, the performance

of the detector and decoder tends to converge when the effects

of read decision errors are more severe

V CONCLUSION This study proposes using a 7/9-rate sparse code to encode the user signal and the RNN detector to detect the received signal Accordingly, the sparse code minimizes the effect of the asymmetric write error rate, which is the primary feature of the write failure rate in STT-MRAM systems The RNN detector significantly improves the channel output performance during the reading process The experimental simulation results have demonstrated the superiority of the proposed model The proposed model significantly improves the performance of the STT-MRAM system and substantially eliminates the effect of error propagation

This research is funded by Vietnam National Foundation for Science and Technology Development (NAFOSTED) under grant number 102.04-2019.307

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