THIET KE NANG CAO Flip Flop và thanh ghi có đường cho phép ngõ vào SRAM Bus dung chung... LIBRARY ieee ; USE ieee.std_logic_] 164.all ; ENTITY rege IS PORT R, Resetn, E, Clock :IN STD_
Trang 1THIET KE NANG CAO
Flip Flop và thanh ghi có đường cho phép ngõ vào
SRAM
Bus dung chung
Trang 2Zz LIBRARY ieee :
Flip Flop CO USE ieee.std_logic_1164.all ;
N ( ENTITY rege IS
` PORT (R, Resetn, E, Clock :IN STD_LOG
END rege ;
BEGIN PROCESS ( Resetn, Clock )
BEGIN
Q IF Resetn = ’0’ THEN
Q<='0';
IF E=’|° THEN
@Q<=R:
ELSE
Q<=Q:
END IF ; END IF :
END PROCESS ; END Behavior ;
Trang 3
LIBRARY ieee ;
USE ieee.std_logic_] 164.all ;
ENTITY rege IS
PORT (R, Resetn, E, Clock :IN STD_LOGIC ;
END rege ;
ARCHITECTURE Behavior OF rege IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = 0’ THEN
Q<='0';
ELSIF Clock’ EVENT AND Clock = °1° THEN
IFE =’! THEN
Q<=R:
ELSE
Q<=Q:
END IF;
END IF:
END PROCESS ;
END Behavior ;
Trang 4Thanh ghi dich co duo’ng cho
phép ngõ vào
Trang 5
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
right-to-left shift register with parallel load and enable
ENTITY shiftine IS
GENERIC (N : INTEGER := 4);
PORT( R > IN STD_LOGIC_VECTOR(N —1 DOWNTO 0) -
L,E,w : IN STD_LOGIC :
Q : BUFFER STD_LOGIC_VECTOR(N -1 DOWNTO 0) ) :
END shiftlne ;
Trang 6ARCHITECTURE Behavior OF shiftlne IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Cleck”7 EVENT AND Clock = °I’ ;
IF L= °1’ THEN
Q<=R;
ELSIE E = '1' THEN
QO(O) <= w;
Genbits: FORi IN 1 TO N—1 LOOP
Qi) <= Qti-b);
END LOOP ; END IF ;
END PROCESS ;
END Behavior ;
Trang 7SRAM
Sel
th
Figure 10.6 = An SRAM cell
Trang 8
Data, Data,
Figure 10.7 A2 x2 œrroy of SRAM cells.
Trang 9
Sel,
Sel,
œ1
a Š + e
Sel2„
Trang 10Bus dung chung
Data Extern
Bus
Function >
Control circuit
Trang 11
Bus
Rlị„—*
Figure 7.60 Using multiplexers to implemen