polymer metal oxide hybrid dielectrics for low voltage field effect transistors with solution processed high mobility semiconductors

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors MartinHeld,1,2,aStefan P.Schießl,1,2,aDominikMiehler

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

Martin Held, Stefan P Schießl, Dominik Miehler, Florentina Gannott, and Jana Zaumseil,

Citation: Appl Phys Lett 107, 083301 (2015); doi: 10.1063/1.4929461

View online: http://dx.doi.org/10.1063/1.4929461

View Table of Contents: http://aip.scitation.org/toc/apl/107/8

Published by the American Institute of Physics

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

MartinHeld,1,2,a)Stefan P.Schießl,1,2,a)DominikMiehler,1FlorentinaGannott,1,2

and JanaZaumseil2,b)

1

Department of Materials Science and Engineering, Friedrich-Alexander-Universit€ at Erlangen-N€ urnberg,

Erlangen D-91058, Germany

2

Institute for Physical Chemistry, Universit€ at Heidelberg, Heidelberg D-69120, Germany

(Received 27 June 2015; accepted 12 August 2015; published online 25 August 2015)

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should

operate at low voltages and be able to sustain high currents over long times without degradation

Hence, high capacitance dielectrics with low surface trap densities are required that are compatible

with solution-processable high-mobility semiconductors Here, we combine poly(methyl

methacry-late) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric

for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon

nano-tubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances

for both The ultra-thin PMMA layer ensures a low density of trap states at the

semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and

superior barrier properties Transistors with these thin (70 nm), high capacitance (100–300 nF/

cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities

and low threshold voltages Moreover, the hybrid layers substantially improve the bias stress

stabil-ity of the transistors compared to those with pure PMMA and HfOxdielectrics.V C 2015 Author(s)

All article content, except where otherwise noted, is licensed under a Creative Commons

Attribution 3.0 Unported License [http://dx.doi.org/10.1063/1.4929461]

High-mobility solution-processable semiconductors such

as donor-acceptor polymers1,2or single-walled carbon

nano-tubes (SWNTs)35 are attractive for flexible and printable

electronics With mobilities higher than 1 cm2V1s1, they

have the potential for application in drive transistors of

active-matrix organic light-emitting diode (OLED) displays.68

However, not only high mobilities but also low drive voltages

are required These are enabled by high-capacitance

dielec-trics that can be achieved with ultrathin organic insulating

layers9,10or with high-k dielectrics.11The deposition of metal

oxides by atomic layer deposition (ALD) or sputtering on

or-ganic semiconductors causes irreversible damage12and is thus

not suitable for top-gate transistors But even in bottom-gate

transistors high-k dielectrics such as hafnium oxide (HfOx)

lower the carrier mobility due to the large dipolar disorder.13

Unpassivated interfacial trap states at the semiconductor

dielectric interface cause current hysteresis and threshold

shifts in both organic semiconductor and semiconducting

SWNT network field-effect transistors (FETs).14Low-k

poly-mers are preferred as dielectrics despite their low breakdown

strengths, high probability of pinholes, necessity of relatively

thick layers (>100 nm) and thus low capacitances These

issues led to the idea of using organic buffer layers on oxide

dielectrics15 and hybrid dielectrics consisting of layers16 or

blends17 of high-k and low-k insulators Especially, layered

hybrid dielectrics consisting of a polymer insulator at the

semiconductor surface and a pinhole-free high-k material with

higher breakdown strength are attractive as they combine the

advantageous properties of both and can be applied to a wide range of semiconductors.12,18–20

Here, we demonstrate a high-capacitance bilayer hybrid dielectric of poly(methyl methacrylate) PMMA and ALD HfOxfor top-gate FETs that can be processed at low temperatures compatible with polymer substrates It ena-bles low drive voltages (<5 V), maintains a low interfacial trap state density, and provides efficient encapsulation for hole and electron transport in air The hybrid dielectric substantially improves the performance of FETs based on high-mobility polymers as well as semiconducting SWNT networks and allows FETs to operate without degradation under extended bias stress

The donor-acceptor polymer DPPT-TT (poly(2,5-bis(2-octyldodecyl)–3 -(5–(thieno[3,2-b]thiophen-2,5-yl)thiophen-2-yl)–6 -(thiophen-2,5-yl)pyrrolo[3,4-c]pyrrole-1,4(2 H,5 H)-dione)) and polymer-sorted semiconducting SWNTs (diameter 1.2–1.5 nm) were chosen as representative semiconductors They are both solution-processable and exhibit high ambipo-lar carrier mobilities.21,22Bottom-contact top-gate transistors (see Fig 1(a)) were fabricated on glass substrates (Schott AF32 Eco) Source-drain electrodes (channel width/length W/L¼ 125, L ¼ 40 lm) were patterned by photolithography, evaporation of Cr (2 nm)/Au (30 nm) and lift-off DPPT-TT (Mn¼ 23 kg mol1, Mw¼ 87 kg mol1, Flexink Ltd.) was spin-coated from 1,2-dichlorobenzene (o-DCB) (10 mg ml1,

1000 rpm, 30 nm) and annealed for 30 min at 200C SWNTs (NanoIntegris, Inc., RN-220, plasma torch SWNTs, diameter 0.9–1.9 nm, SWNT content 60%–70%, approxi-mately 70% semiconducting SWNTs) were selectively dispersed with poly(9,9-di-n-dodecylfluorenyl-2,7-diyl)

a) M Held and S P Schießl contributed equally to this work.

b) Author to whom correspondence should be addressed Electronic mail:

zaumseil@uni-heidelberg.de.

(Sigma Aldrich, Mw¼ 10 kg mol1, Mn¼ 4.7 kgmol1) in

toluene as previously reported22 (see supplementary material

S123) and polymer-free dispersions were spin-coated at

2000 rpm and annealed for 45 min at 300C Dielectric layers

were deposited before thermal evaporation of 35 nm silver as

the gate electrode completed the FETs PMMA (Polymer

Source, syndiotactic,Mw¼ 350 kg mol1) layers were applied

via spin-coating PMMA/n-butylacetate solutions with different

concentrations and spin speeds Hafnium oxide layers were

de-posited by ALD (Ultratech Savannah S100) using

tetrakis(di-methylamino)hafnium (TDMAH) as hafnium precursor and

water as oxygen source at 100C DPPT-TT transistors were

fabricated with PMMA (470 nm, 60 mg ml1, 2000 rpm) and

hybrid dielectrics (11 nm PMMA, 6 mg ml1, 6000 rpm and

HfOx, 38 nm, 300 ALD cycles) SWNT transistors were

fabri-cated with HfOx(61 nm, 500 ALD cycles) and hybrid (11 nm

PMMA, 6 mg ml1, 6000 rpm and HfOx, 61 nm, 500 ALD

cycles) dielectrics All processing steps were carried out in dry

nitrogen Parallel-plate capacitors for capacitance and

break-down strength measurements of various PMMA, HfOx and

hybrid layers consisted of photolithographically patterned Cr/

Au pads (2500 lm2) on glass and shadow mask evaporated Cr/

Au top electrodes Current-voltage characteristics of the

tran-sistors were recorded with an Agilent 4156 C Semiconductor

Parameter Analyzer Gate dielectric capacitances were

meas-ured with an Agilent E4980A Precision LCR Meter at 5000 Hz

or 1000 Hz

We first established the dielectric properties of single

PMMA and HfOxlayers and the hybrid bilayer depending on

layer thickness, as shown in Fig.1(b) Even for very thin layer

thicknesses, which are prone to pinholes and leakage currents,

the capacitance of PMMA is low compared to HfOx The

capacitances of the hybrid layers are between those of PMMA

and HfOx and can be modelled well by two parallel-plate

capacitors in series with the permittivities of the single layers

(PMMA: e¼ 2.6 6 0.7; HfOx: e¼ 14.3 6 0.4) The

permittiv-ity e of the single dielectric layers was obtained by fitting the

capacitance per area C versus the layer thickness d with

C¼ee 0

d The breakdown strength of hybrid dielectrics

consist-ing of a very thin PMMA layer and a HfO layer on top is 1–3

MV/cm, which allows for safe low-voltage operation (see sup-plementary material S223) More importantly, the conformal ALD of HfOx fills pinholes, which are unavoidable in thin PMMA layers (<120 nm) over larger areas and prevent device operation at any voltage Leakage current and breakdown probability are significantly reduced with the hybrid dielectric, the device yield is high and device variability low The maxi-mum possible charge carrier density (taking into account the breakdown voltage and the capacitance) that could be accu-mulated with a hybrid dielectric of 6 nm PMMA and 38 nm HfOxis 2 1013cm2 It does not reach that of a thin HfOx layer with about 5 1013cm2but clearly exceed thin single layers of PMMA with 0.1 1013cm2 In addition, the hybrid dielectric also provides a low-k dielectric interface with few trap states that should be beneficial for FET performance Figure2(a)shows the transfer characteristics of FETs with DPPT-TT and SWNTs as the semiconductor and PMMA, HfOxor hybrid layers as the dielectrics No work-ing transistors of DPPT-TT were obtained with ALD-HfOx directly deposited onto the semiconductor Thus, we com-pare single layer PMMA and the hybrid layer Typically,

400 nm of PMMA are required to reliably avoid pinholes and severe gate leakage in polymer FETs This leads to very high operating voltages as shown in Fig.2(a) In con-trast to that DPPT-TT FETs with a hybrid dielectric of

11 nm of PMMA and 38 nm of HfOxoperate at a tenth of that voltage (see Fig 2(b)) The metal oxide of the hybrid dielectric also provides orders of magnitude lower water vapor permeability than PMMA and acts as an encapsulat-ing layer DPPT-TT FETs with hybrid dielectrics could be operated in air without further encapsulation and without degradation, whereas FETs with single thick PMMA layers showed strong p-doping and increased hysteresis of the electron current after a short time in air (see supplementary material S323) The saturation mobilities of holes and

FIG 1 (a) Top-gate, bottom-contact FET geometry with different

dielec-trics (HfO x , PMMA versus hybrid dielectric) and different semiconductors

(DPPT-TT and semiconducting SWNT network) (b) Capacitance as a

func-tion of total layer thickness for hafnium oxide, PMMA, and hybrid

dielectric.

FIG 2 Transfer characteristics of FETs with DPPT-TT as the semiconduc-tor and with (a) PMMA and (b) PMMA/HfO x as the dielectric Transfer characteristics of network SWNT FETs with (c) HfO x and (d) hybrid dielec-tric Channel width/length ratio and channel lengths were 125 and 40 lm, respectively.

electrons in DPPT-TT FETs with the hybrid dielectric were

more balanced (lh¼ 0.37 6 0.04 cm2V1s1; le¼ 0.12

6 0.01 cm2V1s1) than for the pure PMMA dielectric

(lh¼ 0.43 6 0.03 cm2V1s1, le¼ 0.06 6 0.001 cm2V1s1)

This might be due to the improved encapsulation of the

hybrid devices and the extended annealing during the ALD

process at 100C The extraction of the linear mobility was

omitted for these FETs because of the non-ohmic contact

re-sistance (see supplementary material S423)

Since dense semiconducting networks of carbon

nano-tubes generally show higher effective mobilities than even

the best semiconducting polymers,22we also investigated the

effects of a hybrid dielectric for SWNT-FETs Pure PMMA

as a dielectric would again require thick layers (>400 nm)

due to the intrinsic roughness of the SWNT films However,

SWNTs can withstand deposition of metal oxides as

dielec-trics and low-voltage FETs with ultrathin layers were

dem-onstrated.24,25 Hence, we will compare ALD-HfOxand the

hybrid dielectric Figure2(c)shows the transfer

characteris-tics of FETs with random semiconducting SWNT networks

with 61 nm of HfOx Although they work at low voltages,

they show n-doping, strong threshold shifts and hysteresis

This behavior was independent of the ALD temperature

(100C and 200C) A closer look at the HfOxgrowth on

SWNTs may provide an explanation for the strong

hystere-sis Atomic force microscopy (AFM) images of SWNT

net-works after the deposition of 7 nm of HfOxshow island-like

growth that appears to be inhibited on the SWNTs (see

sup-plementary material S523) Several studies have

demon-strated that defect-sites are necessary to start ALD on

SWNTs and thus a uniform coverage is difficult to

obtain.26,27 Although after 500 cycles clearly a continuous

HfOxfilm (61 nm) is formed as corroborated by the low gate

leakage currents, the initial island growth may give rise to

incomplete coverage, non-stoichiometric hafnia, and thus

interfacial traps By using the hybrid dielectric (11 nm

PMMA, 61 nm HfOx) instead of pure HfOxfor SWNT

net-work FETs almost ideal ambipolar transfer characteristics

without hysteresis and with turn-on voltages close to zero

were accomplished (Fig.2(d)) AFM images of SWNT

net-works after spin-coating of the PMMA layer show that this

thin layer already provided good planarization and deposition

of HfOxonto this layer was more uniform (see supplementary

material S523) The output curves for all SWNT-FETs (see

supplementary material S423) indicate ohmic injection of

holes and electrons The linear mobilities (calculated with

quantum capacitance corrected capacitances, see

supplemen-tary material S623) were extracted for both dielectrics The

hybrid layer clearly enables higher linear mobilities

(lh¼ 44.2 6 14.1 cm2V1s1; le¼ 34.0 6 7.0 cm2V1s1)

than the pure HfOx dielectric (lh¼ 1.1 6 0.3 cm2 V1 s1;

le¼ 4.9 6 0.3 cm2 V1 s1) The reduced mobilities in the

SWNT FETs with HfOxare most likely caused by the higher

density of charge traps at the SWNT-HfOxinterface In

addi-tion, polar dielectrics such as hafnia are expected to lead to

strong surface polar phonon scattering and thus lower carrier

mobilities as shown by Perebeinoset al.28

In order to estimate the amount of trap states for all

semiconductor/dielectric combinations, trap-related

parame-ters such as the capacitance-corrected threshold voltages

VthC and subthreshold swings SS C were analyzed (see TableI) Absolute values for the threshold voltages and sub-threshold swings are listed in the supplementary material S7.23 For conservative estimates, the lower value for the threshold voltages and the higher values for the subthreshold swings were chosen From SS C, one can calculate the interfacial trap densityDtraccording to

Dtr¼C

q SS

logð Þe kT=q  1

with the elementary chargeq, and thermal energy kT.29 For DPPT-TT FETs with a pure PMMA dielectric, all trap-related parameters (SS C, VthC and Dtr) indicate that the electron trap density exceeds the trap density for holes, which partially explains the lower electron mobilities PMMA is an inferior water vapor barrier and water with oxy-gen can act as an electron trap (even under glovebox condi-tions).30 FETs with hybrid dielectrics show slightly lower trap densities for electrons possibly due to the improved encapsulation by the HfOx and the extended annealing However, the overall differences are not large, which was expected, given that the PMMA/DPPT-TT interface remains the same

In contrast to that, we find significant differences between random SWNT-network FETs with HfOx and hybrid dielectrics The capacitance-corrected subthreshold swings in FETs with HfOxwere 2–3 times higher than for the hybrid dielectric The largerVthC for holes compared to electrons and the large hysteresis in the HfOx devices (DVthC 200 nC cm2) already indicate the presence of trap-states The hybrid dielectric provides a much lower sur-face trap density, which is reflected in the higher carrier mobilities, lack of current hysteresis, and sharp subthreshold swings

Both high-mobility donor-acceptor polymers as well as SWNT networks are possible candidates as semiconductors

in FETs for OLED display backplanes The required low operating voltages can already be accomplished by using the hybrid dielectrics However, drive transistors must also be able to withstand long operation times with large current densities without degradation.7This requirement is a particu-lar problem for SWNT FETs.31Hence, bias stress tests were performed in order to evaluate the long-term stability of

TABLE I Trap-related device parameters for different dielectrics/semicon-ductor combinations.

Semiconductor/dielectric SS  C a nF

cm 2 V dec

V th C b nC

2

D trc 10 12

eV cm 2

a Capacitance-corrected subthreshold swing.

b Capacitance-corrected threshold voltage.

c Interfacial trap density.

these transistors We stressed all FETs for 10 h at constant

gate and drain voltages (see Fig 3) For the DPPT-TT/

PMMA FETs, the on-current decreased by 16% The

SWNT/HfOxFETs suffered an on-current drop of about an

order of magnitude In contrast to that the hybrid dielectrics

in combination with both semiconductors led to constant

on-currents without any degradation over 10 h, which again

cor-roborates the advantages of PMMA as a buffer dielectric

especially for SWNT FETs

In summary, we showed that the application of a bilayer

hybrid dielectric consisting of a thin PMMA layer next to the

semiconductor and a high-k hafnium oxide layer on top

dras-tically reduces the operating voltages of FETs based on two

promising solution-processable high-mobility

semiconduc-tors, i.e., the donor-acceptor polymer DPPT-TT and sorted

SWNT-networks In comparison to pristine dielectrics

(PMMA or HfOx) the PMMA/HfOxhybrid dielectric enables

low-voltage operation, well-balanced charge carrier

trans-port, low trap densities, and excellent bias stress stability In

addition, the top oxide layer is self-encapsulating and thus

provides environmental stability The low processing

tem-peratures of the hybrid dielectric (100C) are compatible

with flexible polymer substrates

This research was funded by the European Research

Council under the European Union’s Seventh Framework

Programme (FP/2007-2013)/ERC Grant Agreement No

306298 (EN-LUMINATE) J.Z thanks the Alfried Krupp

von Bohlen und Halbach-Stiftung via the “Alfried Krupp

Forderpreis f€ur junge Hochschullehrer” and the Cluster of

Excellence “Engineering of Advanced Materials” (EXC 315)

for general support The authors thank Udo Mundloch and

the Institute of Advanced Materials and Processes (ZMP

F€urth) for help with ultra-centrifugation

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FIG 3 Bias stress tests of (a) DPPT-TT and (b) SWNT-based transistors

with different dielectrics.