CMOS VLSI Design - Lecture 4: Nonideal Transistor Theory pdf

CMOS VLSI Design CMOS VLSI Design 4th Ed.Ideal Transistor I-V  Shockley long-channel transistor models 2 cutoff linear saturatio... CMOS VLSI Design CMOS VLSI Design 4th Ed.Coffee Cart

Lecture 4: Nonideal

Transistor Theory

 Nonideal Transistor Behavior

– High Field Effects

• Mobility Degradation

• Velocity Saturation – Channel Length Modulation

– Threshold Voltage Effects

• Body Effect

• Drain-Induced Barrier Lowering

• Short Channel Effect – Leakage

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Ideal Transistor I-V

 Shockley long-channel transistor models

( )2

cutoff linear saturatio

Ideal vs Simulated nMOS I-V Plot

Channel length modulation:

Saturation current increases with V ds

I on = 747 mA @

Vgs = Vds = VDD

Simulated

Ideal

Velocity saturation & Mobility degradation:

Saturation current increases less than quadratically with V gs

Velocity saturation & Mobility degradation:

I on lower than ideal model predicts

CMOS VLSI Design CMOS VLSI Design 4th Ed.

ON and OFF Current

200 400 600 800 1000

Electric Fields Effects

– Attracts carriers into channel

– Accelerates carriers from drain to source

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Coffee Cart Analogy

 Tired student runs from VLSI lab to coffee cart

 Freshmen are pouring out of the physics lecture hall

– Your velocity = fatigue × mobility

Mobility Degradation

– Collisions with oxide interface

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Velocity Saturation

– Carriers scatter off atoms in silicon lattice

– Better model

Vel Sat I-V Effects

 Real transistors are partially velocity saturated

– Approximate with α-power law model

2 ox

gs t

V V W

CMOS VLSI Design CMOS VLSI Design 4th Ed.

linear saturation

β

Channel Length Modulation

 Reverse-biased p-n junctions form a depletion region

– Region between n and p with no carriers

Gate Source Drain

bulk Si

n +

VDDGND VDD

GND

L

Leff

Depletion Region Width: Ld

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Chan Length Mod I-V

– not feature size

– Empirically fit to I-V characteristics

1 2

Threshold Voltage Effects

 Really depends (weakly) on almost everything else:

– Body voltage: Body Effect

– Drain voltage: Drain-Induced Barrier Lowering

– Channel length: Short Channel Effect

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Body Effect

 Body is a fourth transistor terminal

 Vsb affects the charge required to invert the channel

– Increasing Vs or decreasing Vb increases Vt

 φs = surface potential at threshold

– Depends on doping level NA

– And intrinsic carrier concentration ni

 γ = body effect coefficient

n

φ =

si ox

Body Effect Cont.

 For small source-to-body voltage, treat as linear

CMOS VLSI Design CMOS VLSI Design 4th Ed.

DIBL

 Electric field from drain affects channel

 More pronounced in small transistors where the

drain is closer to the channel

 Drain-Induced Barrier Lowering

ttds VVVη

t t ds

V ′ = − V η V

Short Channel Effect

 In small transistors, source/drain depletion regions

extend into the channel

– Impacts the amount of charge required to invert the channel

– Some processes exhibit a reverse short channel

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Leakage Sources

 Subthreshold conduction

– Transistors can’t abruptly turn ON or OFF

– Dominant source in contemporary transistors

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Subthreshold Leakage

 Subthreshold leakage exponential with Vgs

 n is process dependent

– typically 1.3-1.7

 Rewrite relative to Ioff on log scale

 S ≈ 100 mV/decade @ room temperature

Gate Leakage

 Carriers tunnel thorough very thin gate oxides

– A and B are tech constants

– Greater for electrons

• So nMOS gates leak more

From [Song01]

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Junction Leakage

 Reverse-biased p-n junctions have some leakage

– Ordinary diode leakage

Diode Leakage

 Reverse-biased p-n junctions have some leakage

– And area and perimeter of diffusion regions

e 1

D T

V v

I I  

=  − 

 

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Band-to-Band Tunneling

 Tunneling across heavily doped p-n junctions

– Especially sidewall between drain & channel

 Increases junction leakage to significant levels

– A, B: tech constants

Gate-Induced Drain Leakage

 Occurs at overlap between gate and drain

a negative voltage– Thwarts efforts to reduce subthreshold leakage using a negative gate voltage

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Temperature Sensitivity

 Increasing temperature

– Reduces mobility

Vgs

ds

I

increasing temperature

So What?

 So what if transistors are not ideal?

– They still behave like switches

 But these effects matter for…

– Supply voltage choice

– Logical effort

– Quiescent power consumption

– Pass transistors

– Temperature of operation

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Parameter Variation

 Transistors have uncertainty in parameters

– Vary around typical (T) values

 Not all parameters are independent

for nMOS and pMOS

CMOS VLSI Design CMOS VLSI Design 4th Ed.

Process Corners

 Process corners describe worst case variations

– If a design works in all corners, it will probably

work for any variation

 Describe corner with four letters (T, F, S)

– nMOS speed

– pMOS speed

– Voltage

– Temperature

Important Corners

 Some critical simulation corners include