With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition dv/dt for the DVS is pushing the physical limitation of the multiphase co
Introduction to Multiphase Buck Converter
As modern high-end processors feature an exponential increase in transistors, their supply current specifications often exceed 100A, necessitating multiple regulators in parallel to reduce thermal stress on power components such as MOSFETs and inductors Multiphase buck converters have become the standard solution for efficient power conversion in this context Despite their longstanding use in power management, ongoing research is essential to address the growing complexity of power architectures and the rising emphasis on green energy, which aims to minimize power losses and reduce the number of output capacitors for more sustainable electronic systems.
Figure 1 4 A multiphase synchronous buck converter for CPU application
Figure 1 5 shows the relationship of normalized ripple current between duty cycle and phase number
Figure 1 5 Normalized ripple current as a function of phase number and duty cycle
The benefits of adopting multiphase buck converter in the design are bulleted as follows:
Decreased IRMS and reduced power loss;
Increased inductor current slew rate: 𝐿 𝑒𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 = 𝐿
Output inductor current cancellation and voltage ripple reduction;
Optimized efficiency over the whole load range, especially, in light load o Load adaptive control(LAC) o Pulse skipping control(PFM)
Better dynamic voltage regulation capability
However, with those advantages, there are challenges that the multiphase converter have brought in as well The challenges are the major focus of this dissertation
Figure 1 6 A typical power delivery path for today’s microprocessors
Figure 1 illustrates a typical power delivery path for modern microprocessors, emphasizing the importance of placing power inductors and output capacitors close to the processor This proximity is essential to minimize power distribution loss and ensure efficient power delivery, despite mechanical restrictions that limit component placement options.
Figure 1 7 Power distribution impedance versus frequency
The closed-loop output impedance of a voltage regulator is a critical parameter in the frequency domain, influencing the regulator's stability and performance As illustrated in Figure 1.7 [2], the output impedance of a CPU power supply with AVP is depicted, with the red curve representing the impedance profile This output impedance is primarily determined by the regulator's feedback loop characteristics, which are essential for ensuring optimal regulation and transient response in CPU applications.
7 power supply's AVP design value within the loop bandwidth of the VR At higher frequency, the output impedance will be dominated by the ESL of MLCC and the socket
The pyramid of server power design emphasizes robustness as the top priority, as systems handle critical customer data where power-related failures can halt transactions, leading to significant losses Ensuring high power conversion efficiency is fundamental, requiring rigorous optimization of design parameters and adoption of the latest silicon technologies Innovations like phase shedding control and load transient enhancements demonstrate advancements that boost system reliability, efficiency, and cost-effectiveness Ultimately, cost reduction serves as the final step in optimizing the design, minimizing environmental impact while maintaining high performance.
Figure 1 8 Robustness, efficiency and cost pyramid in server power design
Adaptive Voltage Positioning
Figure 1 9 illustrates the comparison results of AVP implementation when load transient events occur The introduced AVP window can be fully utilized to optimize the load transient
Figure 1 9 Load transient without and with AVP implementation.
Figure 1 10 AVP design in analog realization
Figure 1 10 illustrates the block diagram of AVP design in an analog realization [6]
Figure 1 11 AVP design in digital realization
The adaptive voltage position (AVP) design utilizes the entire AVP window to accommodate voltage excursions during transient events, enhancing system stability One key advantage of implementing the AVP scheme is its ability to maintain the output power of the multiphase voltage regulator (VR) at full load, which results in reduced thermal stress compared to designs without AVP.
Figure 1 12 Output power comparison with different LL
The sensed inductor current's differential output is fed into a dedicated ADC for digitization, and these values are summed to determine the total load current The VREF is generated by subtracting the filtered (averaged) sum of the phase currents, multiplied by the load line, from the current VID.
Review of Prior Arts
Constant ON-time (COT)
Constant ON-time (COT) is a popular frequency modulation scheme which is capable of achieving fast transient response
The core component of the modulator is the one-shot circuit responsible for setting the HS ON-time This ON-time (TON), as illustrated in equation (1.2), is inversely proportional to the input voltage (VIN) and directly proportional to the output voltage (VOUT).
When the feedback voltage (VFB) drops below the reference voltage (VREF), the next switch-on period is triggered, maintaining the pulse for a predetermined duration as defined by equation (1.2) The clock-less architecture offers the advantage of initiating the high-side (HS) pulse more promptly during transient conditions, enhancing responsiveness and regulation performance, as illustrated in Figure 1.13.
A minimum OFF-time between the high-side (HS) pulses is essential to ensure accurate current sensing This minimum OFF-time also determines the maximum duty cycle that the voltage regulator (VR) can support, impacting overall system performance and efficiency.
Figure 1 14 Simplified voltage mode COT architecture with ripple injection
The D-CAP2 control scheme by Texas Instruments features an internal ripple generation circuitry (RCC) that enables improved performance, as shown in Figure 1 This advanced design allows the use of multi-layer ceramic capacitors (MLCC) with very low ESR, thanks to the ripple injection mechanism The hybrid control mode combines emulated inductor current ripple with voltage feedback signals to enhance control accuracy and efficiency in power management systems.
To meet small-signal stability, the output capacitance value should be governed by (1.3)
3 (1 3) where G =0.25 RC1× CC1 time constant can be referred to TPS53819 datasheet D is the duty cycle
Current Mode Hysteresis
Hysteretic control is widely used in fast transient applications due to its quick response capabilities However, traditional hysteretic control has a drawback in that its switching frequency is variable and clock-less, primarily influenced by parasitic elements like the ESR of the output capacitor To address this issue, advanced hysteretic control techniques incorporate frequency stabilization methods, such as phase-locked loops, to maintain a consistent switching frequency.
Intersil refers to the R4 (Robust Ripple Regulator as described with R3) Modulator as a
The Current-Mode Hysteretic (CMH) modulator is a variable frequency switching architecture that operates without a clock, using a hysteretic band to compare against a synthesized "current" ripple, rather than true inductor current This design eliminates the need for compensating ramps, voltage feedback compensation, and integrators, enabling fast transient response and simplified deployment Unlike traditional current-mode controllers, CMH does not use actual inductor current for modulation but generates a synthetic current ripple to determine power switch on and off times, providing a more straightforward and responsive power management solution.
Figure 1 15 Simplified R4™ modules for PWM generation
Figure 1 illustrates the core components of the R4 controller, including the modulator core, error amplifier, synthetic current generator, and hysteretic window comparator The error voltage, produced by subtracting feedback from the VDAC output, is used to monitor and compare the synthetic current signal against a specified window voltage This comparison triggers the PWM switching events, ensuring precise regulation of the system.
Figure 1 16 Simplified operation waveform during load transient
Figure 1 illustrates the operational waveform during load assertion and load release The switching frequency, represented by the magenta curve, increases during load assertion and decreases during load release Both PWM edges are modulated based on the comparison of the synthetic current against the hysteric upper window and the VCOMP voltage, ensuring precise control of the switching operation.
EAPP
Minimizing control loop delay during transient events is crucial for optimal system performance Enhanced Active Pulse Positioning (EAPP) leverages the advantages of trailing and leading edge modulation during switching ON and OFF to reduce delays By combining these modulation schemes, as discussed in reputable sources like [24], EAPP effectively minimizes both ON and OFF switching delays, ensuring faster and more reliable control response in dynamic conditions.
Figure 1 17 Schematic diagram of EAPP circuitry.
The simplified block diagram and the corresponding operational waveforms are depicted in Figure 1, illustrating the system's functioning During transient events, the EAPP activates PWM earlier (from t3 to t2) and advances the subsequent PWM (from t8 to t7) to minimize blanking time Figure 5 demonstrates the transient load engagement response of a 3-phase VR system with EAPP, showcasing its effectiveness in managing sudden load changes.
Figure 1 18 Dual-Edge and Variable-Frequency Operational Waveforms.
Dissertation Outlines
Chapter 1 highlights the critical role of power management ICs across various industries, emphasizing their importance for efficient energy regulation It introduces the scenario of multiphase synchronous buck converters and explores AVP (Adaptive Voltage Positioning) design techniques that effectively reduce output capacitor size and minimize power dissipation The chapter also reviews ongoing research and advanced control topologies, with a focus on nonlinear control schemes that enhance converter performance and reliability.
In chapter 2, we start the efficiency optimization from static operation First, we design the compensation of the voltage mode controller with digitized format We meticulously study
This article explores power loss across various operational modes of CPU voltage regulators, including buck, PFM, and boost modes, ensuring comprehensive coverage of all typical operating scenarios It provides an in-depth analysis of the driver interface to enhance operational stability and efficiency By examining switching waveforms and accounting for parasitic elements, the study offers a clearer understanding of switching behavior Additionally, an efficiency optimization routine is developed through parametric variation, enabling improved performance and reduced power loss in CPU voltage regulation systems.
In Chapter 3, we introduce load transient enhancement schemes designed to minimize output voltage excursions during low repetitive load transients Key strategies include leveraging DCR current sensing in the AVP loop to effectively shape voltage responses, ensuring rapid pulse engagement to counteract voltage deviations during load increases, and implementing adaptive body braking schemes to suppress voltage overshoot during load releases Additionally, special design considerations are emphasized during slow phase shedding, where inductor current must be ramped down to zero before phase turn-off To address potential shoot-through in power MOSFETs, a new dead-time management scheme is proposed, maintaining high efficiency, preventing shoot-through, and ensuring system reliability.
In Chapter 4, the sampling characteristics of the PWM converter are analyzed, with a focus on deriving the output impedance of the closed-loop system The chapter details the optimization of compensation networks in the high-frequency range to effectively attenuate system noise Additionally, the study examines beat frequency phenomena and proposes a load frequency detection scheme combined with current protection mechanisms within the control loop to mitigate interference and limit phase current, ensuring enhanced system stability and performance.
Multiphase converter design capable of dynamic voltage scaling (DVS) is presented in chapter 5 Modes of operation are thoroughly studied first Optimized driver dead-time in boost
This article discusses a 18-mode operation technique that enables DVID downward transitions using shared phase current, enhancing control flexibility It highlights that boost mode operation can induce excessive stress on the control MOSFET, raising reliability concerns, which are addressed through feasible solutions verified by simulation and experimental results The paper proposes CdV/dt compensation methods to eliminate the AVP effect and introduces a novel nonlinear control scheme for smooth voltage transitions during fast voltage positioning Additionally, it presents an optimal phase number control strategy during dynamic voltage transitions, triggered by voltage identification (VID) delta, to further minimize dynamic losses and improve overall system efficiency.
Chapter 6 presents the conclusions and the future work is outlined
CHAPTER TWO: OPTIMIZATION ON STATIC OPERATION
Figure 2 1 The architecture of the bidirectional multiphase synchronous controller
The architecture of the multiphase synchronous buck converter, capable of bidirectional operation, is illustrated in Figure 2.1, featuring interleaved phases at 360/N degrees to optimize ripple cancellation The controller comprises key modules including current ADCs that sample and digitize each phase current via the voltage across the inductor DCR sense network in real time, while voltage ADCs monitor and digitize both VOUT and VBUS, with the latter serving as a feed-forward term in the control loop The Adaptive Voltage Positioning (AVP) module decodes VID commands and generates reference voltages based on total phase current data with DVID compensation A digital compensator filters errors from ADC outputs and AVP signals, feeding control signals into the DPWM generator Additionally, the current balance module—designed as one-fifth of the voltage loop—and the nonlinear PWM generator modulate the DPWM patterns, producing control outputs such as PWM signals and driver enable (DR_EN) signals to ensure efficient converter operation.
Compensation Design
Direct Digital Design
Due to the double pole of output filter in the voltage mode control, as shown in Figure 2
3, two zeros from the type III compensation network are needed so that the phase can be boosted by 180 degrees There are two methods to design the digital compensation network:
(1) Emulation method, design the analog compensation first in Laplace domain and transfer to digital domain
(2) Direct digital design, design the compensation network in digital domain by first digitizing the plant
Figure 2 3 Generic type III compensation network
Figure 2 4 Digital control loop block diagram
Digitalizing a plant can be achieved through various methods such as Zero-Pole Matching (ZPM), Impulse Invariant Mapping, and Tustin Approximation; among these, ZPM is preferred for its accuracy in system conversion Ensuring matched DC gains between the analog and discretized systems is essential for maintaining system fidelity The transformation of zeros and poles during the discretization process is performed using specific equations, facilitating precise digital representation of the plant.
In discrete-time system analysis, the pole or zero of the discretized system (zi) is obtained by dividing the continuous-time pole or zero (si) by the sampling frequency (FS), as expressed by the formula zi = es_i / FS This relationship ensures accurate system discretization, maintaining the stability and characteristics of the original continuous system during digital implementation Proper understanding of this conversion is essential for effective digital signal processing and control system design.
Root Locus and Bode Plot
Root locus is a powerful graphical method for analyzing the locations of poles and zeros of a system's characteristic equation, providing insights into system stability and transient response Utilizing MATLAB's SISO Design Tool enables precise placement of poles and zeros, helping to optimize system performance by achieving desired bandwidth and phase margin This approach facilitates effective control system design and tuning, ensuring robust and reliable operation.
Figure 2 5 shows the system root locus plot using Matlab
Figure 2.6 illustrates the compensator gain across the frequency domain, highlighting that KI and KD dominate in both low and high-frequency ranges, ensuring effective control throughout the spectrum Kp maintains a stable gain in the middle frequency range, directly influencing the loop bandwidth for optimal system performance Additionally, Kfp plays a crucial role in high-frequency noise reduction by rolling off the loop gain, thereby minimizing high-frequency disturbances and enhancing overall system stability.
Power Loss Analysis
To ensure comprehensive system compatibility, the VR design in server applications must support both multiphase and single-phase configurations, covering all loading conditions Careful power budgeting is essential, as illustrated in Figure 2.7, which depicts a typical power distribution in percentage terms to optimize efficiency and reliability across diverse system loads.
Figure 2 7 A power design breakdown in server application
Understanding and optimizing power conversion losses [26]-[29] is essential for improving efficiency The loss model varies based on different operation modes of the buck converter, which are categorized into CCM buck, CCM boost, and PFM buck modes Corresponding power loss representations, aligned with inductor current profiles, are illustrated in Figures 2.8, 2.10, and 2.12, providing clear insights into each mode’s unique loss characteristics.
Figure 2 8 Power loss distribution of a synchronous buck in buck mode
Power loss simulation and experimental verification should be conducted across different switching frequencies and PVCC (MOSFET drive voltage) settings to ensure comprehensive analysis The power loss in a synchronous buck converter is governed by specific equations that describe the losses when the VR operates in this mode Understanding these equations is essential for optimizing efficiency and minimizing energy wastage in power management systems.
Recent advancements in power MOSFET technology have prioritized ultra-low channel resistance and ultra-fast switching speeds to enhance efficiency and performance The figure of merit (FOM) is a crucial metric used to assess MOSFETs under the same breakdown voltage, enabling better comparison of device performance Industry-leading low voltage power MOSFETs, such as Infineon’s OptiMOS™ and Fairchild Semiconductor’s PowerTrench®, set the standard for cutting-edge innovation and reliability in power electronics.
The conduction loss is the resistive loss due to current conducted through the channel resistance Rds_ON
P COSS is the power loss caused by the output capacitance of MOSFET
P deadtime represents the body diode conduction loss during t deadtime
The equation for dead time, denoted as 𝑡𝑑𝑒𝑎𝑑𝑡𝑖𝑚𝑒(𝑓), incorporates the diode forward voltage drop (VSD) The parameter t deadtime(r) specifies the dead time during the rising edge between the Low-Side (LS) switch turning off and the High-Side (HS) switch turning on Conversely, t deadtime(f) indicates the dead time during the rising edge when the HS switch turns off and the LS switch turns on, ensuring proper switching overlap and preventing device damage.
P QRR ,the LS body diode reverse-recovery loss, is induced during the phase of turning off of the LS body diode
𝑃 𝑄𝑅𝑅 = 𝑄 𝑅𝑅(𝐿𝑆) ∙ 𝑉 𝐵𝑈𝑆 ∙ 𝑓 𝑆𝑊 (2 13) where Q RR is the excess minority carrier charge in the reverse recovery transient
Figure 2 9 Diode reverse-recovery waveforms
In buck mode operation, the LS MOSFET is regarded as providing soft switching The turn-on and turn-off losses of the HS MOSFET, which include the effects of common source inductance from the device package, can be accurately calculated using a specific formula.
In this context, the parameters include OUT (output current), V_BUS (bus voltage), V_FET_DR (gate drive voltage), Rg (gate drive resistance), V_PL (HS MOSFET plateau voltage), L_Cis (HS MOSFET source inductance), Q_ds (HS MOSFET drain-source charge), and Q_gd (HS MOSFET gate-drain charge) These variables are essential for analyzing the performance of the circuit, with each playing a critical role in the operation and efficiency of the MOSFET switch Accurate measurement and understanding of these parameters enable optimized design and reliable functioning of power electronics systems.
The gate charge induced loss:
𝑃 𝑔𝑎𝑡𝑒 = (𝑄 𝑔(𝐻𝑆) + 𝑄 𝑔(𝐿𝑆) ) ∙ 𝑉 𝐹𝐸𝑇_𝐷𝑅 ∙ 𝑓 𝑆𝑊 (2 16) The switching frequency and V FET_DR should be optimally selected based on the minimum power loss
Figure 2 10 Power loss distribution of a synchronous buck in boost mode
When the inductor current flows reversely, the converter operates in either sink mode or boost mode, as illustrated in Figure 2.10 In these modes, the loss formulas are adjusted accordingly Additionally, high-speed power MOSFETs enable soft switching, enhancing overall efficiency. -**Sponsor**Sounds like you're looking to refine your article for SEO and clarity! It can be tough ensuring each paragraph is coherent and impactful Did you know [Article Generation](https://pollinations.ai/redirect-nexad/f2ByPTsU?user_id=983577) can instantly create 2,000-word, SEO-optimized articles? Imagine saving over $2,500 a month compared to hiring a writer, while still getting high-quality content Focus on high-impact results, and let Article Generation handle the content burden.
LS power MOSFETs are consequently hard switching in the boost mode The simplified turn ON/OFF losses are:
Driver Interface
The t watch-dog is triggered when the HS gate signal remains low while the switch node stays high; after a specified time interval, the LS MOSFET turns on to ensure system protection A detailed analysis of the system impact caused by the t watch-dog mechanism is provided in Chapter V.
Figure 2 11 Driver IC block diagram with proposed dead-time management
Dead-time must be sufficient enough to guarantee no cross conduction between high & low side MOSFETs However, a longer dead-time will bring in more switching power loss to a
Effective dead-time management is crucial in MOSFET drivers to ensure VR efficiency and reliability, as it prevents the body diode from conducting during dead-time, even when the low-side MOSFET channel remains off While shorter dead-times can improve performance, they also increase the risk of cross-conduction, making precise control essential Proper dead-time optimization minimizes conduction losses and enhances overall power conversion stability.
The discrete driver dead-time design should consider MOSFET parameter variation (R G ,
An adaptive dead-time scheme should be tailored to the specific characteristics of MOSFETs, such as CISS and VGS(TH) This approach involves measuring the actual gate voltage and enabling the transition only when the gate voltage drops below a suitable threshold, typically around 1V, which is effective for approximately 90% of MOSFETs Implementing adaptive dead-time control enhances switching performance and reduces losses, making it a valuable feature in general MOSFET drivers.
Adaptive dead time enhances circuit performance by replacing traditional fixed dead time, which is often around 12ns from leading suppliers, with dynamic control Reducing dead time impacts system efficiency positively, as discussed in section 2.12, by minimizing dead-time and Q RR losses Incorporating LS Schottky barrier diodes, such as Infineon BSC014NE2LSI with a forward voltage of 0.56V, further improves efficiency A calculation shows that adding just 5ns of extra dead time results in a minimal 0.2% efficiency penalty, making adaptive dead time control a valuable optimization in discrete MOSFET driver circuitry.
Integrated power stages featuring MOSFETs and drivers are increasingly adopted in high-density applications like blade servers Using fixed driver dead-time simplifies control logic and enhances power conversion efficiency, as parasitic MOSFET parameters within the power stage are predictable with minimal variation However, fixed dead-time can lead to shoot-through issues in multiphase VRs when phases remain in tri-state for extended periods before returning to normal operation, as both MOSFETs remain OFF during PWM tri-state signals, increasing the risk of cross-conduction.
PWM and DR_EN are control input signals generated by the PWM controller's state machine to manage the driver IC The timing diagram in Figure 2.12 illustrates the driver interface with HiZ management, which involves placing all MOSFETs in the off state to create a high-impedance (HiZ) stage The HiZ window is defined as the PWM voltage range between 1.2 V and 2.2 V for a 3.3 V system, ensuring safe operation Key timing parameters include propagation delays (t1 and t3 for LS and HS gates), dead times (t2 and t4 from LS and HS falling edges), hold-off times (t5 and t8), and propagation delays for DR_EN rising and falling edges (t6 and t7) These parameters are crucial for proper timing control and safe operation of the driver IC.
(a) (b) Figure 2 12 Timing diagram of driver interface: (a) DR_EN is asserted; (b) DR_EN is toggling during operation
Figure 2.13 illustrates the timing diagram of the embedded boot switch within the driver circuitry The boot switch is activated (ON) when the low-side (LS) switch is on, enabling the bootstrap capacitor to be charged Conversely, the boot switch turns off (OFF) when the high-side (HS) switch is on During PWM HiZ mode, the switch must remain OFF to prevent negative current flow, which could discharge the bootstrap capacitor if the switch were inadvertently turned on.
Figure 2 13 Timing diagram of driver interface: PWM vs Boot switch
To achieve optimal static efficiency across the entire load range, it is essential to select power MOSFETs with low figures of merit (FOM) and carefully analyze driver capabilities and power loss parameters for optimal performance Additionally, implementing phase shedding control is crucial for enhancing efficiency during mid-light loads, with control thresholds determined at the intersection points of adjacent phases in the efficiency curve.
Upper driver source/sink current 2A / 2A
Upper driver source/sink impedance
Lower driver source/sink current
Lower driver source/sink impedance t deadtime(f)
Properly defining and enhancing the driving capability of the power MOSFET driver is crucial to reduce switching losses during commutation, particularly in minimizing the overlapped conduction area As outlined in TABLE I, clear definitions of driving capability and dead times are essential for optimal performance Maintaining a low sink impedance is vital to prevent Cdv/dt-induced turn-on phenomena, such as shoot-through, in the low-side MOSFET during the rapid turn-on of the high-side MOSFET, thereby ensuring efficient and safe switching operation.
Figure 2 14 LS turning ON/OFF
Figure 2.14 illustrates the color-coded procedures for turning LS MOSFETs ON and OFF, highlighting that the switching speed is limited by parasitic RLC components within the circuit loop The red arrows in Figure 2.15 indicate the peak source and sink currents, with the sink current required to be higher to prevent shoot-through events Additionally, implementing a minimum OFF-time latch in the driver design is essential to ensure that all gate charge is fully discharged during turn-off, enhancing switching reliability and efficiency.
Figure 2 15 Simulation result of LS turning ON/OFF
Figure 2 16 An example of resonant gate-drive circuit
Figure 2.16 illustrates a resonant gate driver structure that enables energy recovery through resonance, offering potential efficiency benefits; however, it is not suitable for hard switching designs due to its timing constraints, which limit the ability to drive MOSFETs vigorously According to the loss analysis, gate drive losses constitute a small portion of total losses in typical applications, and implementing a resonant gate driver can lead to increased dynamic losses as switching transitions shift from being inductively limited to MOSFET limited To fully leverage resonance benefits, an entirely resonant buck topology is necessary, but this approach introduces larger phase currents that increase conduction losses, offsetting potential gains.
Light Load Operation
37 we treat the terms, diode emulation (DE), discontinuous conduction mode (DCM), pulse skipping, and pulse frequency modulation (PFM) the same
The voltage gain during PFM can be found:
⁄ , TON is the ON time of the control MOSFET L is the per phase inductance IOUT is the load current
Figure 2 17 Transfer ratio M vs duty cycle D
Assuming the switching frequency (f_SW) remains constant during power factor modulation (PFM), it is linearly proportional to the load current to ensure consistent output voltage regulation This relationship allows for improved light load efficiency, as the switching frequency can be decreased according to the load conditions, reducing switching losses and enhancing overall system performance.
From Figure 2 12, we can easily find
𝜏 = 𝐼 𝑂𝑈𝑇 𝐿𝑓 𝑆𝑊 (2 21) τ is the normalized inductor time constant
When the CPU is in an idle state, the load current is typically less than half of the inductor current ripple, causing the voltage regulator (VR) to operate in pulse-frequency modulation (PFM) mode to minimize power loss However, upon receiving a dynamic VID transition command, the VR must promptly switch from PFM to continuous conduction mode (CCM) to accommodate the load change It is important to note that in PFM mode, the VR cannot sink current, which prevents downward voltage regulation transitions in this operating state.
Figure 2 18 Operational waveforms of PFM operation
In PFM mode, as illustrated in Figure 2.18, PWM transitions from HiZ to high, causing the phase node to shift from the output voltage level to VBUS To enable rapid HiZ operation, as depicted in Figure 2.12(b), specific control strategies are employed to optimize transition speed and improve overall efficiency.
Utilizing EN toggle in PFM operation is essential for efficient power management, as the inductor current reaches zero and the LS switches off After turn-off, the output voltage gradually decays based on the load conditions During this process, power MOSFETs remain in high-impedance (HiZ) mode until the output voltage drops below the regulation target, triggering a PWM pulse to re-engage the system When LS turn-off is managed through PWM in a tri-state (slow HiZ operation), the hold-off time introduces a delay that can result in negative inductor current, impacting overall circuit performance.
Figure 2 19 Power loss distribution of a synchronous buck in PFM
PFM significantly reduces losses beyond just lowering switching frequency, including eliminating turn-on losses in HS thanks to Zero Voltage Switching (ZCS) Additionally, LS body diode reverse recovery loss is eliminated because there is no current freewheeling during the HiZ period, leading to improved efficiency and reduced thermal stress.
Similarly, there is no HS rising dead-time loss if accurate zero current detection scheme can be implemented The power loss in PFM is summarized in Figure 2 19
Figure 2 20 PFM to CCM transition (load: 1 A)
Figure 20 illustrates the mode transition from PFM to CCM, initiated by a change in the power stage The PWM ON-time pulse is triggered when VOUT falls below the setpoint, with TON calculated based on converter parameters and the VOUT ripple requirement TOFF is estimated at the zero current crossing point, ensuring accurate timing Additionally, THiZ depends on the load condition, influencing the overall switching behavior and efficiency of the converter.
41 voltage ripple in PFM is expected due to the excessive charge of inductor ripple current (minus load) built upon the output capacitor compare to CCM operation.
Switching Waveforms
To ensure the reliability of MOSFETs, it is crucial to prevent stress by accurately analyzing waveform measurements taken at the package pins, as opposed to directly on the silicon die Studying the difference (delta) between these measurements is essential for identifying potential issues and optimizing overall VR (Voltage Regulator) design A thorough understanding of these waveforms enables engineers to improve performance, enhance durability, and achieve a more efficient and robust system.
Figure 2 21 LS V DS rising waveform due to diode reverse recovery
Since the C OSS can be looked up from the curve in the datasheet, therefore, L para can be calculated by using (2.22)
Figure 2 22 Discrete solution of the converter considering circuitry parasitics in the buck mode
Figure 2 23 Simetrix simulation of Gate waveforms
Figure 2.23 presents a Simetrix simulation comparing gate drive waveforms, highlighting a significant difference between the actual waveform on the silicon die and the measured waveform on the package The green curve indicates a shoot-through concern related to LS bump back; however, this measurement is misleading because it includes parasitic effects In contrast, the blue curve shows the true waveform on the silicon die, which remains very low, with its peak lower than the V_GS(th) of the LS MOSFET, confirming minimal actual switching activity.
Figure 2 24 HS V DS waveforms comparison
Figure 2.24 illustrates the HS VDS waveform measured at both the power pin (source) on the package and directly at the silicon die, as indicated by the arrows The waveform details are clearly captured through fast acquisition, providing valuable insights into switching behavior and thermal performance of the device.
Measured at the silicon die
Measured at the package pin
The true VDS in a 44 scope shot is approximately 4V higher than the typical package measurement This voltage difference is primarily caused by the combined effects of rapid di/dt changes and source clip inductance Understanding this discrepancy is crucial for accurate voltage assessment and optimizing circuit performance.
Efficiency Optimization
Optimizing the static efficiency of the power stage is essential, as it is a key performance metric in VR design Load adaptive control (LAC) has been proposed and experimentally validated to enhance efficiency The multiphase VR operation mode and the number of phases dynamically depend on the load current, ensuring optimal performance across varying conditions Adaptive adjustment of FET drive voltage is crucial for achieving peak efficiency Selecting the optimal switching frequency (f_SW) with nonlinear control loop integration ensures low switching frequencies do not compromise load transient response, thereby maintaining system stability and performance.
Figure 2 25 Light load CCM vs PFM
Figure 2.25 highlights the efficiency comparison at light load, demonstrating that PFM operation significantly outperforms CCM operation, as anticipated The efficiency curves gradually converge around a load level that corresponds to approximately half of the inductor current ripple, emphasizing the superior performance of PFM mode during low load conditions.
Figure 2 26 Power loss reduction (PFM minus CCM) vs VID
Figure 2.26 illustrates the power-saving performance as VOUT increases under a 10mA load current The plot demonstrates that, as VOUT rises, enabling the voltage regulator (VR) to operate in PFM mode becomes increasingly critical when the load current is low, optimizing power efficiency.
Converter parameters are detailed in TABLE I, with the exception of the disabled LL The output voltage (VOUT) is regulated at 1.05 V and measured at the output inductor for accurate performance assessment An automated efficiency measurement program, developed using GPIB communication, interfaces with the data acquisition unit (Agilent 3497A) and electric load (Sorensen) to record critical parameters such as VIN, IIN, VOUT, IOUT, VFET_DR, and IFET_DR, enabling precise efficiency curve plotting.
Figure 2 27 Efficiency vs switching frequency
Switching frequency, f SW, is the key parameter that needs to be optimized for achieving optimum efficiency Figure 2 27 shows the efficiency comparison between different f SW cases
Figure 2 28 Efficiency vs FET drive voltage
The driver voltage of power MOSFETs is also an important parameter to be optimized In the total power loss formula, it affects the Rdson of (2.6) and (2.14)
Figure 2 29 Measured efficiency of multiphase buck converter with operating different number of phases
Figure 2.29 illustrates the measured efficiency of a multiphase buck converter operating across various modes and phase configurations The test includes seven cases: single-phase PFM and multi-phase CCM from two to six phases The crossover points between adjacent phases' operation can be programmed into non-volatile memory (NVM) to enable auto phasing shedding This feature helps flatten the efficiency curve across the entire load range, enhancing overall power conversion performance.
MOSFET Drive Voltage Selection Power Inductor Selection
Setup Simulation/Experimental with Initial
Efficiency Optimization with Load Adaptive Control Reached
Figure 2 30 Power efficiency optimization flow chart
Output inductor per phase L = 230 nH
Output capacitor 6ì470 àF Panasonic SP-Caps EEFSX0D471XE
Figure 2 31 Diagram of Load adaptive control
Figure 2 31 shows the diagram of load adaptive control based on previous optimization results
CHAPTER THREE: LOW FREQUENCY TRANSIENT AND SYSTEM
This chapter introduces load transient enhancement schemes tailored for low-frequency transient operation, aiming to improve system stability and performance Adaptive body braking control is proposed to actively suppress load release transients, while dynamic phase addition and removal help minimize VOUT excursions Load adaptive control offers significant power-saving benefits but may create corner cases, such as shoot-through risks To address this, a novel dead-time management scheme combining fixed and adaptive dead-times is proposed to enhance system reliability and optimize power conversion efficiency during normal operation.
DCR Sense Network Impact
Figure 3 1 DCR sense network RC time constant
In voltage mode control with proper compensation as a baseline, Figure 3.1 demonstrates how the VOUT is influenced by the DCR sense network, with VOUT excursions color-coded as blue, green, and red The green curve shows the ideal RC time constant without nonlinear control, highlighting optimal response A larger RC time constant, shown by the blue curve, results in sluggish VOUT response due to AVP loop delay, risking CPU reliability issues from overshoot Conversely, a smaller RC time constant, depicted by the red curve, causes VOUT sag during load insertion and excessive undershoot, which can lead to system hangs in computing systems.
Nonlinear Control Scheme
Load Engage Enhancement
Nonlinear control schemes are essential for slow transient applications, particularly those operating below 50 kHz In virtual reality (VR) systems, during load engagement transients, nonlinear control effectively manages PWM pulse adjustments by pulling-in or asserting pulses faster than the linear loop’s response This advanced control method helps reduce voltage excursions and extends the life of output capacitors, ensuring more reliable and efficient power management in VR applications.
Figure 3.3 illustrates the load engagement response, where a load current step of 131A is applied with an associated slew rate of 524A/µs The diagram depicts six digital channels, representing six PWM signals, with the lighter blue line indicating the load current and the darker blue line showing the voltage output, highlighting the system's dynamic performance during load transitions.
Figure 3 3 Load engage response with pure voltage mode control
The voltage mode response, with an 80 kHz control bandwidth, cannot respond quickly enough to compensate for the 60 mV undershoot, as it fires phases based on internal clock cycles rather than faster phase adjustments The initial sharp voltage dip is caused by the ESR and ESL of the output capacitors Since the inductor current slew rate is much lower than that of the load current, physical charge balance limits prevent complete elimination of the undershoot when the load engages However, implementing a nonlinear control scheme could help improve the undershoot response.
Figure 3 4 Load engage response w/ auto-phasing
Figure 3.4 illustrates the load engagement response of the multiphase buck converter with ALER enabled, demonstrating the converter's dynamic stability under typical operating conditions The test utilizes consistent step and slew rate parameters of 131A and 524A/µs, respectively, to ensure accurate performance assessment Six digital channels represent the PWM signals controlling each phase, with cyan blue indicating the load current and darker blue illustrating the output voltage Initially, the converter operates in a two-phase mode before the load is applied, providing a baseline for observing the system's response during load engagement.
Load Release Enhancement
Existing methods to manage overshoot voltage include increasing the VR's output capacitance to suppress voltage spikes and utilizing the power MOSFET's body diode for “body braking” to dissipate excess current However, these approaches have drawbacks: larger capacitors raise cost and size, while relying on “body braking” can lead to reliability concerns and inefficiencies.
57 generates additional power loss and excess heat Therefore, we propose a method to pulse the LS gate ON and OFF to achieve the compromised result
The equation set in (3.4) encompasses all operational scenarios and inductor current slopes within the converter Equation (a) describes the charging slope during boost (sink) mode when the body diode of the high-side switch (HS) conducts Equation (b) pertains to the charging slope in buck mode operation Equation (c) outlines the discharging (freewheeling) slope when the low-side switch (LS) operates asynchronously and the body diode conducts, causing body braking Finally, equation (d) illustrates the discharging slope when the low-side switch (LS) is turned on.
Figure 3 5 Inductor current profile and gate-drive signals for the corresponding operations
Figure 3.5 illustrates all possible inductor current slopes in buck/boost mode, derived from equation (1), along with the corresponding gate-drive signals for both synchronous and asynchronous operations The intervals T1 and T2 represent the conduction states of the high-side (HS) body diode and HS channel, respectively Additionally, intervals T3 and T4 correspond to asynchronous and synchronous rectifier control modes, respectively, highlighting the switching behavior and control mechanisms within the power converter.
Figure 3 6 Load release response comparison
Figure 3.6 illustrates the impact of suppressing load release, comparing LS MOSFET ON, LS MOSFET OFF, and LS MOSFET Pulse control, with waveforms in light blue, black, and magenta The results show overshoot values of 58 mV when the body diode is ON and 68 mV when both the LS MOSFET and body diode are ON, highlighting the effectiveness of each control method in managing voltage overshoot.
Figure 3 7 Inductor current slew rate difference during load release
Figure 3 7 shows the resultant inductor current profiles during load release
Using the LS pulse control during load release results in a temperature that is 7 degrees lower compared to turning off the LS to freewheel the load current Figure 3.8 illustrates the differences in inductor current slopes when the body diode is ON, when pulsing the LS, and when the LS is fully ON This demonstrates the effectiveness of pulse control in managing thermal performance and current behavior in power systems.
When a transient load like a CPU operates across a wide voltage range, the worst-case overshoot typically occurs at the lowest VID level Conventional body braking methods involve turning off the LS FET for either an entire cycle or a specific period, focusing solely on the lowest VID, but this approach can be too aggressive at higher VID levels As a result, unnecessary power dissipation occurs in the body diode, potentially leading to thermal management challenges and efficiency losses.
Figure 3 8 Adaptive body-braking control (pulsing control)
Turn LS MOSFET ON/OFF Based on the Identified Pre-defined Switching Pattern
Figure 3 9 Flow chart of adaptive body-braking control (pulse control)
The flow chart of adaptive body-braking control in pulse control mode is shown in Figure
Figure 3 10 Adaptive body-braking control (Body diode ON)
In Figure 3.10, the body braking control duration features a pulse pattern that toggles the LS gate, with the OFF time duration dynamically adapting based on the current VID This adaptive adjustment is primarily focused on mitigating worst-case overshoot scenarios at the lowest VID Figure 3.11 presents the corresponding flow chart, illustrating the control process for optimized braking performance.
Turn OFF HS MOSFET Turn ON LS MOSFET
Adaptive Turn OFF LS MOSFET
Re-enter Steady State Operation
Output Voltage Exceed Identified Pre-determined Threshold
Figure 3 11 Flow chart of adaptive body-braking control (Body diode ON)
Drop Phase Optimization
The phase number of a multiphase converter depends on the load current and must adapt dynamically to load variations to ensure optimal static operation Proper management is essential when shutting off a phase, requiring a gradual ramp-down of the inductor current to prevent adverse effects during the droop operation.
Figure 3 12 Overshoot during phase shedding
Figure 3.12 illustrates the phase shedding process during load release, with the yellow channel representing VOUT and the blue channel depicting load current The load current step is 30A, with a slew rate of 10A/µs The scope captures three overshoots, circled in red; the first is normal and caused by the load step, while the subsequent overshoots result from dropping phases 2 and 3, where the remaining inductor current causes the overshoot when these phases turn off.
65 increased when the phase is off state because the current is freewheeling through the LS body diode
When the phase dropping command is initiated, the module's state machine adjusts the modulated ON time produced by the PID controller and ramps down the inductor current in the phase being turned off Simultaneously, it increases the current in the remaining phase to maintain the total load current, effectively eliminating overshoot caused by phase dropping and ensuring stable power delivery.
Figure 3 13 Current balance block diagram
The simulation shows the inductor current is ramping down 5 consecutive switching cycles before the controller issue a drop commend
Figure 3 14 Simulated inductor current with smooth gain.
PWM HiZ to High Transition in Shedded Phase
During power state transitions or load transients, the shedded phase must become active instantly to conduct current, which can cause the PWM signal to switch from a high-impedance (HiZ) state to a high level This rapid transition is crucial for maintaining system stability and proper current flow Understanding this behavior is essential for designing effective power management and PWM control systems, especially in scenarios requiring swift response to transient conditions.
The simulation results in Figure 3.15 illustrate the VR existing tri-state, where the PWM signal transitions directly from HiZ to high The bootstrap capacitor voltage remains around 3V because of gate drive leakage, causing Vboot_SW to decay linearly due to artificially introduced leakage current, as described by equation (1) A shoot-through event lasting approximately 13 ns is observed in Figure 3.16 (a), while no shoot-through occurs in Figure 3.16 (b) due to different dead-time schemes, demonstrating the impact of dead-time control on switching losses.
In d u ct o r cu rr en t (A )
Figure 3 15 Simulation results of VR entering tri-state
(b) Figure 3 16 Simulation waveforms of existing long tri-state: (a) fixed dead-time: around 13 ns of shoot- through (b) adaptive dead-time: No shoot-through captured.
When VBOOT-SW is above 3.8 V, the system operates normally under typical conditions However, lowering PVCC and increasing VOUT to around 1.8 V can cause the driver to create a GH/GL overlap or shoot-through scenario if the dead-time design is too aggressive Additionally, if the phase remains in tri-state for an extended period, the boot capacitor discharges due to gate driver leakage current (approximately 1 nA/sec), which ultimately clamps VBOOT-SW according to the specified equation.
𝑉 𝐵𝑂𝑂𝑇−𝑆𝑊 = 𝑃𝑉𝐶𝐶 − 𝑉 𝑆𝐷 − 𝑉 𝑂𝑈𝑇 (3 5) Where PVCC is the power MOSFET drive voltage VSD is the diode voltage drop for the internal switch
The level shift circuit, as illustrated in Figure 2.11, converts GND-referenced signals to the HDRV “isolated” circuitry, producing a level-shifted output that is referenced to SW.
The 69-node circuit is powered from the BOOT-SW capacitor voltage, influencing the overall timing behavior The HS gate falling edge propagation delay increases relative to the LS rising edge delay, primarily due to BOOT-SW bleed phenomena This bleed is affected by variables such as VOUT, the duration of tri-state conditions, and other factors, making the delay susceptible to operational conditions Additionally, the HS falling preparation delay increases independently of PVCC voltage, potentially causing a GH/GL overlap until the BOOT capacitor recharges from the second LS pulse, impacting switching performance and timing accuracy.
Figure 3.17(a) highlights a 10 ns overlap in gates when using long PWM tri-state signals To eliminate this overlap, Figure 3.17(b) suggests that the controller-driven PWM should go LOW first to charge the BOOT capacitor, reducing propagation delay and preventing shoot-through Alternatively, Figure 3.17(c) shows that an anti-shoot protection unit can monitor HG and LG signals to adaptively prevent gate overlap in real-time.
The avalanche breakdown energy of the power stage devices is simulated to be approximately 50 mJ using Cadence Virtuoso Analog Design Environment, representing the worst-case scenario During the gate overlap event, the energy is significantly lower, remaining under 100 attojoules (aJ), which is only 1/500th of the energy required for device breakdown Despite the low energy during gate overlap, it is essential to prohibit overlapping gate signals to enhance overall system robustness and prevent potential device failure.
Figure 3 illustrates the operational waveforms of the existing long tri-state The waveform in (a) shows approximately 10 ns of shoot-through, indicating a brief conduction during switching In contrast, waveform (b) demonstrates that no shoot-through occurs when the PWM goes low first upon exiting the tri-state condition, ensuring safer operation Additionally, waveform (c) confirms that with the implementation of “adaptive” shoot-through protection, no shoot-through is captured, highlighting the effectiveness of the protective mechanism in preventing conduction faults.
This innovative method effectively eliminates the shoot-through issue while ensuring efficient VR operation during steady-state mode It strategically combines the benefits of fixed dead-time and adaptive dead-time control techniques to optimize performance By integrating these approaches, the proposed solution enhances system reliability and power efficiency, making it a robust choice for advanced voltage regulation applications.
The proposed dead-time management system incorporates both fixed and adaptive dead-time circuits to optimize power converter performance Implementing shorter dead-times in steady-state mode enhances overall power conversion efficiency Additionally, the adaptive dead-time can be selectively activated when needed to maintain the robustness and reliable operation of the power converter under varying conditions.
Adaptive dead-time control dynamically adjusts to manufacturing variations in Qg and RG of discrete MOSFETs by monitoring driver outputs, including HDR and LDR signals This approach ensures optimal switching performance, improves efficiency, and enhances reliability in power electronic systems By tailoring dead-time compensation based on real-time feedback, the system minimizes switching losses and prevents cross-conduction, leading to more robust and efficient operation under varying conditions.
When the 72 transition reaches a high level, the LS gate voltage begins to decrease after a propagation delay Simultaneously, the LDR voltage is monitored, and the high-side driving voltage starts to rise once the LDR voltage drops below the threshold of 1V.
The fixed dead-time is monitored before the level shift circuitry, ensuring precise control of gate signals By understanding and managing MOSFET parameter variations, a shorter, more aggressive delay can be applied This approach allows for reliable and consistent fixed dead-time implementation, optimizing switching performance and enhancing overall efficiency.
Efficiency improvements can be estimated using the buck loss model, where reducing both LS rising and falling dead-times by 5 ns results in approximately a 0.30% gain in efficiency In typical applications involving 20 phases of multiphase VR, this reduction can save up to 1.23 W—0.66 W from 12 Vcore phases and 0.57 W from 8 MEM VRs—by shrinking dead-time by 5 ns with standard MOSFETs.
Deadtime, denoted as t_deadtime(f) and t_deadtime(r), refers to the interval between switching events in power electronics Specifically, t_deadtime(r) is the rising edge dead-time between the downswing of the Low-Side (LS) switch and the upswing of the High-Side (HS) switch, while t_deadtime(f) is the rising edge dead-time between the downswing of the HS switch and the upswing of the LS switch The parameter Nphase represents the number of active phases in the system, influencing overall performance and efficiency Proper management of deadtime is essential to prevent cross-conduction and ensure reliable operation of multi-phase power converters.
Driver POR and enabled after 100 às
Monitor input PWM logic level
In tri-state for more than 100 às
Switch dead-time management to adaptive dead-time
Voltage on boot capacitor reaches to Vcc
Switch dead-time management to fixed dead-time
Figure 3 18 Dead-time management diagram when VR exist tri-state
Figure 3 18 shows the proposed dead-time management scheme that can enhance the system reliability and also maintain high power conversion efficiency
CHAPTER FOUR: HIGH FREQUENCY TRANSIENT
Sampling Effects of PWM Converters
In voltage mode control, VCOMP serves as the error amplifier output that compares with the saw-tooth carrier signal to generate pulse-width modulation (PWM) As depicted in Figure 4.1 (a), VCOMP is essential for accurate voltage regulation The trailing-edge modulation approach, shown in Figure 4.1 (b), involves introducing a perturbed VCOMP to produce the PWM signal through comparison with the saw-tooth carrier, ensuring precise control of the power converter.
Figure 4 1 PWM modulator diagram and V COMP perturbation waveform: (a) PWM Modulator; (b) modulation waveform with V COMP perturbations
Pulse width modulation (PWM) is a sampling hold system and it samples periodically at the switching frequency where VCOMP and ΔOSC encounters
The transfer function of zero-order hold is:
(b) Figure 4 2 Frequency response of zero-order hold: (a) Gain; (b) Phase
The transfer function of sample data system can be found as:
Figure 4 2 shows the frequency response of PWM sample data system The sampling frequency is 400 kHz as the simulation indicates
Output Impedance Optimization
Figure 4 3 Small-signal control block diagram of the closed loop output impedance
G id is the transfer function of open loop duty cycle to inductor current
Z O is the open loop output impedance
G ii is the transfer function of open loop output current to inductor current
G AVP is the AVP LPF transfer function
G COM is the total compensator gain
As illustrated in Figure 4 3, two transfer functions representing the loop gains, Ti(s) and Tv(s) are defined as:
By adopting Mason’s gain formula, the overall output impedance of voltage mode control with AVP loop can be mathematically expressed as:
The output impedance and the compensation gain in high frequency region should be low enough to attenuate high frequency noise
Figure 4 4 Plots of |Z v | and |Z OC |
Beat Frequency Mitigation
As the repetitive load frequency approaches the switching frequency, the control loop struggles to respond quickly to load transients, leading to increased dynamic currents between phases that sink and source, which in turn raises dynamic losses due to circulating energy Additionally, the extra phase imbalance current can impose additional stress on power devices, underscoring the need for effective design mitigation strategies to ensure system stability and reliability.
The voltage loop bandwidth (BW) is optimized to 75 kHz, which is one-fifth of the switching frequency (fSW), ensuring system stability within this range Maintaining the feedback loop within this bandwidth allows the system to remain stable, but beyond this frequency, the compensator's response to high-frequency transients diminishes due to reduced loop gain Additionally, operating beyond the bandwidth increases the risk of aliasing problems Therefore, it is recommended to minimize the compensator's influence outside the bandwidth and rely on the output capacitor (COUT) to handle high-frequency transient responses, enhancing overall system performance.
During low-frequency load current transients, the control loop is optimized to suppress load current variations, ensuring the output impedance is regulated by the system’s closed-loop response For high-frequency, large load current changes, the closed-loop system is fine-tuned to reduce output impedance peaking, thereby maintaining stability and performance.
Figure 4 5 Block diagram of load frequency detection (LFD)
Figure 4.5 presents a simplified block diagram of the Load Fault Detection (LFD) scheme during high-frequency repetitive load transients The programmable threshold must exceed the ripple voltage to effectively detect load events Changes in the polarity rate of the voltage error signal indicate load engagement and release events When the load frequency exceeds the predefined high-frequency range, the enable signal (EN) of the nonlinear transient loop is de-asserted to protect the system Real-time phase current monitoring is performed via ADCs, while a peak current limiter provides double-layer protection by truncating PWM pulses once the current surpasses the set threshold, preventing inductor saturation and enhancing system reliability.
To enhance the reliability of the VR system, it is essential to bound the instantaneous phase current A two-layer current protection mechanism within the control loop is proposed to effectively mitigate the beat frequency issue, ensuring more stable and dependable operation.
Dynamic Current Sharing
Figure 4.6 (a) illustrates the total AC window for both overshoot and undershoot excursions during low-frequency transients, marked by two cursors Excessive undershoot caused by beat frequency oscillation is undesirable and can lead to system instability, such as blue screen errors in computing systems Disabling the nonlinear loop effectively eliminates the beat frequency oscillation, resulting in improved regulation As shown in Figure 4.6 (b), the output voltage (VOUT) remains well within the AC window, ensuring stable system performance.
Figure 4 6 A load transient response Load step: 10A-141A, slew rate: 450 A/àS Rep rate: 400 kHz (a) Nonlinear loop enabled (b) Nonlinear loop disabled
Frequency domain analysis using Matlab is carried out and the effectiveness of the proposed scheme is verified
The load repeater rate operates at approximately 400 kHz, generated by Intel VRTT, ensuring high-speed data transfer The VOUT data, as shown in Figure 6, are exported in DAT files from the oscilloscope for detailed analysis The spectral characteristics of VOUT provide valuable insights, with notable low-frequency peaking around 9 kHz observed in Figure 4, indicating specific interference or signal behavior.
Disabling the nonlinear loop, as illustrated in Figure 4.7(b), effectively removes the low-frequency oscillations, leaving only the high-magnitude spectrum that corresponds to the load frequency This highlights how turning off the nonlinear loop improves the clarity of the load frequency signal by eliminating unwanted low-frequency oscillations.
(b) Figure 4 7 Magnitude of an N-point DFT on V OUT (high frequency rep rate transient) (a) Nonlinear loop enabled (b) Nonlinear loop disabled
(b) Figure 4 8 Phase currents oscillation: transient step: 132A-165A, load frequency 385 kHz (a) LFD disabled (b) LFD enabled
Figure 4.8 illustrates the enhanced phase current waveforms achieved through the proposed schemes, with magenta, cyan-blue, and blue channels representing the three-phase currents at a load frequency of 385 kHz, near the switching frequency Specifically, Figure 4.8 (a) depicts the circulating phase currents among the phases, highlighting maximum sourcing and sinking currents of 62A and -24A, respectively These phase currents were precisely measured using a proprietary fixture connected via BNC cables, ensuring accurate data collection.
CHAPTER FIVE: DYNAMIC VOLTAGE SCALING
Dynamic voltage scaling is an essential energy-saving feature in modern processors, enabling efficient power management A multiphase VR (Voltage Regulator) design is crucial to allow CPUs to seamlessly transition to updated voltage levels within specified ranges This design minimizes power conversion losses, improving overall energy efficiency and performance in contemporary computing systems.
Figure 5 1 The impact of DVS operation at datacenter level
Figure 5 1 [46] shows the impact of DVS operation at datacenter level and shows the significance of this operations.
Modes of Operation
In Power Flow Management (PFM), as illustrated in Figure 5.2(b), Pulse Width Modulation (PWM) transitions from high impedance (HiZ) to a high state, enabling efficient power control During this process, the phase node shifts from the output voltage level to VBUS, facilitating seamless power transfer Achieving rapid HiZ operation, as depicted in the figure, is crucial for enhancing system response and stability in power management applications.
In PFM operation, the EN toggle (2b) should be used to control the mode When the inductor current approaches zero, the LS turns OFF, causing the output voltage to gradually decay based on the load During this period, the Power MOSFETs remain in a high-impedance (HiZ) state until the output voltage drops below the regulation target, which then triggers a PWM on pulse to restore voltage regulation.
Figure 5 2 Operational waveforms with the critical dead times: (a) Buck (Source) CCM; (b) Buck (Source) PFM; (c) Boost (Sink) Mode
Under the boost mode, as shown in Figure 5 2 (c), the phase node voltage is clamped to
When VBUS is active, the diode forward voltage drop occurs after the HS MOSFET turns off, with the red rectangle indicating the watchdog timing Following the watchdog interval, the LS MOSFET undergoes hard switching, initiating after this delay Once the LS MOSFET switches on, the current previously flowing through the HS body diode commutes to the LS MOSFET, passing through a reverse recovery phase, which can impact overall efficiency and switching performance.
During mode transition, the inductor current in one phase and the corresponding LS VDS waveform are observed, with the VDS initially starting negative due to the body diode voltage drop during t dead-time The sharp edges in the first VDS pulse result from the rapid charging and discharging of COSS After the dead-time, the LS turns on, causing the VDS voltage to be determined by RDS(on) multiplied by the inductor current The middle VDS pulse exhibits a falling edge when the inductor current reaches zero, with COSS discharging gradually In the final pulse, VDS is clamped to VIN plus the diode forward drop VSD during both the dead-time and watchdog periods, reflecting the switching behavior during mode transition.
Figure 5 3 Operational waveforms during mode transition
During the buck mode operation at t1, the Low-Side switch (LS) achieves Zero Voltage Switching (ZVS) turning on, ensuring efficient switching At the transition point t2, the inductor current flows through the High-Side body diode, allowing the High-Side switch (HS) to turn on with ZVS, reducing switching losses When the inductor current reaches zero at t3, the High-Side switch (HS) turns off with Zero-Current Switching (ZCS), while the Low-Side switch (LS) turns on with ZCS, optimizing overall power efficiency and minimizing switching stress.
Driver Dead-time in Sink Mode
During the voltage transition from 1.2 V to 0.7 V, the setup experienced a significant reduction in response time, decreasing from 280 ns to 80 ns Figure 5.4 illustrates the impact of the driver watchdog across two consecutive switching cycles during DVID down, highlighting its influence on performance stability The discharging slope remains consistent at 5.1 across these cycles, with key time points labeled as t2, t1, and t3, ensuring reliable and predictable circuit behavior during voltage downscaling.
The parameter 2𝐿 ∆𝑡 (equation 5.1) represents the modulated OFF time or LS ON time between two switching cycles, where ∆t plays a critical role in circuit regulation When the t watchdog (indicated by the red bar) is narrower, it causes the inductor current to increase more rapidly, effectively turning on LS2 sooner This leads to more precise regulation of VOUT, allowing it to be easily adjusted and slewed down in relation to the internal reference DAC, thereby enhancing overall power supply stability and performance.
Figure 5 4 System dynamic comparison of different driver t watch-dog
(b) Figure 5 5 Experimental waveforms with different design of t watch-dog : (a) Boost (Sink) mode: t watch-dog = 60 ns; (b) Boost (Sink) mode: t watch- dog = 120 ns
The voltage mode controller intentionally skips the PWM high pulse when the sensed output significantly exceeds the reference DAC during DVID downward operation Prolonged watchdog duration can cause asymmetric conduction of the LS MOSFET in one phase, leading to unbalanced negative inductor currents across phases This asymmetry impacts overall system stability and efficiency, highlighting the importance of proper control timing and phase balance in power supply designs.
VR long term reliability would degrade
Figure 5.5 illustrates key scenarios: at a watch-dog time of 60 ns, the converter operates in boost mode with negative output inductor current, and the driver actively sinks current by "hard" turning on the LS MOSFET When the watch-dog reaches 120 ns, during DVID operation, the output inductor current reaches zero, distributing energy back into input capacitors as the COSS of the LS MOSFET discharges and the driver waits for the phase node to go low before turning on the MOSFET The additional 60 ns delay introduced by the watch-dog hampers regulation, making downward regulation via DVID challenging.
Control MOSFET Stress Suppression
(b) Figure 5 6 (a) Discrete solution of the converter considering circuitry parasitics in the boost mode; (b) HS MOSFET enters avalanche due to high di/dt and parasitic inductance
The schematics of the discrete type of solution with circuitry parasitics are shown in Fig
9 (a) when the converter is in the boost mode The HS V DS can be mathematically expressed as:
The voltage V_DS is determined by the sum of bus voltage (BUS) and the stray inductance voltage (L_STRAY * I_D), where L_STRAY includes the loop parasitic inductance from PCB, drain, and source During switching, the diode reverse recovery current (I_D) can cause voltage spikes that approach the MOSFET's breakdown voltage, resulting in high current transients that may damage the device Additionally, when the body diode of a high-side (HS) MOSFET conducts during the watchdog time slot, its PN junction accumulates minority carriers, which can impact switching behavior and system reliability.
Figure 5 7 Equavelent circuitry with snubber when MOSFET is in off state
Figure 5 7 shows the equivalent circuitry with snubber circuit when MOSFET is in off state CGFP is formed by gate electrode, interelectrode and field electrode Rfp is the field-
94 electrode resistance between source terminal and field electrode Fine tune the snubber resister,
Rfp, is very critical in the MOSFET design to surpress the VDS ringing
Figure 5 8 Simulation result of HS V DS waveforms with different snuber resister R fp
Figure 5.8 illustrates the Simetrix simulation results demonstrating the damping effect of HS V_DS waveforms by varying RFP resistance The results highlight that the snubber resistor must be appropriately sized; a resistance that is too high, as shown by the blue curve, can cause shoot-through conditions, reducing system reliability and efficiency Conversely, a resistor that is too low may lead to avalanche phenomena, compromising system stability Based on the simulation, an optimal resistance value of approximately 3 Ohms is recommended for the snubber circuitry to balance performance and safety.
Figure 5.9 illustrates the HS VDS during fast DVID tests conducted at 20 mV/µs and 40 mV/µs in fast acquisition mode The screen captures depict the VDS waveform, highlighting the maximum amplitude observed under these high-speed conditions.
5 9(b) is 20.6 V which is reduced by 4.4 V compared with the result in Figure 5 9(a) or [41] because HS with smaller QRR are implemented and also damped by intrinsic internal snubber structure in MOSFET
Figure 5 9 High side V DS during repetitive DVID operation: (a) Q RR = 20 nC and without snubber circuitry; (b) Q RR = 10 nC with snubber circuitry Channel 2: HS drain-source voltage, 5V/div
During the DVID downward transition, the inductor current flows in reverse as the energy stored in the capacitor banks is discharged back to the input side When HS turns off, the body diode of HS conducts, resulting in a voltage spike on V_DS that can cause impact ionization and avalanche breakdown of the MOSFET To mitigate this excessive ringing on V_DS, simulation and experimental studies have identified three effective methods to reduce these voltage oscillations, ensuring improved device reliability and circuit stability.
Embed and fine tune the internal snubber structure;
Embed one more layer of Schottky barrier diode in the HS MOSFET design, which essentially reduces Q RR ;
Use integrated power stage, such as stacked-die package, which reduces the parasitic inductance
DVS Responsiveness Optimization
Nonlinear Control Scheme
Figure 5 10 The timing architecture of the multiphase controller
Figure 5.10 illustrates the timing architecture of the multiphase VR, which effectively manages low-frequency load transients and enhances voltage stability during DVID operation This architecture is particularly beneficial during DVID downward transitions, helping to smooth the voltage output and maintain reliable power delivery.
CdV/dt Compensation
AVP is an advantageous technique for managing load transient events, but its loop design in DVID systems requires careful consideration While the AVP loop uses the total inductor current to represent load conditions, phase currents (CdV/dt) during VID changes can charge or discharge output capacitors without altering load current, impacting regulation accuracy The additional inductor current within the closed loop can influence VOUT regulation as described in equation (4) Moreover, the AVP loop introduces lag, delaying VOUT settling during upward VID transitions, which can pose issues for alert timing on the sVID bus in applications demanding precise timing, such as processors.
Figure 5 11 Architecture of DVID module with compensations
Figure 5.11 illustrates the architecture of DVID compensation, highlighting its role in managing both current and voltage aspects Effective compensation is crucial for mitigating droop current and ensuring proper charging of output capacitors during dynamic operation This enables precise timing of DVID upward transitions, enhancing overall system stability and performance.
The transition process is crucial in ensuring smooth voltage adjustments, with careful control of the Alert line to signal processor readiness Digital current compensation effectively removes the AVP effect by subtracting the sensed total current's absolute value during DVID, stabilizing the current loop Voltage compensation involves adding a programmable offset to reshape the ramp DAC, which accelerates the transition and enhances smoothness during both initial and final phases During an upward DVID transition, the output voltage measurement includes the capacitor voltage and ESR voltage caused by Cdv/dt current, necessitating an offset to counteract ESR voltage sag at the end of the transition for improved accuracy and performance.
Figure 5 12 Matlab simulation result of DVID transition with and without droop compensation and nonlinear control: (a) DVID upward transition; (b) DVID downward transition
DVID transitions are simulated using Matlab and presented in Figure 5 12 The VOUT with CdV/dt compensation (red and black curves), in Figure 5 12 (a) was regulated tightly to the
Implementing body brake control significantly reduces overshoot during DVID upward transitions, as demonstrated by the black curve in the analysis The reshaped VTarget, enhanced with Cdv/dt compensation, introduces additional asynchronous pulses at the end of the transition This approach ensures that no undershoot occurs, improving overall transition accuracy and system stability.
Figure 5 illustrates experimental waveforms of fast DVID transitions, comparing cases with and without CdV/dt compensation The cyan traces represent signals with CdV/dt compensation, while the black traces show signals without compensation The scope shots display six digital channels corresponding to the six PWM signals of the voltage regulator (VR), highlighting the effects of compensation on waveform quality and switching performance.
Excessive undershoot of output voltage during DVID transitions must be prevented to avoid system hangs or blue screen errors in server systems Reshaping the ramp pattern, as indicated by the asynchronous pulses in the digital channels, introduces a voltage offset at the start of the DVID upward transition and at the end of the downward transition This technique accelerates the DVID upward transition and effectively eliminates voltage undershoot during downward transitions, ensuring stable and reliable system performance.
Figure 5 13 Experimental waveforms of fast DVID transitions with/without Cã dV/dt compensation: (a) Fast DVID upward transition; (b) Fast DVID downward transition
Given the total output capacitance CO, the relationship between the sinking/sourcing current and DVID slew rate can be expressed by:
Server processors roughly have about 4000 àF of CO in each VR At 20mV/às DVID rate:
80 Amps of source or sink current during DVID
Current Sharing during DVS
To effectively adjust the output voltage during sVID transactions, additional phase current is required to charge or discharge the output capacitors accordingly During voltage transitions, particularly during DVID downward operations, it is essential to evenly distribute the phase current among the active phases to ensure stable and efficient voltage regulation Proper management of phase current sharing enhances system reliability and performance in voltage adjustments.
Figure 5 14 Simulation result of total phase current (a) Source current at different VID transition (b) Sink current at different VID transition
Figure 5.14 illustrates the simulation results of total charge and discharge phase currents during three different VID transitions: 1.2V-0.7V (blue), 1.2V-0.9V (red), and 1.2V-1.1V (green) The VID delta indicates variations in sink/source energy, as shown by equation (5.3) During the sink (boost) mode, the inductor current reverses direction, requiring negative current sharing, as demonstrated in Figure 5.14(b) Proper optimization of the watchdog timer, a critical IC parameter, is essential—if set too high, the controller may activate the LS asymmetrically, preventing even phase current sharing, since the primary focus during this operation is to ramp down VOUT in a controlled manner.
Figure 5 15 Negative current calculation in DVID downward transition
The worst-case negative current in a single phase can be determined by measuring the time during the specific slope section, as illustrated There are three key inductor current slopes: HS ON slope 1, HS body diode ON slope 2, and LS ON slope 3 These negative current peaks occur at the end of the downward transition, with the output voltage assumed to be 0.7V, and the inductance considered constant regardless of load variations.
(b) Figure 5 16 Vout regulation comparison of different driver t watch-dog during DVID down
(a) Sink mode: t watch-dog 0 ns; (b) Sink mode: t watch-dog = 60 ns
To effectively perform a controlled DVID downward operation, it is essential to quickly discharge the energy stored in the output capacitor Rapid sinking of the phase current is crucial to regulate and reduce the voltage efficiently, ensuring a safe and stable power conversion process.