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Trang 1Physica E 32 (2006) 547–549
Self-aligned doping profiles in nanoscale silicon structures
Jouni Ahopelto , Mika Prunnila, Eeva Pursula VTT Information Technology, PO Box 1208, FIN-02044 VTT, Finland
Available online 10 February 2006
Abstract
We propose and demonstrate a method for self-aligning control of doping profiles in nanoscale silicon devices The method is based on different segregation behaviour of n-type and p-type dopants during thermal oxidation The simulations show that in nanowires with compensated impurity concentrations the type of conductivity can be changed from p-type to n-type We use the method to realize a lateral field effect device in silicon showing pn-diode-like characteristics at 300 K
r2006 Elsevier B.V All rights reserved
PACS: 64.75.+g; 73.63.b
Keywords: Segregation; Semiconductor doping; Diode; Silicon on insulator
The dimensions of semiconductor devices are
continu-ously decreasing, reaching sub-50 nm regime in many
applications [1–3] The small dimensions set stringent
requirements for the fabrication processes and in nm-scale
structures the alignment is becoming an issue In silicon
technology a pn-junction forms a basic building block in
the device fabrication In the fabrication of CMOS circuits,
even with gate lengths well below 100 nm, pn-junctions
are self-aligned, because the gate electrode (and spacers)
are used as an implantation mask In nm-scale device
structures in which this kind of masked implantation
process cannot be used, the alignment-related issues may
become unsurmountable Here we report on a self-aligning
doping method which relies on the difference in the
segregation of impurities in silicon during thermal
oxida-tion The method allows to control the doping profile, e.g.,
along wires with sub-50 nm diameter We demonstrate the
method by fabricating a unipolar lateral field effect device
with characteristics resembling those of a pn-diode
The Si–SiO2segregation coefficient of impurities can be
given as m ¼ CSi=CSiO¼aeD=kT where CSiO(CSi) is the
equilibrium impurity concentration in SiO2(Si)[4] If mo1
the impurity segregates into the oxide during thermal
oxidation while if m41 the oxide repels the impurity The
values for a and D are aBðPÞ ¼1126 (30), DBðPÞ¼ 0:91 eVð0:0 eVÞ for boron (phosphorus)[5] Thus, during thermal oxidation of silicon the growing oxide takes up p-type boron while the n-type phosphorus tends to pile up
in silicon This effect can be used to change locally the net doping concentration
Fig 1shows results of Silvaco[5]process simulation In Fig 1(a)is shown the cross section of an originally 100 nm wide and 180 nm high silicon wire after 120 min dry oxidation at 950 1C The doping concentrations before the oxidation were P0¼7 1017cm3for boron and N0¼
1 1017cm3 for phosphorus, leading to effective p-type concentration of 6 1017cm3.Fig 1(b)shows the doping profiles before and after the oxidation During thermal oxidation boron atoms segregate into the forming silicon dioxide leading to decrease in boron concentration in silicon On the other hand, the phosphorus concentration increases and the conduction type of silicon is converted to n-type with the average effective carrier concentration of
1 1016cm3 The effect is the stronger the smaller the remaining silicon volume is compared to the volume of the formed oxide In case there are two bodies with different surface to volume ratios attached to each other, the oxidation-induced change in the effective doping varies from one structure to another For example, if a narrow wire is attached to larger bulky leads the doping of the wire can be
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1386-9477/$ - see front matter r 2006 Elsevier B.V All rights reserved.
doi:10.1016/j.physe.2005.12.148
Corresponding author Tel.: +358 20 722 6644; fax: +358 20 722 7012.
E-mail address: jouni.ahopelto@vtt.fi (J Ahopelto).
Trang 2tuned, as demonstrated in Fig 1, while in the large leads
the oxidation has a minor effect on the doping Thus, by
fabricating a compensated lead–wire–lead structure and
exposing this to an oxidizing ambient we can obtain a
self-aligned pnp structure
We demonstrate the feasibility of this self-aligning
method by fabricating so called self-switching devices [6]
in silicon The device is essentially a lateral double gate
FET connected as a diode A top-view SEM image of such
a device is shown in Fig 2(a) Depending on the biasing
condition, i.e., whether the source or the drain is at higher
potential, the potential across the trenches defining the
channel either opens or closes it The devices were
processed on a 100 mm diameter silicon on insulator
(SOI) wafer with a 180 nm thick SOI film and a 400 nm
thick buried oxide (BOX) layer The whole wafer was
implanted with boron to a dose of 2:4 1013cm2 Half of
the wafer was then masked and an extra compensating implantation with phosphorus to a dose of 3:0 1012cm2
was performed These implantations produce roughly the doping concentrations P07 1017cm3 for boron and
N01 1017cm3 for phosphorus in the SOI film The large-scale mesas for the devices were defined by UV-lithography and dry etching The devices were patterned by electron beam lithography and dry etching using a 30 nm thick layer of thermal oxide as hard mask Prior to etching
of the SOI film the oxide was patterned with PMMA mask
in CHF3/CF4 plasma The trenches in the SOI film were etched using the oxide mask and Cl2/He plasma The etching selectivity between silicon dioxide and silicon is high and the process can be used to create narrow trenches with vertical walls in silicon After dry etching the wafer was oxidized in dry ambient at 950 1C for 55 min This process results in formation of a 30 nm thick oxide and
Fig 1 Simulation by Silvaco process simulator (a) 100 nm wide and 180 nm thick Si channel on SOI substrate after oxidizing at 950 1C for 120 min Prior
to the oxidation the concentrations of phosphorus and boron were N 0 ¼ 1 1017cm 3 and P 0 ¼ 7 1017cm 3 in the Si channel, respectively (zero elsewhere) (b) Concentrations along the line AB During the oxidation the phosphorus concentration has exceeded the boron concentration.
Fig 2 (a) SEM image of silicon nanodiode G3/21 with P 0 7 10 17 cm 3 and N 0 1 10 17 cm 3 The trench is defined by e-beam lithography and plasma etching The SEM image is taken prior to the oxidation, simulated in Fig 1 The channel is 50 nm wide, 150 nm thick and 530 nm long (b) Room temperature I–V curves of G3/21 and a similar device fabricated with N 0 0 The channel dimensions of the devices are the same The finite initial n-type doping N 0 1 1017cm 3 enables the diode type of operation due to the segregation-induced compensation enhancement in the channel The n-type doping has negligible effect on the source and the drain, which remain strongly p-type.
Trang 3controls the tuning of the doping profile in the device The
final thickness of the SOI film is 150 nm, the width of the
channel 50 nm and the width of the trenches 40 nm
I–V curves measured from two devices with similar
dimensions but the other without compensating
implanta-tion are shown in Fig 2(b) The uncompensated device
shows nonlinear behaviour but the I–V curve is symmetric
and not diode-like The compensated device, on the other
hand, has the desired diode like-behaviour Essential
condition for the diode operation is that the voltage drop
between the source and the drain occurs along the wire so
that the effective potential difference builds up between
the wire and the drain This condition is fulfilled for the
compensated device where the conduction type of the
channel has changed from p-type to n-type, and
conse-quently, the device has a self-aligned pnp doping profile
from drain to channel to source The quantitative doping
concentrations along the channel cannot be extracted from
the two-dimensional simulation, because the simulation
does not include the diffusion of dopants from the source
and drain into the narrow channel However, qualitatively
the behaviour is as expected
In summary, we have proposed and demonstrated a
method for self-aligning control of doping profiles in
nanoscale silicon structures The method is based on the
different segregation of p-type and n-type dopants during thermal oxidation of silicon We have applied the method
in fabrication of lateral field effect devices and show that the doping profiles can be controlled in devices with
sub-50 nm dimensions In principle, the method can be applied
in local tuning of doping in arbitrary-shaped silicon devices
as long as the different parts of the device have different surface to volume ratios
The authors want to thank M Markkanen for assisting
in the device fabrication This work has been partially funded by European Commission (NEAR IST-2001-32300) and the Academy of Finland
References
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