Design an 2 stage amplifier

Slide 1 VIETNAM NATIONAL UNIVERSITY HO CHI MINH UNIVERSITY OF SCIENCE FACULITY OF ELECTRONICS AND TELECOMMUNICATION GRADUATE COURSE IN MICROELECTRONICS Design an 2 stage amplifier Le Thanh Thien An 1.

VIETNAM NATIONAL UNIVERSITY - HO CHI MINH

UNIVERSITY OF SCIENCE FACULITY OF ELECTRONICS AND TELECOMMUNICATION

GRADUATE COURSE IN MICROELECTRONICS

Design an 2 stage amplifier

Le Thanh Thien An

1 Outline

2 Result review

3 Hand design result

4 Simulation summary result

5 Layout review

Agenda

Item

Condition

Specification

-Input offset voltage

Saturation region

-Strong inversion region

3

Result review

Item

  Specification hand-calculation simulation simulation (Post_layout)

Judge

Unit MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

Condition

Supply Voltage V 4.5 5 5.5 4.5 5 5.5 4.5 5 5.5 4.5 5 5.5

-Temperature ° C -40 25 150 -40 25 150 -40 25 150 -40 25 150

-Input voltage range V 1 1.5 2.5 1 1.5 2.5 1 1.5 2.5 1 1.5 2.5

-Specification

Current (Icc) uA - - 800 248.67 355.25 532.87 245 379 602 244.6 378.6 600.6 OK Slew rate (SR) MV/s 5 - - 7.36 10.51 15.77 5.12 8.43 15.9 5.04 8.32 15.63 OK Open Gain dB 60 - - 96.22 100.03 105.87 74.57 84.12 88.38 74.59 84.12 88.39 OK Unity Gain Frequency MHz 2 - - 6.02 7.2 8.82 2.98 6.22 14.7 2.978 6.21 14.71 OK Phase Margin deg 50 - - - 72.8 - 51.29 67.29 72.12 51.27 67.29 72.11 OK Input offset voltage

(3s + systematic) mV -10 - 10 - 9.89 - -9.85 -0.05 9.67 -9.87 -0.05 9.81

OK

Below result is from hand-calculation.

Amplifier has met all specifications

Cout = 10 pF

Hand design result (1/2)

Items unit Mpin0/Mpin1 Mnl0/Mnl1 Mno Mpr Mpt1 Mpt2

W (total W) (um) 27.33 5.9 212.24 7.47 7.47 134.39 finger/multi   2/2 2/2 2/72 2/2 2/2 2/36

J (uA/um) 0.33 1.51 1.51 2.38 2.38 2.38

Vds - Vdsat (V) 1.17 0.66 1.5 0.56 0.56 0.56 Area (um^2) 109.33 35.37 636.71 7.47 7.47 134.34

Cc(pF) Iref(A) 1.69 17.76

Area of Capacitor Cc (0.0013pF/um2)

1300 (um2)

unCox =  

6.40E-05 (A/(V^2))

upCox =  

2.41E-05 (A/(V^2))

Input offset voltage

3 σ 9.92 (mv)

Simulation results

Cc (pF) R0(kohm)

min

0.993 284

typ

1.87 228 2.27 170

5

 Step 1: Hand design and simulation

Below image shows the schematic with parameters of components

Hand design result (2/2)

Consideration (1) ICC

Current (ICC) [uA]

Contribution Analysis from DC simulation Res [kohm] Vth_MPR Vdsat_MPR I_MPR I_MPT1 I_MPT2

Typ temp = 25 deg VCCA=5V Vcm=1.5 mos_hv=TT Moscap=TT Res=TT

Worst temp = 150 deg VCCA = 5.5V Vcm=1 mos_hv=FF Moscap=Max Res= FF

Simulation result summary

7

Consideration (2) slew rate

Slew rate [Mv/s]

Contribution anaysis from DC simulation

Cc [pF]

Res [kohm]

I_MPR [uA]

I_MPT1 [uA]

I_MPT2 [uA]

Typ : temp=2 5deg VCCA=5V Vcm=1.5V mos hv=TT MosCap=TT Res=TT Worst : Temp=-4 0 VCCA=4.5 mos _hv=FS Moscap=MAX Res=SS

Consideration (2) Slew rate (2/2)

Slew rate [Mv/s]

Contribution anaysis from DC simulation

Cc [pF]

Res [kohm]

I_MPR [uA]

I_MPT1 [uA]

I_MPT2 [uA]

Typ : temp=2 5deg VCCA=5V Vcm=1.5V mos hv=TT MosCap=TT Res=TT

Worst : Temp=-4 0 VCCA=4.5 mos _hv=FS Moscap=MAX Res=SS

9

Consideration (3) Open gain

Open Gain [dB]

Contribution Analysis from DC simulation

gm _MPIN1 [uA/V]

gm _MN0 [uA/V]

ro1 [Mohm]

ro _MPIN1 [Mohm]

ro _MNL1 [Mohm]

ro2 [kohm]

ro _MN0 [kohm]

ro _MPT2 [kohm]

I_MPT2 [uA]

I_MPT2 [uA]

Typ : temp=2 5deg VCCA=5V Vcm=1.5V mos_hv=TT Moscap=TT Res=TT Worst : temp=1 50 VCCA=5.5 Vcm=1 mos_hv=FF Moscap=MAX Res=FF

Consideration (4) Unity Gain Frequency

Unity Gain Frequency [MHz]

Contribution Analysis from DC simulation

Cc [pF]

gm _MPIN 1 [uA/V]

I_MPT1 [uA]

gm _MN 0 [uA/V]

fu (calc) [MHz]

fp2 (calc) [MHz]

Typ: temp=2 5deg VCCA=5V Vcm=1.5 mos_hv=TT Moscap=TT Res=TT

Worst: temp=1 50 VCCA=4.5 Vcm=2.5 mos_hv=ss Moscap=MAX Res=SS

11

 Simulation result does not match with hand design It’s decreased by fz The error factor: Cc, gm_PIN1, gm_MN0

Consideration (5) Phase Margin (1/2)

Phase Margin [deg]

Contribution Analysis from DC simulation fu

(calc) [MHz]

fp2 (calc) [MHz]

fz (calc) [MHz]

Cc [pF]

gm_MPIN1 [uA/V]

gm_MN0 [uA/V]

I_MPT1 [uA]

I_MPT2 [uA]

Typ temp=25deg VCCA=5V Vcm=1 mos_hv=TT moscap=TT Res=TT

Worst tem=-40 VCCA=5.5 Vcm=1 mos_hv=SF moscap=Min Res=FF

Consideration (5) Phase Margin (2/2)

Phase Margin [deg]

Contribution Analysis from DC simulation fu

(calc) [MHz]

fp2 (calc) [MHz]

fz (calc) [MHz]

Cc [pF]

gm_MPIN1 [uA/V]

gm_MN0 [uA/V]

I_MPT1 [uA]

I_MPT2 [uA]

Typ temp=25deg VCCA=5V Vcm=1 mos_hv=TT moscap=TT Res=TT

Worst tem=-40 VCCA=5.5 Vcm=1 mos_hv=SF moscap=Min Res=FF

13

Consideration (6) Offset Voltage:

Random

Random offset voltage [mv]

Contribution Analysis from DC simulation

σVth_diff [mv]

σVth_load [mv]

gm_MPIN1 [uA/V]

gm_MNL1 [uA/V]

(Ratio) gm_MNL1/gm_MPIN1 [uA/V]

Consideration (7) Offset voltage:

Systematic

Systematic offset voltage [mv]

Contribution Analysis from DC simulation

Delta Vgs*

[mv]

Av1 [V/V]

gm_MPIN1 [uA/V]

ro1 [Mohm]

ro MPIN1 [Mohm]

ro MNL1 [Mohm]

Typ temp=25deg VCCA=5V Vcm=1.5V mos_hv=TT Moscap=TT Res=TT

Worst temp=150deg VCCA=5.5V Vcm=1 mos_hv=SS Moscap=MAX RES=TT

Delta Vgs* = Vgs_MN0 - Vgs_MNL0

15

Circuit schematic for layout

Layout

R & Dummy R

Cc

Output Mos

DM : Dummy

MPT2

MPIN1

MPIN1 MPIN0

MPIN0

MNL0

DM DM

DM DM

DM DM

DM DM

MNL0 MNL1

MNL1

Antenna

diodes

common centroid

close to gate with mosfets

current source mosfets

45.8 um

71,8 um

17

1 VPT1: Tail signal is short and route straight due to center line of differential pair.

2 OUT: short and width correspond with current ratio

Important nets

Important nets

3 VNL0-VNL1: routing common centroid , using some dummy metal

4 OUT: increase wiring width for long nets

19

THANK FOR YOUR ATTENTION