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Digital Design FlowCompilation and Synthesis Analysis Synthesis Routing and placement Behavioral Simulation Assertion Verification Formal Verification Design Entry in Verilog always pose

Verilog Digital System Design

Z Navabi, McGraw-Hill, 2005

Chapter 1 Digital System Design Automation with Verilog

Prepared by:

Homa Alemzadeh

Digital System Design Automation with Verilog

1.1 Digital Design Flow

Digital System Design

Automation with Verilog

 As the size and complexity of digital systems increase,

more computer aided design (CAD) tools are introduced into the hardware design process

 Early simulation and primitive hardware generation tools have given way to sophisticated design entry, verification, high-level synthesis, formal verification, and automatic hardware generation and device programming tools

 Growth of design automation tools is largely due to

hardware description languages (HDLs) and design

methodologies that are based on these languages

 Based on HDLs, new digital system CAD tools have been developed and are now widely used by hardware

designers

 One of the most widely used HDLs is the Verilog HDL

 Because of its wide acceptance in digital design industry, Verilog has become a must-know for design engineers

and students in computer-hardware-related fields.

Digital Design Flow

Compilation and Synthesis

Analysis Synthesis Routing and placement

Behavioral Simulation Assertion Verification Formal Verification

Design Entry in Verilog

always (posedge clk) begin end

Digital Design Flow

Design Entry in Verilog

always (posedge clk) begin end

Digital Design Flow

design at various levels of abstraction.

mixture of behavioral

Verilog code, instantiation of Verilog modules, and bus and wire assignments

Compilation and Synthesis

Analysis Synthesis Routing and placement

Digital Design Flow

 FPLD Design Flow

(Continued)

Presynthesis Verification

Digital Design Flow

verification of the design and later for verifying the synthesis output

Compilation and Synthesis

Analysis Synthesis Routing and placement

Digital Design Flow

 FPLD Design Flow

(Continued)

Synthesis Process

Digital Design Flow

hardware of a target device (FPLD, ASIC or custom IC)

Digital Design Flow

 FPLD Design Flow (Continued)

Postsynthesi

s Verification

Digital Design Flow

model of the design and its hardware model by using presynthesis test data

Digital Design Flow

 FPLD Design Flow (Continued)

Digital Design Flow

an application specific integrated circuits (ASIC), layout for a custom IC, or a program for a

programmable logic devices (PLD)

Digital Design

Flow

Hardware Generation

and Synthesis Postsynthesis

Simulation

Timing Analysis

Digital Design Flow

Digital Design

Flow

Hardware Generation

and Synthesis Postsynthesis

Simulation

Timing Analysis

Design Entry

Design Entry

Design Entry

hierarchical fashion

designs usually described at this level

 procedural statements for high-level behavioral

description

 continuous assignments for representing logic

blocks, bus assignments, and bus and input/output interconnect specifications

 instantiation statements for using lower-level

components in an upper-level design

Digital Design

Flow

Hardware Generation

and Synthesis Postsynthesis

Simulation

Timing Analysis

Testbench in Verilog

Testbench in Verilog

Testbench in Verilog

 Simulation and Test of a designed system functionality

before Hardware generation

 Detection of design errors and incompatibility of

components used

 in the design

 By generation of a test data and observation of simulation results

 Testbench: A Verilog module

 Use of high-level constructs of Verilog for:

 Data Generation

 Response Monitoring

 Handshaking with the design

 Inside the Testbench: Instantiation of the design

module

 Forms a simulation model together with the design,

used by a Verilog simulation engine

Digital Design

Flow

Hardware Generation

and Synthesis Postsynthesis

Simulation

Timing Analysis

Design Validation

Design Validation

Design Validation

Design Validation

Design Validation

Design Validation

at the gate or transistor levels

waveform editors, or through a testbench

Other forms

Simulation Model

Hierachical Design Description Simulator

Text, VCD

`timescale 1 ns / 100 ps module Chap1CounterTester ();

Chap1Counter U1 (Clk, Reset, Count);

Design to Simulate

The simulation results in form of a waveform

Simulation The testbench

instantiates the design under test, and as part

of the code of the testbench it applies test data to the instantiated circuit

Simulation

Validates the functionality of the counter circuit being tested,

Regardless of clock frequency

differently

there will be a nonzero delay between the active edge

of the clock and the counter output

actual part is too fast for propagation of values within the gates and transistors of a design, the output of

the design becomes unpredictable

details of the timing of the hardware being simulated

that are due to gate delays cannot be detected

behavioral simulation.

Assertion Verification

Design Validation

Verification

of design according to the designer’s expectation

assertion monitors for monitoring common design

properties

Formal Verification

Design Validation

Verification

Formal Verification

against certain properties

described properties by the designer to reflect

correct behavior of the design hold under all

conditions

property to fail

exercised by the property

Digital Design

Flow

Hardware Generation

and Synthesis Postsynthesis

Simulation

Timing Analysis

Compilation and

Synthesis

Compilation And Synthesis

Compilation and

Synthesis

generation from a design description that has an unambiguous hardware correspondence

specifications, file handling, and other language

combinational logic equations

combinational and sequential circuits

Logic

Routing and Placement

Timing Analysis

Target Hardware Specification

Chip Manufacturing or Device Programming

always (posedge clk) begin end

if (…) bus = w;

else

module design ( .);

assign always

ng an FPLD

or

The compilation process and a graphical representatio

n for each of

the compilation phase outputs

an intermediate

format.

Compilation and

Synthesis

Synthesis Phase: Links

all parts together and

generates the

Has three different

phases

Compilation and

Synthesis

Routing and Placement

Phase: Places and routes components of the target hardware, and generates timing

details.

Routing and Placement

Timing Analysis

T = … ; T =

Operating Condition

Chip Manufacturing

or Device Programming

Compilation and

and Synthesis

Routing and Placement

Generation Logic

Compilation and Synthesis

Routing and Placement

Generation

Logic

Analysis

Verilog code

Generic Hardware

and Synthesis

Routing and Placement

Generic Hardware

Generation

into a generic hardware format such as a set of Boolean expressions or a netlist of basic gates

Logic Optimization

Compilation and Synthesis

Routing and Placement

Generation

Logic

Logic Optimization

Logic Optimization

Compilation and Synthesis

Routing and Placement

Generation Logic

needed for the realization of the circuit using

information from target hardware

used

Routing and Placement

Compilation and Synthesis

Routing and Placement

Generation

Logic

Routing and Placement

Routing and Placement

channels and switching areas of the target hardware

can be used for programming an FPLD or

manufacturing an ASIC.

Routing and Placement

module Chap1Counter (Clk, Reset, Count);

- Pin-to-pin timing

Design to Synthesize

An example

of a synthesis run: The counter circuit is being synthesized

Routing and Placement

module Chap1Counter (Clk, Reset, Count);

Target hardware specification

List of primitive components

- Flip-flops

- Logic elements Timing specifications

- Pin-to-pin timing

Design to Synthesize

Verilog Description

of the Design

Specificatio

n

of the Target Hardware

Synthesis Tool

Routing and Placement

their

Digital Design

Flow

Hardware Generation

and Synthesis Postsynthesis

Simulation

Timing Analysis

Postsynthesis

Simulation

Postsynthesis Simulation

Post-synthesis Simulation

hardware components and their timings is generated.

wires and gates.

Digital Design

Flow

Hardware Generation

and Synthesis Postsynthesis

Simulation

Timing Analysis

Timing Analysis

Timing Analysis

circuits.

Digital Design

Flow

Hardware Generation

and Synthesis Postsynthesis

Simulation

Timing Analysis

Hardware Generation

Hardware Generation

Hardware Generation

program for programming FPLDs, or layout of custom

IC cells

Verilog HDL

Verilog HDL

Verilog

Evolution

Verilog Attributes

The Verilog Language

Verilog Evolution

Verilog HDL

Verilog

Evolution

Verilog Attributes

The Verilog Language

Verilog

Evolution

Verilog Evolution

industry, a fault simulator, a timing analyzer, and later in

1987, a synthesis tool was developed based on this language.

Verilog-based tools by Cadence Design System, Cadence has been a strong force behind popularizing the Verilog hardware

description language.

description language.

projects and contracts.

Verilog International) was formed and Verilog was placed in public domain.

Verilog became the IEEE standard, IEEE Std 1364-1995, in 1995.

Verilog Evolution

IEEE in 2001

write

Verilog Attributes

Verilog HDL

Verilog

Evolution

Verilog Attributes

The Verilog Language

Verilog Attributes

Verilog Attributes

describing hardware from transistor level to

behavioral.

simulation and at the same time, has features for

describing hardware at the abstract algorithmic

level.

at various abstraction levels with different degrees of detail.

Verilog Attributes

PLI

Specifications Behavioral

Verilog Attributes

Verilog Attributes

PLI

Specifications Behavioral

Switch Level

Switch Level

Switch Level

and simulation:

with parameters for delay and charge storage

rise and fall delay, and line delays

complimentary metal oxide semicondutor (CMOS)

and metal oxide semiconductor (MOS) circuits.

Verilog Attributes

PLI

Specifications Behavioral

Gate Level

Gate Level

Gate Level

provide a convenient platform for:

simulations:

special functionalities:

for more accurate logic modeling

Verilog Attributes

PLI

Specifications Behavioral

Pin-To-Pin Delay

Pin-To-Pin Delay

Pin-To-Pin Delay

components at the input/output level:

information in original predesigned descriptions

their models based on physical implementations

Verilog Attributes

PLI

Specifications Behavioral

Bussing Specifications

Bussing Specifications

Bussing Specifications

bus resolution functions using the 4-value logic value system

enable modeling of most physical bus types

representation and timing-control constructs can be used for representation of registers with various

clocking and resetting schemes.

Verilog Attributes

PLI

Specifications Behavioral

Behavioral Level

Behavioral

Level

Behavioral Level

representations of hardware structures

languages are provided for describing hardware at this level.

Verilog Attributes

PLI

Specifications Behavioral

System Utilities

System Utilities

 Special hardware modeling

logic array (PLA) images provide convenient ways of

modeling these components.

 Verilog display and I/O tasks can be used to handle all inputs and outputs for data application and simulation

 Verilog allows random access to files for read and write operations.

Verilog Attributes

PLI

Specifications Behavioral

PLI

PLI

The Verilog Language

Verilog HDL

Verilog

Evolution

Verilog Attributes

The Verilog Language

The Verilog Language

The Verilog Language

and synthesis of digital systems:

from system to gate or even switch level

specification and violation detection

modeling are specially emphasized in it.

module_declaration language construct in it

The Verilog Language

and synthesis of digital systems (Continued):

input and output list as well as internal component busses and registers within a module, concurrent

assignments, component instantiations, and

procedural blocks can be used to describe a

hardware component.

form other hardware structures

provide simulation, fault simulation, formal

verification, and synthesis

programs and waveform editing and display tools

used for taking a design from the design stage to a hardware implementation

developers, researchers, and software vendors

have become more focused, resulting in better

tools and more uniform environments