Electrical Engineering Essentials http://www.springer.com/series/10854 Series Editor Anantha P. Chandrakasan For further volumes: Dejan Markovic Robert W. Brodersen ғ K DSP Architecture Design Essentials ISBN 978-1-4419-9659-6 ISBN 978-1-4419-9660-2 (e-Book) DOI 10.1007/978-1-4419-9660-2 Springer New York Heidelberg Dordrecht London Library of Congress Control Number: 2012938948 © This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Springer Science+Business Media New York 2012 Please note that additional material for this book can be downloaded from http://extras.springer.com Dejan Markoviþ Associate Professor Electrical Engineering Department University of California, Los Angeles Los Angeles, CA 90095 USA Robert W. Brodersen Professor Emeritus University of California, Berkeley Berkeley, CA 94704 USA Berkeley Wireless Research Center Contents Preface Part I: Technology Metrics 1. Energy and Delay Models 3 2. Circuit Optimization 21 3. Architectural Techniques 4. Architecture Flexibility Part II: DSP Operations and Their Architecture 69 5. Arithmetic for DSP 71 6. CORDIC, Divider, Square Root 91 7. Digital Filters 111 8. Time-Frequency Analysis FFT and Wavelets 145 Part III: Architecture Modeling and Optimized Implementation 171 9. Data-Flow Graph Model 173 10. Wordlength Optimization 181 11. Architectural Optimization 201 12. Simulink-Hardware Flow 225 Part IV: Design Examples: GHz to kHz 2 13. Multi-GHz Radio DSP 255 277 15. MHz-rate Multi-Antenna Decoders Flexible Sphere Decoder Chip Examples 295 16. kHz-Rate Neural Processors 321 Brief Outlook 341 Index 347 vii 1 39 57 53 : : 14. Dedicated S Chip ExampleMHz-rate Multi-Antenna Decoders VD : Slide P.1 The advancement of semiconductor industry over the past few decades has made significant social and economic impacts by providing inexpensive computing and communication technologies. Our ability to access and process increasing amounts of data has created a major shift in information technology towards parallel data processing. Today’s microprocessors are deploying multiple processor cores on a single chip to increase performance; radios are starting to use multiple antennas to transmit data faster and farther; new technologies are needed for processing large records of data in biomedical applications. The fundamental challenge in all these applications is how to map data processing algorithms onto the underlying hardware while meeting application constraints for power, performance, and area. Digital signal processing (DSP) architecture design is the key for successful realization of many diverse applications in hardware. The tradeoff of various types of architectures to implement DSP algorithms has been a topic of research since the initial development of the theory. Recently, the application of these DSP algorithms to systems that require low cost and the lowest possible energy consumption has placed a new emphasis on defining the most appropriate solutions. The flexibility consideration has become a new dimension in the algorithm/architecture design. Traditional approach to provide flexibility has been through software programming a Von Neumann architecture. This approach was based on technology assumptions that hardware was expensive and the power consumption was not critical so time multiplexing was used to provide maximum sharing of the hardware resources. The situation now for highly integrated system-on-a-chip implementations is fundamentally different: hardware is cheap with potentially 1000’s of multipliers and adders on a chip and the energy consumption is a critical design constraint in portable applications. Even in the case of applications that have an unlimited energy source, we have moved into an era of power-constrained performance since heat removal requires the processor to operate at lower clock rates than dictated by the logic delays. This book, therefore, addresses DSP architecture design and the application of advanced DSP algorithms to heavily power-constrained micro-systems. Preface Slide P.2 This book addresses the need for DSP architecture design that maps advanced DSP algorithms to the underlying hardware technology in the most area- and energy-efficient way. Architecture design is expensive and architectural changes have not been able to track the pace of technology scaling. The ability to quickly explore many architectural realizations is essential for selecting the architecture that best utilizes the intrinsic computational efficiency of silicon technology. In addition to tracking the advancements in technology, advanced DSP algorithms greatly increase computational complexity. At the same time, more flexibility to support multiple operation modes and/or multiple standards is needed in portable devices. Traditionally, algorithms and architectures are developed by different engineering teams, who also use different tools to describe their designs. Clearly, there is a pressing need for DSP architecture design that tightly couples into algorithmic and technology parameters, in order to deliver the most effective solution in power-limited regime. In response to the above challenges, this book provides systematic methodology for algorithm modeling, architecture description and mapping, and various hardware optimizations that take into account algorithm, architecture, and technology layers. This interaction is essential, because algorithmic simplifications can often far outstrip any energy savings possible in the implementation step. The outcomes of the proposed approach, generally speaking, are hardware-aware algorithm development and its optimized hardware implementation. Why This Book?  Goal: to address the need for area/energy-efficient mapping of advanced DSP algorithms to the underlying hardware technology  Challenges in digital signal processing (DSP) chip design – Higher computational complexity for advanced DSP algorithms – More flexibility (multi-mode, multi-standard) required – Algorithm and hardware design are often separate – Power-limited performance  Solution: systematic methodology for algorithm specification, architecture mapping, and hardware optimizations – Outcome 1: hardware-friendly algorithm development – Outcome 2: optimized hardware implementation P. 2 viii DSP Architecture Design Essentials Preface ix Slide P.3 The key feature of this book is a design methodology based on a high-level design model that leads to hardware implementation that is optimized for performance, power, and area. The methodology includes algorithm-level considerations such as automated wordlength reduction and unique data properties that can be leveraged to simplify the arithmetic. Starting point for architectural optimizations is a direct-mapped architecture, because it is well defined. From a high-level data- flow graph (DFG) model for the reference architecture, a methodology based on linear the underlying technology. Once architectural solutions are available, any of the architecture design points can be mapped through commercial and semi-custom flows to field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) hardware platforms. As a final step, FPGA-based logic analysis is used to verify ASIC chips using the same design environment, which greatly simplifies the debugging process. To exemplify the use of the design methodology described above, many examples will be discussed to demonstrate diverse range of application requirements. Applications ranging from kHz to GHz rates will be illustrated and results from working ASIC chips will be presented. The slide material provided in the book is supplemented with additional examples, links to reference material, CAD tutorials, and custom software. All the supplements are available online. More detail about the online content is provided in Slide P.11. Slide P.4 The material in this book is a result of many years of development and classroom use. It started as a class material (Communications Signal Processing, EE225C) at UC Berkeley, developed by professors Bob Brodersen, Jan Rabaey, and Bora Nikoliý in the 1990s and early 2000s. Many concepts were applied and extended in research projects at the Berkeley Wireless Research Center in the early 2000s. These include automated Simulink-to- silicon toolflow (by R. Davis, H. So, Highlights  A design methodology starting from a high-level description to an implementation optimized for performance, power and area  Unified description of algorithm and hardware parameters – Methodology for automated wordlength reduction – Automated exploration of many architectural solutions – Design flow for FPGA and custom hardware including chip verification  Examples to show wide throughput range (kS/s to GS/s) – Outcomes: energy/area optimal design, technology portability  Online resources: examples, references, tutorials etc. P. 3 Book Development  Over 15 years of effort and revisions… – Course material from UC Berkeley (Communication Signal Processing, EE225C), ~1995-2003 Ɣ Profs. Robert W. Brodersen, Jan M. Rabaey, Borivoje Nikoliđ – The concepts were applied and expanded by researchers from the Berkeley Wireless Research Center (BWRC), 2000-2006 Ɣ W. Rhett Davis, Chen Chang, Changchun Shi, Hayden So, Brian Richards, Dejan Markoviđ – UCLA course (VLSI Signal Processing, EE216B), 2006-2008 Ɣ Prof. Dejan Markoviđ – The concepts expanded by researchers from UCLA, 2006-2010 Ɣ Sarah Gibson, Vaibhav Karkare, Rashmi Nanda, Cheng C. Wang, Chia-Hsiang Yang  All of this is integrated into the book – Lots of practical ideas and working examples P. 4 programming is used to create many different architectural solutions, within constraints dictated by DSP Architecture Design Essentials B. Richards), automated wordlength optimization (by C. Shi), the BEE (Berkeley Emulation Engine) FPGA platforms (by C. Chang et al.), and the use of this infrastructure in chip design (by D. Markoviý and Z. Zhang). spike analysis (by S. Gibson and V. Karkare), automated architecture transformations (by R. Nanda), revisions to wordlenght optimization tool (by C. Wang), flexible architectures for multi-mode and multi-band radio DSP (by C H. Yang). All this knowledge is integrated in this book. The material will be illustrated on working hardware examples and supplemented with online resources. Slide P.5 The material is organized into four parts: (1) technology metrics, (2) DSP operations and their architecture, (3) architecture modeling and optimized implementation, and (4) design examples. The first part introduces technology metrics and their impact on architecture design. Towards implementation, the second part discusses number representation, fixed-point effects, basic direct and recursive DSP operations and their architecture. Putting the technology metrics and architecture concepts together, Part 3 provides data-flow graph based model and discusses automated architecture exploration using linear programming methods. Quantization effects and hardware design flow are also discussed. Finally, Part 4 demonstrates the use of architecture design methodology and hardware mapping flow on several examples to show architecture optimization under different sampling rates and amounts of flexibility. The emphasis is placed on flexibility and parallel data processing. To get a quick grasp of the book content, visual highlights from each of the parts are provided in the next few slides. Organization  The material is organized into four parts Technology Metrics DSP Operations & Their Architecture Architecture Modeling & Optimized Implementation Design Examples: GHz to kHz 1 2 3 4 Performance, area, energy tradeoffs and their implication on architecture design Number representation, fixed- point, basic operations (direct, iterative) & their architecture Data-flow graph model, high- level scheduling and retiming, quantization, design flow Radio baseband DSP, parallel data processing (MIMO, neural spikes), architecture flexibility P. 5 x The material was further developed at UCLA as class material by Prof. D. Marković and EE216B (VLSI Signal Processing) students. Additional topics include algorithms and architectures for neural- [...]... tradeoffs is important to ensure that the implemented algorithms fully utilize the performance capabilities of the underlying technology D Markovi and R.W Brodersen, DSP Architecture Design Essentials, Electrical Engineering Essentials, DOI 10.1007/978-1-4419-9660-2_1, © Springer Science+Business Media New York 2012 3 4 Chapter 1 Slide 1.3 Power and Energy Figures of Merit Let’s start with power and energy... optimization is the optimal energy-delay tradeoff line, and the values of the tuning variables at each point along the tradeoff line D Markovi and R.W Brodersen, DSP Architecture Design Essentials, Electrical Engineering Essentials, DOI 10.1007/978-1-4419-9660-2_2, © Springer Science+Business Media New York 2012 21 22 Chapter 2 Slide 2.3 Energy Model for Circuit Optimization Based on energy and delay... Frequency Int Iterative DSP algorithms for standard ops, convergence analysis, the choice of initial condition Frequency Ch 5: Arithmetic for DSP 1 critical mult add Time Time DSP Architecture Design Essentials xii Part 3: Architecture Model & Opt Implementation Slide P.8 Having defined technology metrics in Part 1, algorithm and architecture x (n) x (n) Example: 1/sqrt() v v techniques in Part 2,... computation at the same frequency 1.3 Power is the rate at which energy is delivered or exchanged; power dissipation is the rate at which energy is taken from the source (VDD) and converted into heat (electrical energy is converted into heat energy during circuit operation) Power is expressed in watts and determines battery life in hours (instantaneously measures how much energy is taken out of energy... supply voltage can be lumped together in the effective fanout parameter heff as defined on this slide In logical effort terms, this parameter is g(VDD, VTH)·h, where g is the logical effort and h is the electrical effort (fanout) Such a formulation allows for consideration of voltage effects together with the sizing problem typically considered in the logical effort delay model Chapter 2 will make use... shrinking Hard output Hard-output Sphere Decoder trace-back 128-2048 pt FFT FT Reg File Bank k P Pre-proc Detection Soft-output Bank ft-outp ft tput k Analog Front End xiv DSP Architecture Design Essentials Online Material Online content – References (papers, books, links, etc.) – Design examples (mini projects) – Custom software (architecture transformations) – CAD tutorials (hardware mapping . 2012 D. Markoviü and R.W. Brodersen, DSP Architecture Design Essentials, Electrical Engineering Essentials, Slide 1.3 Let’s start with power and energy. Electrical Engineering Essentials http://www.springer.com/series/10854 Series Editor