Tài liệu Digital systems testing and testable design P2 ppt

The combinational element model corresponding to a JK F/F is defined by the truth table in Figure 2.10a.. Functional Modeling at the Logic Level 17 2.2.3 Binary Decision Diagrams A bina

combinational circuit C

F/F

CLOCK

Figure 2.5 Canonical structure of a synchronous sequential circuit

JK

(a) JK flip-flop

0 T1

y

(b) T (Trigger) flip-flop

0° |

y

(c) D (Delay) flip-flop

Figure 2.6 Three types of flip-flops

caused by a single input change to /;, until a stable configuration is reached, denoted

by the condition N (q;,/;) = q; Such stable configurations are shown in boldface in the flow table Figure 2.7 shows a flow table for an asynchronous machine, and Figure 2.8 shows the canonical structure of an asynchronous sequential circuit

Functional Modeling at the Logic Level 15

X 1X2

1,0 | 5,1 2,0 1,0

10 | 2,0 | 2,0 5,1 3,1 2,0 | 4.0 | 3,0 3,1 5,1 4,0 | 4,0 3,1 5,1 4,0 5,1

Figure 2.7 A flow table

combinational

circuit

Figure 2.8 Canonical structure of an asynchronous sequential circuit

For test generation, a synchronous sequential circuit S can be modeled by a pseudocombinational iterative array as shown in Figure 2.9 This model is equivalent

to the one given in Figure 2.5 in the following sense Each cell C(i) of the array is identical to the combinational circuitC of Figure 2.5 If an input sequence x(O) x(1) x(k) is applied to S in initial state y(O0), and generates the output sequence z(0) z(1) z(k) and state sequence y(1) y(2) y(K + 1), then the iterative array will generate the output z(7) from cell 7, in response to the input x(i) to cell i (1 < i < &) Note that the first cell also receives the values corresponding to y(0) as inputs In this transformation the clocked F/Fs are modeled as combinational elements, referred to as pseudo-F/Fs For a JK F/F, the inputs of the combinational model are the present state q and the excitation inputs J and K, and the outputs are the next state g* and the device outputs y and y The present state g of the F/Fs in cell i must be equal to the q* output of the F/Fs in cell i-1 The combinational element model corresponding to

a JK F/F is defined by the truth table in Figure 2.10(a) Note that here g* = y Figure 2.10(b) shows the general F/F model

Y(1)| F/F y4) ¥(2)| F/F y2 y0) YU+1)) F/F | y@+1)

Figure 2.9 Combinational iterative array model of a synchronous sequential

circuit

|

T

|

y next state

(b)

Figure 2.10 (a) Truth table of a JK pseudo-F/F (b) General model of a

pseudo-F/F

This modeling technique maps the time domain response of the sequential circuit into a space domain response of the iterative array Note that the model of the combinational part need not be actually replicated This transformation allows test generation methods developed for combinational circuits to be extended to synchronous sequential circuits A similar technique exists for asynchronous sequential circuits

Functional Modeling at the Logic Level 17

2.2.3 Binary Decision Diagrams

A binary decision diagram [Lee 1959, Akers 1978] is a graph model of the function of

a circuit A simple graph traversal procedure determines the value of the output by sequentially examining values of its inputs Figure 2.11 gives the diagram of

f = abc +c The traversal starts at the top At every node, we decide to follow the left or the right branch, depending on the value (0 or 1) of the corresponding input variable The value of the function is determined by the value encountered at the exit branch For the diagram in Figure 2.11, let us compute f for abc=001 At node a we

take the left branch, then at node b we also take the left branch and exit with value 0

(the reader may verify that when a=0 and b=0, f does not depend on the value of c)

If at an exit branch we encounter a variable rather than a value, then the value of the function is the value of that variable This occurs in our example for a=1; here f=c

f

Figure 2.11 Binary decision diagram of f = abc + ac

When one dot is encountered on a branch during the traversal of a diagram, then the final result is complemented In our example, for a=O and b=1, we obtain f=c If

more than one dot is encountered, the final value is complemented if the number of

dots is odd

Binary decision diagrams are also applicable for modeling sequential functions Figure 2.12 illustrates such a diagram for a JK F/F with asynchronous set (S) and reset (R) inputs Here q represents the previous state of the F/F The diagram can be entered to determine the value of the output y or y For example, when computing y

for S=0, R=0, C=1, and g=1, we exit with the value of K inverted (because of the dot),

ie., y=K The outputs of the F/F are undefined (x) for the "illegal" condition S$ = 1 and R = 1

The following example [Akers 1978] illustrates the construction of a binary decision diagram from a truth table

Example 2.1: Consider the truth table of the function f=abc +ac, given in Figure 2.13(a) This can be easily mapped into the binary decision diagram of Figure 2.13(b), which is a complete binary tree where every path corresponds to one of the eight rows of the truth table This diagram can be simplified as follows Because both branches from the leftmost node c result in the same value 0, we remove this

S

Figure 2.12 Binary decision diagram for a JK F/F

node and replace it by an exit branch with value 0 Because the left and right branches

from the other c nodes lead to 0 and 1 (or 1 and 0) values, we remove these nodes and

replace them with exit branches labeled with c (or c) Figure 2.13(c) shows the resulting diagram Here we can remove the rightmost b node (Figure 2.13(d)) Finally, we merge branches leading to c and ¢ and introduce a dot to account for

2.2.4 Programs as Functional Models

A common feature of the modeling techniques presented in the previous sections is that the model consists of a data structure (truth table, state table, or binary decision diagram) that is interpreted by a model-independent program A different approach is

to model the function of a circuit directly by a program This type of code-based modeling is always employed for the primitive elements used in a structural model In general, models based on data structures are easier to develop, while code-based models can be more efficient because they avoid one level of interpretation (Modeling options will be discussed in more detail in a later section)

In some applications, a program providing a functional model of a circuit is automatically generated from a structural model If only binary values are considered, one can directly map the logic gates in the structural model into the corresponding logic operators available in the target programming language For example, the following assembly code can be used as a functional model of the circuit shown in

Figure 2.14 (assume that the variables A,B, ,Z store the binary values of the signals A,B, ,Z):

Functional Modeling at the Logic Level 19

(a)

(b)

a (a) (a)

Figure 2.13 Constructing a binary decision diagram

LDA A /* load accumulator with value of A */

AND B_ /* compute A.B */

AND C /* compute A.B.C */

STA E — /* store partial result */

LDA D _ /* load accumulator with value of D */

INV /* compute D */ _

OR E /* compute A.B.C + D */

STA Z /* store result */

Qa

Figure 2.14

Using the C programming language, the same circuit can be modeled by the following:

E=A&B&C F=~D Z=E|F

As the resulting code is compiled into machine code, this type of model is also referred to as a compiled-code model

2.3 Functional Modeling at the Register Level

2.3.1 Basic RTL Constructs

RTLs provide models for systems at the register and the instruction set levels In this section we will discuss only the main concepts of RTL models; the reader may refer to

[Dietmeyer and Duley 1975, Barbacci 1975, Shahdat et al 1985] for more details

Data (and control) words are stored in registers and memories organized as arrays of registers Declaring the existence of registers inside the modeled box defines a skeleton structure of the box For example:

register [R [0-7]

defines an 8-bit register /R, and

memory ABC [0-4255; 0-15]

denotes a 256-word memory ABC with 16-bit/word

The data paths are implicitly defined by describing the processing and the transfer of data words among registers RTL models are characterized as functional, because they emphasize functional description while providing only summary structural information

Functional Modeling at the Register Level 21

The processing and the transfer of data words are described by reference to primitive

operators For example, if A, B, and C are registers, then the statement

C=A+B

denotes the addition of the values of A and B, followed by the transfer of the result into C, by using the primitive operators "+" for addition and "=" for transfer This notation does not specify the hardware that implements the addition, but only implies its existence

A reference to a primitive operator defines an operation The control of data transformations is described by conditional operations, in which the execution of operations is made dependent on the truth value of a control condition For example,

if X thenC =A+B

means that C = A + B should occur when the control signal X is 1 More complex control conditions use Boolean expressions and relational operators; for example:

if (CLOCK and (AREG < BREG)) then AREG = BREG

States that the transfer AREG = BREG occurs when CLOCK = 1 and the value contained in AREG is smaller than that in BREG

Other forms of control are represented by constructs similar to the ones encountered in programming languages, such as 2-way decisions (if then else) and multiway decisions The statement below selects the operation to be performed depending on the value contained in the bits 0 through 3 of the register /R

test (/R[0—>3]) case 0: operatiang case 1: operation,

case 15: operation,;5 testend

This construct implies the existence of a hardware decoder

RTLs provide compact constructs to describe hardware addressing mechanisms For example, for the previously defined memory ABC,

ABC[3]

denotes the word at the address 3, and, assuming that BASEREG and PC are registers

of proper dimensions, then

ABC[BASEREG + PC]

denotes the word at the address obtained by adding the current values of the two registers

Combinational functions can be directly described by their equations using Boolean

operators, as in

Z = (A and B) or C

When Z, A, B, and C are n-bit vectors, the above statement implies n copies of a

circuit that performs the Boolean operations between corresponding bits

Other primitive operators often used in RTLs are shift and count For example, to shift AREG right by two positions and to fill the left positions with a value 0, one may specify

shift_right (AREG, 2, 0)

and incrementing PC may be denoted by

incr (PC) Some RTLs allow references to past values of variables If time is measured in "time units,” the value of X two time units ago would be denoted by X(—2) [Chappell et al 1976] An action caused by a positive edge (0 to 1 transition) of X can be activated by

if (X(—1)=0 and X=1) then

where X is equivalent to X(0) and represents the current value of X This concept introduces an additional level of abstraction, because it implies the existence of some memory that stores the "history" of X (up to a certain depth)

Finite-state machines can be modeled in two ways The direct approach is to have a state register composed of the state variables of the system State transitions are implemented by changing the value of the state register A more abstract approach is

to partition the operation of the system into disjoint blocks representing the states and identified by state names Here state transitions are described by using a go to

operator, as illustrated below:

state S1, S82, S3

Si: if X then begin P=Q+R

go to S2 end else P=Q-R

go to S3

S2:

Functional Modeling at the Register Level 23

Being in state S/ is an implicit condition for executing the operations specified in the

SI block Only one state is active (current) at any time This more abstract model allows a finite state machine to be described before the state assignment (the mapping

between state names and state variables) has been done

2.3.2 Timing Modeling in RTLs

According to their treatment of the concept of time, RTLs are divided into two categories, namely procedural languages and nonprocedural languages A procedural RTL is similar to a conventional programming language where statements are sequentially executed such that the result of a statement is immediately available for

the following statements Thus, in

A=B C=A

the value transferred into C is the new value of A (i.e., the contents of B) Many

procedural RTLs directly use (or provide extensions to) conventional programming languages, such as Pascal [Hill and vanCleemput 1979] or C [Frey 1984]

By contrast, the statements of a nonprocedural RTL are (conceptually) executed in parallel, so in the above example the old value of A (ie., the one before the

transfer A = B) is loaded into C Thus, in a nonprocedural RTL, the statements

A=B B=A

accomplish an exchange between the contents of A and B

Procedural RTLs are usually employed to describe a system at the instruction set level

of abstraction An implicit cycle-based timing model is often used at this level Reflecting the instruction cycle of the modeled processor, during which an instruction

is fetched, decoded, and executed, a cycle-based timing model assures that the state of the model accurately reflects the state of the processor at the end of a cycle

More detailed behavioral models can be obtained by specifying the delay associated with an operation, thus defining when the result of an operation becomes available For example:

C=A+B, delay = 100

shows that C gets its new value 100 time units after the initiation of the transfer Another way of defining delays in an RTL is to specify delays for variables, rather than for operations In this way, if a declaration

delay C 100

has been issued, then this applies to every transfer into C

Some RTLs allow a mixture of procedural and nonprocedural interpretations Thus, an RTL that is mostly procedural may have special constructs to denote concurrent