MPP 5 V CC Uses push-pull eff ect and com-
35. A small quiescent current is necessary with a Class-AB
b. Destroying the compensating diodes
c. Excessive current drain d. Loading the driver stage
SEC. 10-2 T WO LOAD LINES
10-1 What is the dc collector resistance in Fig. 10-38?
What is the dc saturation current?
10-2 In Fig. 10-38, what is the ac collector resistance?
What is the ac saturation current?
10-3 What is the maximum peak-to-peak output in Fig. 10-38?
10-4 All resistances are doubled in Fig. 10-38. What is the ac collector resistance?
10-5 All resistances are tripled in Fig. 10-38. What is the maximum peak-to-peak output?
Problems
410 Chapter 10 10-6 What is the dc collector resistance in Fig. 10-39?
What is the dc saturation current?
10-7 In Fig. 10-39, what is the ac collector resistance?
What is the ac saturation current?
10-8 What is the maximum peak-to-peak output in Fig. 10-39?
10-9 All resistances are doubled in Fig. 10-39. What is the ac collector resistance?
10-10 All resistances are tripled in Fig. 10-39. What is the maximum peak-to-peak output?
SEC. 10-3 CLASS-A OPERATION
10-11 An amplifi er has an input power of 4 mW and out- put power of 2 W. What is the power gain?
10-12 If an amplifi er has a peak-to-peak output voltage of 15 V across a load resistance of 1 kV, what is the power gain if the input power is 400 W?
10-13 What is the current drain in Fig. 10-38?
10-14 What is the dc power supplied to the amplifi er of Fig. 10-38?
10-15 The input signal of Fig. 10-38 is increased until maximum peak-to-peak output voltage is across the load resistor. What is the effi ciency?
10-16 What is the quiescent power dissipation in Fig. 10-38?
10-17 What is the current drain in Fig. 10-39?
10-18 What is the dc power supplied to the amplifi er of Fig. 10-39?
10-19 The input signal of Fig. 10-39 is increased until maximum peak-to-peak output voltage is across the load resistor. What is the effi ciency?
10-20 What is the quiescent power dissipation in Fig. 10-39?
10-21 If VBE 5 0.7 V in Fig. 10-40, what is the dc emitter current?
10-22 The speaker of Fig. 10-40 is equivalent to a load resistance of 3.2 V. If the voltage across the speaker is 5 Vp-p, what is the output power? What is the effi ciency of the stage?
SEC. 10-6 BIASING CLASS-B/AB AMPLIFIERS 10-23 The ac load line of a Class-B push-pull emitter follower has a cutoff voltage of 12 V. What is the maximum peak-to-peak voltage?
R2 470 Ω
RC 680 Ω R1
2 kΩ
vg 2 mV
RL 2.7 kΩ
RE 220 Ω RG
50 Ω
VCC +15 V
Figure 10-38
VCC +30 V
R2 100 Ω
RC 100 Ω R1
200 Ω
RE 68 Ω
RL 100 Ω
vin
Figure 10-39 Figure 10-40
vin RE
1 Ω R2
2.2 Ω R1 10 Ω
3.2-Ω SPEAKER +10 V
1000 mF
10-24 What is the maximum power dissipation of each transistor of Fig. 10-41?
10-25 What is the maximum output power in Fig. 10-41?
10-26 What is the quiescent collector current in Fig. 10-42?
10-27 In Fig. 10-42, what is the maximum effi ciency of the amplifi er?
10-28 If the biasing resistors of Fig. 10-42 are changed to 1 kV, what is the quiescent collector current? The effi ciency of the amplifi er?
SEC. 10-7 CLASS-B/AB DRIVERS
10-29 What is the maximum output power in Fig. 10-43?
10-30 In Fig. 10-43, what is the voltage gain of the preamp stage if 5 200?
10-31 If Q3 and Q4 have current gains of 200 in Fig. 10-43, what is the voltage gain of the driver stage?
10-32 What is the quiescent collector current in Fig. 10-43 of the power output stage?
10-33 What is the overall voltage gain for the three- stage amplifi er in Fig. 10-43?
SEC. 10-8 CLASS-C OPERATION
10-34 If the input voltage equals 5 Vrms in Fig. 10-44, what is the peak-to-peak input voltage?
If the dc voltage between the base and ground is measured, what will a DMM indicate?
10-35 What is the resonant frequency in Fig. 10-44?
10-36 If the inductance is doubled in Fig. 10-44, what is the resonant frequency?
10-37 What is the resonance in Fig. 10-44 if the capacitance C3 is changed to 100 pF?
SEC. 10-9 CLASS-C FORMULAS
10-38 If the Class-C amplifi er of Fig. 10-44 has an output power of 11 mW and an input power of 50 W, what is the power gain?
10-39 What is the output power in Fig. 10-44 if the output voltage is 50 Vp-p?
10-40 What is the maximum ac output power in Fig. 10-44?
10-41 If the current drain in Fig. 10-44 is 0.5 mA, what is the dc input power?
10-42 What is the effi ciency of Fig. 10-44 if the current drain is 0.4 mA and the output voltage is 30 Vp-p?
R1 10 kΩ
R3 1 kΩ
R5 12 kΩ
Preamp Driver Power Amp
R7 1 kΩ
RL 100 Ω
GND +15 V
Q3 +15.7 V
Q4 Q2
+1.43 V R8 100 Ω +14.3 V +2.13 V
R6 1 kΩ R4
1 kΩ +10 V Q1 +20 V +10.7 V
R2 5.6 kΩ
VCC +30 V
vin
Figure 10-43
R1 220 Ω
R3 220 Ω
RL 16 Ω R2
vin
VCC +30 V
Q1
Q2
Figure 10-41
R1 100 Ω
R2 100 Ω
RL vin 50 Ω
VCC +30 V
Q1
Q2
Figure 10-42
412 Chapter 10 10-43 If the Q of the inductor is 125 in Fig. 10-44, what is
the bandwidth of the amplifi er?
10-44 What is the worst-case transistor power dissipa- tion in Fig. 10-44 (Q 5 125)?
SEC. 10-10 TRANSISTOR POWER RATING 10-45 A 2N3904 is used in Fig. 10-44. If the circuit has to
operate over an ambient temperature range of 0 to 100°C, what is the maximum power rating of the transistor in the worst case?
10-46 A transistor has the derating curve shown in Fig. 10-34. What is the maximum power rating for an ambient temperature of 100°C?
10-47 The data sheet of a 2N3055 lists a power rating of 115 W for a case temperature of 25°C. If the der- ating factor is 0.657 W/°C, what is PD(max) when the case temperature is 90°C?
R1 10 kΩ
RL 10 kΩ vin
C1 0.1 mF
L1 1 mH C3
220 pF
VCC +30 V
C2
Figure 10-44
Critical Thinking
10-48 The output of an amplifi er is a square-wave output even though the input is a sine wave. What is the explanation?
10-49 A power transistor like the one in Fig. 10-36 is used in an amplifi er. Somebody tells you that since the case is grounded, you can safely touch the case. What do you think about this?
10-50 You are in a bookstore and you read the following in an electronics book: “Some power amplifi ers
can have an effi ciency of 125 percent.” Would you buy the book? Explain your answer.
10-51 Normally, the ac load line is more vertical than the dc load line. A couple of classmates say that they are willing to bet that they can draw a circuit whose ac load line is less vertical than the dc load line. Would you take the bet? Explain.
10-52 Draw the dc and ac load lines for Fig. 10-38.
Multisim Troubleshooting Problems
The Multisim troubleshooting fi les are found on the Instructor Resources section of Connect for Electronic Principles, in a folder named Multisim Troubleshooting Circuits (MTC). See page XVI for more details. For this chapter, the fi les are labeled MTC10-53 through MTC10-57 and are based on the circuit of Figure 10-43.
Open up and troubleshoot each of the respec- tive fi les. Take measurements to determine if there is a fault and, if so, determine the circuit fault.
10-53 Open up and troubleshoot fi le MTC10-53.
10-54 Open up and troubleshoot fi le MTC10-54.
10-55 Open up and troubleshoot fi le MTC10-55.
10-56 Open up and troubleshoot fi le MTC10-56.
10-57 Open up and troubleshoot fi le MTC10-57.
Digital/Analog Trainer System
The following questions, 10-58 through 10-62, are directed toward the schematic diagram of the Digital/Analog Trainer System found on the Instructor Resources section of Connect for Electronic Principles.
A full Instruction Manual for the Model XK-700 trainer can be found at www.elenco.com.
10-58 What type of circuit does the transistors Q1 and Q2 form?
10-59 What is the MPP output that could be measured at the junction of R46 and R47?
10-60 What is the purpose of diodes D16 and D17?
10-61 Using 0.7 V for the diode drops of D16 and D17, what is the approximate quiescent collector current for Q1 and Q2?
10-62 Without any ac input signal to the power amp, what is the normal dc voltage level at the junction of R46
and R47?
Job Interview Questions
1. Tell me about the three classes of amplifi er opera- tion. Illustrate the classes by drawing collector cur- rent waveforms.
2. Draw brief schematics showing the three types of coupling used between amplifi er stages.
3. Draw a VDB amplifi er. Then, draw its dc load line and ac load line. Assuming that the Q point is centered on the ac load lines, what is the ac saturation cur- rent? The ac cutoff voltage? The maximum peak-to- peak output?
4. Draw the circuit of a two-stage amplifi er and tell me how to calculate the total current drain on the supply.
5. Draw a Class-C tuned amplifi er. Tell me how to calcu- late the resonant frequency, and tell me what happens to the ac signal at the base. Explain how it is possible that the brief pulses of collector current produce a sine wave of voltage across the resonant tank circuit.
6. What is the most common application of a Class-C amplifi er? Could this type of amplifi er be used for an audio application? If not, why not?
7. Explain the purpose of heat sinks. Also, why do we put an insulating washer between the transistor and the heat sink?
8. What is meant by the duty cycle? How is it related to the power supplied by the source?
9. Defi ne Q.
10. Which class of amplifi er operation is most effi cient?
Why?
11. You have ordered a replacement transistor and heat sink. In the box with the heat sink is a package con- taining a white substance. What is it?
12. Comparing a Class-A amplifi er to a Class-C amplifi er, which has the greater fi delity? Why?
13. What type of amplifi er is used when only a small range of frequencies is to be amplifi ed?
14. What other types of amplifi ers are you familiar with?
Self-Test Answers
1. b 2. b 3. c 4. a 5. c 6. d 7. d 8. b 9. b 10. d 11. c 12. d
13. b 14. b 15. b 16. b 17. c 18. a 19. a 20. c 21. b 22. d 23. a 24. a
25. b 26. c 27. c 28. a 29. d 30. d 31. b 32. c 33. d 34. c 35. a
Practice Problem Answers
10-1 ICQ 5 100 mA;
VCEQ = 15 V 10-2 ic(sat) 5 350 mA;
VCE(cutoff ) 5 21 V;
MPP 5 12 V 10-3 Ap 5 1122
10-5 R 5 200 V
10-6 ICQ 5 331 mA;
VCEQ 5 6.7 V;
re 5 8 V 10-7 MPP 5 5.3 V 10-8 PD(max) 5 2.8 W;
Pout(max) 5 14 W 10-9 Effi ciency 5 63%
10-10 Effi ciency 5 78%
10-11 fr 5 4.76 MHz;
vout 5 24 Vp-p 10-13 PD 5 16.6 mW 10-14 PD(max) 5 425 mW
414 chapter
11 JFETs
The bipolar junction transistor (BJT) relies on two types of charge: free electrons and holes. This is why it is called bipolar:
the prefi x bi stands for “two.” This chapter discusses another kind of transistor called the fi eld-eff ect transistor (FET). This type of device is unipolar because its operation depends on only one type of charge, either free electrons or holes. In other words, an FET has majority carriers but not minority carriers.
For most linear applications, the BJT is the preferred device.
But there are some linear applications in which the FET is better suited because of its high input impedance and other properties.
Furthermore, the FET is the preferred device for most switching applications. Why? Because there are no minority carriers in an FET. As a result, it can switch off faster since no stored charge has to be removed from the junction area.
There are two kinds of unipolar transistors: JFETs and MOSFETs.
This chapter discusses the junction fi eld-eff ect transistor (JFET) and its applications. In Chapter 12, we discuss the metal-oxide semiconductor FET (MOSFET) and its applications.
© Eyewire/Getty Images
automatic gain control (AGC)
channel chopper
common-source (CS) amplifi er
current source bias drain
fi eld eff ect
fi eld-eff ect transistor (FET) gate
gate bias
gate-source cutoff voltage ohmic region
pinchoff voltage self-bias
series switch shunt switch source
source follower transconductance transconductance curve voltage-controlled device voltage-divider bias
Vocabulary
Objectives
After studying this chapter, you should be able to:
■ Describe the basic construction of a JFET.
■ Draw diagrams that show common biasing arrangements.
■ Identify and describe the signifi cant regions of JFET drain curves and transconductance curves.
■ Calculate the proportional pinchoff voltage and determine which region a JFET is
operating in.
■ Determine the dc operating point using ideal and graphical solutions.
■ Determine transconductance and use it to calculate gain in JFET amplifi ers.
■ Describe several JFET
applications, including switches, variable resistances, and choppers.
■ Test JFETs for proper operation.
Chapter Outline
11-1 Basic Ideas 11-2 Drain Curves
11-3 The Transconductance Curve
11-4 Biasing in the Ohmic Region 11-5 Biasing in the Active Region 11-6 Transconductance
11-7 JFET Amplifi ers
11-8 The JFET Analog Switch 11-9 Other JFET Applications 11-10 Reading Data Sheets 11-11 JFET Testing
416 Chapter 11
11-1 Basic Ideas
Figure 11-1a shows a piece of n-type semiconductor. The lower end is called the source, and the upper end is called the drain. The supply voltage VDD forces free electrons to fl ow from the source to the drain. To produce a JFET, a manufac- turer diffuses two areas of p-type semiconductor into the n-type semiconductor, as shown in Fig. 11-1b. These p regions are connected internally to get a single external gate lead.
Field Eff ect
Figure 11-2 shows the normal biasing voltages for a JFET. The drain supply volt- age is positive, and the gate supply voltage is negative. The term fi eld effect is related to the depletion layers around each p region. These depletion layers exist because free electrons diffuse from the n regions into the p regions. The recom- bination of free electrons and holes creates the depletion layers shown by the colored a reas.
Reverse Bias of Gate
In Fig. 11-2, the p-type gate and the n-type source form the gate-source diode.
With a JFET, we always reverse-bias the gate-source diode. Because of reverse bias, the gate current IG is approximately zero, which is equivalent to saying that the JFET has an almost infi nite input resistance.
GOOD TO KNOW
In general, JFETs are more temperature stable than bipolar transistors. Furthermore, JFETs are typically much smaller than bipolar transistors. This size dif- ference makes them particularly suitable for use in ICs, where the size of each component is critical.
VDD
(a) (b)
DRAIN
GATE
SOURCE
n
n
n
p p –
+
Figure 11-1 (a) Part of JFET; (b) single-gate JFET.
VDD DRAIN
GATE
SOURCE n
n
p p
VGG
– +
– +
Figure 11-2 Normal biasing of JFET.
A typical JFET has an input resistance in the hundreds of megohms. This is the big advantage that a JFET has over a bipolar transistor. It is the reason that JFETs excel in applications in which a high input impedance is required. One of the most important applications of the JFET is the source follower, a circuit like the emitter follower, except that the input impedance is in the hundreds of meg- ohms for lower frequencies.
Gate Voltage Controls Drain Current
In Fig. 11-2, electrons fl owing from the source to the drain must pass through the narrow channel between the depletion layers. When the gate voltage becomes more negative, the depletion layers expand and the conducting channel becomes narrower. The more negative the gate voltage, the smaller the current between the source and the drain.
The JFET is a voltage-controlled device because an input voltage con- trols an output current. In a JFET, the gate-to-source voltage VGS determines how much current fl ows between the source and the drain. When VGS is zero, maxi- mum drain current fl ows through the JFET. This is why a JFET is referred to as a normally on device. On the other hand, if VGS is negative enough, the depletion layers touch and the drain current is cut off.
Schematic Symbol
The JFET of Fig. 11-2 is an n-channel JFET because the channel between the source and the drain is an n-type semiconductor. Figure 11-3a shows the sche- matic symbol for an n-channel JFET. In many low-frequency applications, the source and the drain are interchangeable because you can use either end as the source and the other end as the drain.
The source and drain terminals are not interchangeable at high frequen- cies. Almost always, the manufacturer minimizes the internal capacitance on the drain side of the JFET. In other words, the capacitance between the gate and the drain is smaller than the capacitance between the gate and the source. You will learn more about internal capacitances and their effect on circuit action in a later chapter.
Figure 11-3b shows an alternative symbol for an n-channel JFET. This symbol with its offset gate is preferred by many engineers and technicians. The offset gate points to the source end of the device, a defi nite advantage in compli- cated multistage circuits.
There is also a p-channel JFET. The schematic symbol for a p-channel JFET, shown in Fig. 11-3c, is similar to that for the n-channel JFET, except that the gate arrow points in the opposite direction. The action of a p-channel JFET is complementary; that is, all voltages and currents are reversed. To reverse-bias a p-channel JFET, the gate is made positive in respect to the source. Therefore, VGS is made positive.
DRAIN
GATE
SOURCE (a)
DRAIN
GATE
SOURCE (b)
DRAIN
SOURCE GATE
(c)
Figure 11-3 (a) Schematic symbol; (b) off set-gate symbol; (c) p-channel symbol.
GOOD TO KNOW
The depletion layers are actu- ally wider near the top of the p-type materials and narrower at the bottom. The reason for the change in the width can be understood by realizing that the drain current ID will produce a voltage drop along the length of the channel. With respect to the source, a more positive voltage is present as you move up the channel toward the drain end. Since the width of a deple- tion layer is proportional to the amount of reverse-bias voltage, the depletion layer of the pn junction must be wider at the top, where the amount of reverse-bias voltage is greater.
418 Chapter 11
11-2 Drain Curves
Figure 11-4a shows a JFET with normal biasing voltages. In this circuit, the gate-source voltage VGS equals the gate supply voltage VGG, and the drain-source voltage VDS equals the drain supply voltage VDD.
Maximum Drain Current
If we short the gate to the source, as shown in Fig. 11-4b, we will get maximum drain current because VGS 5 0. Figure 11-4c shows the graph of drain current ID versus drain-source voltage VDS for this shorted-gate condition. Notice how the drain current increases rapidly and then becomes almost horizontal when VDS is greater than VP.
Example 11-1
A 2N5486 JFET has a gate current of 1 nA when the reverse gate voltage is 20 V.
What is the input resistance of this JFET?
SOLUTION Use Ohm’s law to calculate:
Rin 5 20 V _____
1 nA 5 20,000 MV
PRACTICE PROBLEM 11-1 In Example 11-1, calculate the input resist- ance if the JFET’s gate current is 2 nA.
VGG
VGS
VDS
ID
IDSS
VDS VDS(max)
Vp –
+ +
– VDD
(a)
(c)
VDS +
– VDD
(b)
SHORTED GATE
ACTIVE REGION –
+
– +
– +
Figure 11-4 (a) Normal bias; (b) zero gate voltage; (c) shorted gate drain current.
GOOD TO KNOW
The pinchoff voltage VP is the point at which further increases in VDS are offset by a propor- tional increase in the channel’s resistance. This means that if the channel resistance is increasing in direct proportion to VDS above VP, ID must remain the same above VP.
Why does the drain current become almost constant? When VDS in- creases, the depletion layers expand. When VDS 5 VP, the depletion layers are almost touching. The narrow conducting channel therefore pinches off or prevents a further increase in current. This is why the current has an upper limit of IDSS.
The active region of a JFET is between VP and VDS(max). The minimum voltage VP is called the pinchoff voltage, and the maximum voltage VDS(max) is the breakdown voltage. Between pinchoff and breakdown, the JFET acts like a current source of approximately IDSS when VGS 5 0.
IDSS stands for the current drain to source with a shorted gate. This is the maximum drain current a JFET can produce. The data sheet of any JFET lists the value of IDSS. This is one of the most important JFET quantities, and you should always look for it fi rst because it is the upper limit on the JFET current.
The Ohmic Region
In Fig. 11-5, the pinchoff voltage separates two major operating regions of the JFET. The almost-horizontal region is the active region. The almost-vertical part of the drain curve below pinchoff is called the ohmic region.
When operated in the ohmic region, a JFET is equivalent to a resistor with a value of approximately:
RDS 5 ____ IVDSSP (11-1) RDS is called the ohmic resistance of the JFET. In Fig. 11-5, VP 5 4 V and IDSS 5 10 mA. Therefore, the ohmic resistance is:
RDS 5 ______4 V
10 mA 5 400 V
If the JFET is operating anywhere in the ohmic region, it has an ohmic resistance of 400 V.
Gate Cutoff Voltage
Figure 11-5 shows the drain curves for a JFET with an IDSS of 10 mA. The top curve is always for VGS 5 0, the shorted-gate condition. In this example, the pinchoff voltage is 4 V and the breakdown voltage is 30 V. The next curve down is for VGS 5 21 V, the next for VGS 5 22 V, and so on. As you can see, the more negative the gate-source voltage, the smaller the drain current.
ID
VDS VGS = 0
Vp = 4 V 5.62 mA
2.5 mA 0.625 mA 10 mA
4 15 30
VGS = –1 VGS = –2
VGS = –3 VGS = –4
Figure 11-5 Drain curves.