ideal,90. However, an increased noise sensitivity also appears, as indicated by the gain increase of about 20 dB at 500 Hz.
So whenais larger, the phase advance added by differentiation increases; unfortu- nately, the function is also more noise sensitive. However, this noise susceptibility can be offset by using more highly resolved feedback or by otherwise reducing noise sources in the system.
5.6.2.2 Experiment 5B: Inverse Trapezoidal Differentiation
Experiment 5B, shown in Figure 5-9, demonstrates the frequency-domain performance of inverse trapezoidal differentiation. An adjustable-frequency sine wave similar to that in Experiment 5A is provided. The signal proceeds through the DSA and then is sampled and held. Inverse trapezoidal differentiation is provided through the block
``d/dt.'' Note that this block is similar in appearance to simple differences (see Experiment 4A) except that the symbolDis replaced with a rhombus and the parameterais accepted along the top edge. In Experiment 5B,a is set with a Live Constant. The Live Scope displays the input (amplitude1) against the differentiated signal (amplitude 600);
the differentiated signal leads the input by 90. Note that the input scale is 200 units/div to account for the gain of differentiation at 100 Hz, which is2p100628.
Load Experiment 5B and start the model running. Double-click on the DSA to get the DSA output screen to appear. Press GO on the DSA to produce a Bode plot.
Adjust theLive Constant ato different values and take new Bode plots. Notice that as a increases from 0 (Euler's method) to 1, the phase lag in the higher frequencies improves but the noise sensitivity increases. This is the behavior of the transfer functionT(z) from Equation 5.28.
Correctly applied, inverse trapezoidal can signi®cantly reduce phase lag in the loop.
For example, return to Experiment 4A and replace the simple difference block with inverse trapezoidal differentiation and notice that the proportional gain, KP, can be
Figure 5-9.Experiment 5B: Inverse trapezoidal differentiation.
increased by about 25% when a is set to 0.90. Be aware, however, that this model is essentially noiseless and that noise is the primary disadvantage of inverse trapezoidal differentiation. If the signal being differentiated is noisy enough to require a ®lter to be placed in the loop, the bene®t of inverse trapezoidal differentiation may be lost. For this reason, the bene®ts of the method will be more easily gained with low-noise input signals.
5.6.3 Sample-and-Hold
Digital controllers calculate outputs once each cycle. That output is stored, often in a D/A (digital-to-analog) converter, and then held constant until the next cycle. This function, sample (output to D/A)-and-hold (keep constant for one cycle), is rare in analog systems but present in virtually all digital systems.
The effect of holding the output constant introduces phase lag because the output is getting old from the time it is stored. By the end of the cycle, the output is a full cycle old.
As discussed in Section 4.2.1, since the data is, on average, one-half cycle old, the sample- and-hold (S/H) acts like a delay of a half-cycle. That is, in fact, an excellent approximation:
TS=H z e sT=21 oT=2rad 5:30
or, in degrees and Hz,
TS=H s 1 180FT 5:31
At higher frequencies, the S/H also begins attenuating the input somewhat. The more exact transfer function for S/H is
TS=H z z 1 Tz 1
s 5:32
which turns out to be digital differentiation cascaded with analog integration. This form is shown as a zero-order hold in Ref. 33, although the Tis not included. Few textbooks include the T, although it is required to re¯ect the sample-and-hold's intrinsic unity DC gain.
Recognizing thatzesT, some algebra can provide Equation 5.32 in a simpler form for sinusoidal excitation:
TS=H z z 1 Tz 1
s
esT 1 esT 1
Ts
esT=2 e sT=2 esT=2
1 Ts
5.6 FUNCTIONS FOR DIGITAL SYSTEMS 385
To apply steady-state sinusoids, setsjo: TS=H z ejoT=2 e joT=2
ejoT=2 1
Tjo
e joT=2ejoT=2 e joT=2 2j oT=2
e joT=2sin oT=2
oT=2
sin oT=2
oT=2
oT=2rad
5:33
So the precise sample-and-hold (Equation 5.33) and the approximations presented in Equations 5.30 and 5.31 (and Equation 4.1) have the same phase lag ( oT/2 radians) but different gains. The gain, sin (oT/2)/(oT/2), also known as the sync function, is nearly unity for most frequencies of interest. For example, at one-fourth the sample frequency (o2p/4T), the sync function evaluates to 0.9, or about 1dB, which is a value so close to 0 dB that the difference can usually be ignored. And recognizing that the system bandwidth will usually be at much lower frequencies, say, 1/10 the sample frequency, there is rarely interest in the precise gain at so high a frequency. Even at the Nyquist frequency, the sync function evaluates to 0.637, or 4dB, a value that can often be ignored, considering that this is the highest frequency the system can process. This is why the simpler forms (Equations 4.1, 5.30, and 5.31) are suf®ciently accurate to use in most controls problems.
5.6.4 DAC/ADC: Converting to and from Analog
Computers process digital values. An analog-to-digital converter (ADC) converts a voltage to an integer, where the value of the integer is proportional to the amount of voltage. For example, suppose you are using a 12-bit ADC that converts up to 8 V.
The range of voltages is 0 to 8 V and the range of integers is 0 to 4095 (212 1) counts.
The simple model of the ADC is a constant of proportionality:
TADC z 4095counts
8:0V 511:9counts
V 5:34
Similarly, a digital-to-analog converter (DAC) converts integers to voltages. For example, the constant of proportionality for a 0 to 10 V, 10-bit DAC is
TDAC z 10:0V
1023counts0:0978 V
count 5:35
A sample-and-hold is an implicit part of the output DAC. That is, a DAC can be modeled with two sections:a constant in volts per count and an S/H. So a common model for a DAC is
TDAC z 0:0978 oT 2
V
count 5:36
DACs and ADCs also can convert to and from signed voltages. For example, an 8-bit DAC may output5V. The model for this DAC is
TDAC z 5:0 5:0V 255counts oT
2
0:0392 oT 2
V
count 5:37
In general, the model for DACs and ADCs is the ratio of the integer range to the voltage range. In this text, the sample-and-hold is shown as part of the DAC. How- ever, when studying the effects of phase lag on stability, the sample-and-hold can be placed elsewhere in the loop, with little impact.