General exception vector (offset 0x180)
4.7 Exception Handling and Servicing Flowcharts
The remainder of this chapter contains flowcharts for the following exceptions and guidelines for their handlers:
• General exceptions and their exception handler
• TLB miss exceptions and their exception handler (4Kc core)
• Reset, soft reset and NMI exceptions, and a guideline to their handler
• Debug exceptions
Generally speaking, the exceptions are handled by hardware (HW); the exceptions are then serviced by software (SW).
Note that unexpected debug exceptions to the debug exception vector at 0xBFC0_0200 may be viewed as a reserved instruction since uncontrolled execution of a SDBBP instruction caused the exception. The DERET instruction must be used at return from the debug exception handler, in order to leave debug mode and return to non-debug mode. The DERET instruction returns to the address in the DEPC register.
Figure 4-1 General Exception Handler (HW) To General Exception Servicing Guidelines
=1 (bootstrap)
=0 (normal)
Status.BEV To General Exception Servicing Guidelines
Comments
PC <- 0x8000_0000 + 180 (unmapped, cached)
PC <- 0xBFC0_0200 + 180 (unmapped, uncached) EXL <- 1
EPC <- (PC - 4)
Cause.BD <- 1 EPC <- PC
Cause.BD <- 0 Instr. in
Br.Dly. Slot?
=0
Processor forced to Kernel Mode & interrupt disabled
=0
=1 Check if exception within
another exception EXL
EntryHi and Context are set only for TLB Invalid, Modified, & Refill exceptions (4Kc core only). BadVA is set only for TLB Invalid, Modified, and Refill exceptions (4Kc core only). Note: not set on Bus Errors.
EntryHi <- VPN2, ASID Context <- VPN2 SetCause EXCCode,CE
BadVA <- VA
Exceptions other than Reset, Soft Reset, NMI, or first-level TLB miss (4Kc core only). Note: Interrupts can be masked by IE or IMs, and Watch is masked if EXL = 1.
4.7 Exception Handling and Servicing Flowcharts
Figure 4-2 General Exception Servicing Guidelines (SW) ERET
MTC0 - EPC,STATUS
EXL = 1 Service Code
* ERET is not allowed in the branch delay slot of another Jump Instruction
* Processor does not execute the instruction which is in the ERET’s branch delay slot
* PC <-EPC; EXL <- 0
* LLbit <- 0 Check Cause value & Jump to
appropriate Service Code
* After EXL=0, all exceptions allowed.
(except interrupt if masked by IE) (Optional - only to enable Interrupts while keeping
Kernel Mode) MTC0 -
SetStatus bits:
UM <- 0, EXL <-0, IE<-1 MFC0 -
Context, EPC, Status, Cause
* Unmapped vector so TLBMod, TLBInv, or TLB Refill exceptions not possible (4Kc core only)
* EXL=1 so Watch, Interrupt exceptions disabled
* OS/System to avoid all other exceptions
* Only Reset, Soft Reset, NMI exceptions possible Comments
Figure 4-3 TLB Miss Exception Handler (HW) — 4Kc Core only To TLB Exception Servicing Guidelines
Vec. Off. = 0x180 EPC <- (PC - 4)
Cause.BD <- 1
EPC <- PC Cause.BD <- 0
Vec. Off. = 0x000
EXL <- 1
Points to General Exception Processor forced to Kernel
Mode & interrupt disabled
= 0
= 1 (bootstrap)
= 0 (normal)
PC <- 0x8000_0000 + Vec.Off.(unmapped. cached)
PC <- 0xBFC0_0200 + Vec.Off.(unmapped. uncached) Status.BEV
Check if exception within another exception
= 1
= 1
= 0
EXL EXL
EntryHi <- VPN2, ASID Context <- VPN2 SetCause EXCCode,CE
BadVA <- VA
Instr. in Br.Dly. Slot?
no yes
4.7 Exception Handling and Servicing Flowcharts
Figure 4-4 TLB Exception Servicing Guidelines (SW) — 4Kc Core only Comments
ERET Service Code MFC0 -CONTEXT
* Unmapped vector so TLBMod, TLBInv, or TLB Refill exceptions not possible
* EXL=1 so Watch, Interrupt exceptions disabled
* OS/System to avoid all other exceptions
* Only Reset, Soft Reset, NMI exceptions possible
* Load the mapping of the virtual address inContext Reg. Move it toEntryLo and write into the TLB
* There could be a TLB miss again during the mapping of the data or instruction address. The processor will jump to the general exception vector since the EXL is 1. (Option to complete the first level refill in the general exception handler or ERET to the original instruction and take the exception again)
* ERET is not allowed in the branch delay slot of another Jump Instruction
* Processor does not execute the instruction which is in the ERET’s branch delay slot
* PC <-EPC; EXL <- 0
* LLbit <- 0
Figure 4-5 Reset, Soft Reset and NMI Exception Handling and Servicing Guidelines
Status:
BEV <- 1 TS <- 0 SR <- 1/0 NMI <- 0/1 ERL <- 1
(Optional)
Reset Service Code Soft Reset Service Code
NMI Service Code
ERET
=0
=1
=0
=1
Status.SR Status.NMI PC <- 0xBFC0_0000
ErrorEPC <- PC
Random <- TLBENTRIES - 1 (4Kc core only) Wired <- 0 (4Kc core only)
Config <- Reset state Status:
RP <- 0 BEV <- 1 TS <- 0 SR <- 0 NMI <- 0 ERL <- 1 WatchLo:
I,R,W <- 0
Reset Exception Soft Reset or NMI Exception
Reset, Soft Reset & NMI Exception Handling (HW)Reset,SoftReset&NMIServicing Guidelines (SW)