9.3 Test Access Port (TAP)
9.3.2 Test Access Port Operation
The TAP controller is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These two inputs determine whether an the Instruction register scan or data register scan is performed. The TAP consists of a small controller, driven by the TCK input, which responds to the TMS input as shown in the state diagram inFigure 9-5. The TAP uses both clock edges of TCK. TMS and TDI are sampled on the rising edge of TCK, while TDO changes on the falling edge of TCK.
At power-up the TAP is forced into the Test-Logic-Reset either by low value on TRST_N. The TAP instruction register is thereby reset to IDCODE. No other parts of the EJTAG hardware are reset through the Test-Logic-Reset state.
When test access is required, a protocol is applied via the TMS and TCK inputs, causing the TAP to exit the
Test-Logic-Reset state and move through the appropriate states. From the Run-Test/Idle state, an Instruction register scan or a data register scan can be issued to transition the TAP through the appropriate states shown inFigure 9-5.
The states of the data and instruction register scan blocks are mirror images of each other adding symmetry to the protocol sequences. The first action that occurs when either block is entered is a capture operation. For the data registers, the Capture-DR state is used to capture (or parallel load) the data into the selected serial data path. In the Instruction register, the Capture-IR state is used to capture status information into the Instruction register.
From the Capture states, the TAP transitions to either the Shift or Exit1 states. Normally the Shift state follows the Capture state so that test data or status information can be shifted out for inspection and new data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via Exit1. The reason for entering the Pause state is to temporarily suspend the shifting of data through either the Data or Instruction Register while a required operation, such as refilling a host memory buffer, is performed. From the Pause state shifting can resume by re-entering the Shift state via the Exit2 state or terminated by entering the Run-Test/Idle state via the Exit2 and Update states.
Upon entering the data or Instruction register scan blocks, shadow latches in the selected scan path are forced to hold their present state during the Capture and Shift operations. The data being shifted into the selected scan path is not output through the shadow latch until the TAP enters the Update-DR or Update-IR state. The Update state causes the shadow latches to update (or parallel load) with the new data that has been shifted into the selected scan path.
TRST_N I
Test Reset Input (Optional pin)
The TRST_N pin is an active-low signal for asynchronous reset of the TAP controller and instruction in the TAP module, independent of the processor logic. The processor is not reset by the assertion of TRST_N.
The core signal for this is called EJ_TRST_N
This signal is optional, but power-on reset must apply a low pulse on this is signal at power-on and then leave it high, in case the signal is not available as a pin on the chip. If available on the chip, then it must be low on the board when the EJTAG debug features are unused by the probe.
Table 9-19 EJTAG Interface Pins (Continued)
Pin Type Description
Figure 9-5 TAP Controller State Diagram 9.3.2.1 Test-Logic-Reset State
In the Test-Logic-Reset state the boundary scan test logic is disabled. The test logic enters the Test-Logic-Reset state when the TMS input is held HIGH for at least five rising edges of TCK. The BYPASS instruction is forced into the instruction register output latches during this state. The controller remains in the Test-Logic-Reset state as long as TMS is HIGH.
9.3.2.2 Run-Test/Idle State
The controller enters the Run-Test/Idle state between scan operations. The controller remains in this state as long as TMS is held LOW. The instruction register and all test data registers retain their previous state. The instruction cannot change when the TAP controller is in this state.
When TMS is sampled HIGH at the rising edge of TCK, the controller transitions to the Select_DR state.
9.3.2.3 Select_DR_Scan State
This is a temporary controller state in which all test data registers selected by the current instruction retain their previous state. If TMS is sampled LOW at the rising edge of TCK, the controller transitions to the Capture_DR state. A HIGH on TMS causes the controller to transition to the Select_IR state. The instruction cannot change while the TAP controller is in this state.
9.3.2.4 Select_IR_Scan State
This is a temporary controller state in which all test data registers selected by the current instruction retain their previous state. If TMS is sampled LOW at the rising edge of TCK, the controller transitions to the Capture_IR state. A HIGH on TMS causes the controller to transition to the Test-Reset-Logic state. The instruction cannot change while the TAP controller is in this state.
Shift_IR Select_IR_Scan
Capture_IR
Exit1_IR
Pause_IR
Exit2_IR
Update_IR 1
0
0
0
0
0
0 1
1
1 1
1
1
1
0
Shift_DR Select_DR_Scan
Capture_DR
Exit1_DR Pause_DR
Exit2_DR Update_DR
0
0
0
0
0
0 1
1
1 1
1
1
1
0
Test-Logic-Reset Run-Test/Idle
0 1
0
9.3 Test Access Port (TAP) 9.3.2.5 Capture_DR State
In this state the boundary scan register captures value of the register addressed by the Instruction register, and the value is then shifted out in the Shift_DR. If TMS is sampled LOW at the rising edge of TCK, the controller transitions to the Shift_DR state. A HIGH on TMS causes the controller to transition to the Exit1_DR state. The instruction cannot change while the TAP controller is in this state.
9.3.2.6 Shift_DR State
In this state the test data register connected between TDI and TDO as a result of the current instruction shifts data one stage toward its serial output on the rising edge of TCK. If TMS is sampled LOW at the rising edge of TCK, the controller remains in the Shift_DR state. A HIGH on TMS causes the controller to transition to the Exit1_DR state. The instruction cannot change while the TAP controller is in this state.
9.3.2.7 Exit1_DR State
This is a temporary controller state in which all test data registers selected by the current instruction retain their previous state. If TMS is sampled LOW at the rising edge of TCK, the controller transitions to the Pause_DR state. A HIGH on TMS causes the controller to transition to the Update_DR state which terminates the scanning process. The instruction cannot change while the TAP controller is in this state.
9.3.2.8 Pause_DR State
The Pause_DR state allows the controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO. All test data registers selected by the current instruction retain their previous state. If TMS is sampled LOW at the rising edge of TCK, the controller remains in the Pause_DR state. A HIGH on TMS causes the controller to transition to the Exit2_DR state. The instruction cannot change while the TAP controller is in this state.
9.3.2.9 Exit2_DR State
This is a temporary controller state in which all test data registers selected by the current instruction retain their previous state. If TMS is sampled LOW at the rising edge of TCK, the controller transitions to the Shift_DR state to allow another serial shift of data. A HIGH on TMS causes the controller to transition to the Update_DR state which terminates the scanning process. The instruction cannot change while the TAP controller is in this state.
9.3.2.10 Update_DR State
When the TAP controller is in this state the value shifted in during the Shift_DR state takes effect at the rising edge of the TCK for the register indicated by the Instruction register.
If TMS is sampled LOW at the rising edge of TCK, the controller transitions to the Run-Test/Idle state. A HIGH on TMS causes the controller to transition to the Select_DR_Scan state. The instruction cannot change while the TAP controller is in this state and all shift register stages in the test data registers selected by the current instruction retain their previous state.
9.3.2.11 Capture_IR State
In this state the shift register contained in the Instruction register loads a fixed pattern (000012) on the rising edge of TCK. The data registers selected by the current instruction retain their previous state.
If TMS is sampled LOW at the rising edge of TCK, the controller transitions to the Shift_IR state. A HIGH on TMS causes the controller to transition to the Exit1_IR state. The instruction cannot change while the TAP controller is in this state.
9.3.2.12 Shift_IR State
In this state the instruction register is connected between TDI and TDO and shifts data one stage toward its serial output on the rising edge of TCK. If TMS is sampled LOW at the rising edge of TCK, the controller remains in the Shift_IR state.
A HIGH on TMS causes the controller to transition to the Exit1_IR state.
9.3.2.13 Exit1_IR State
This is a temporary controller state in which all registers retain their previous state. If TMS is sampled LOW at the rising edge of TCK, the controller transitions to the Pause_IR state. A HIGH on TMS causes the controller to transition to the Update_IR state which terminates the scanning process. The instruction cannot change while the TAP controller is in this state and the instruction register retains its previous state.
9.3.2.14 Pause_IR State
The Pause_IR state allows the controller to temporarily halt the shifting of data through the instruction register in the serial path between TDI and TDO. If TMS is sampled LOW at the rising edge of TCK, the controller remains in the Pause_IR state. A HIGH on TMS causes the controller to transition to the Exit2_IR state. The instruction cannot change while the TAP controller is in this state.
9.3.2.15 Exit2_IR State
This is a temporary controller state in which the instruction register retains its previous state. If TMS is sampled LOW at the rising edge of TCK, the controller transitions to the Shift_IR state to allow another serial shift of data. A HIGH on TMS causes the controller to transition to the Update_IR state which terminates the scanning process. The instruction cannot change while the TAP controller is in this state.
9.3.2.16 Update_IR State
The instruction shifted into the instruction register takes effect on the rising edge of TCK.
If TMS is sampled LOW at the rising edge of TCK, the controller transitions to the Run-Test/Idle state. A HIGH on TMS causes the controller to transition to the Select_DR_Scan state.