cisc and risc in computer organization and architecture

... ACK’s receiving the data • Buffer in I/O module compensates for speed differences • Point-to-Point and Multipoint Configurations o Point-to-point interface § provides a dedicated line between ... execution, waiting for some system resource o Halted - the process has terminated and will be destroyed by the operating system • Memory Pointers - starting and ending points of the process in memory ... beginning of program o Organizational support in the CPU for partitioning § base address register § limit register • Paging o Extends partition idea by dividing up both memory and processes into

Ngày tải lên: 14/08/2014, 20:21

... IEEE Standard for Floating Point Arithmetic o Infinity § Most operations involving infinity yield infinity § Signs obey usual laws § -infinity -infinity yields -infinity and +infinity +infinity ... + infinity and -infinity § Result is rounded up toward positive infinity or Result is rounded down toward negative infinity § Useful in implementing interval arithmetic * every calculation in ... of interrupt routine (so next instruction cycle will begin by fetching appropriate instruction) Instruction Pipelining (11.4) • Concept is similar to a manufacturing assembly line o Products at

Ngày tải lên: 14/08/2014, 20:21

... Stallings Computer Organization and Architecture 7th Edition Chapter 18 Parallel Processing Trang 2Multiple Processor Organization• Single instruction, single data stream - Trang 3Single Instruction, ... Single Data Stream - SISD• Single processor • Single instruction stream • Data stored in single memory • Uni-processor Trang 4Single Instruction, Multiple Data Stream - SIMD • Single machine instruction ... per cycle • Increase performance by increasing clock frequency and increasing instructions that complete during cycle • May be reaching limit — Complexity Trang 37Multithreading and Chip Multiprocessors•

Ngày tải lên: 30/11/2016, 22:13

... Trang 1William Stallings Computer Organization and Architecture 6th Edition Chapter 15 IA-64 Architecture Trang 4Superscalar v IA-64Trang 5Why New Architecture?Trang 7General OrganizationTrang ... Large number of registers —IA­64 instruction format assumes 256 – 128 * 64 bit integer, logical & general purpose– 128 * 82 bit floating point and graphic Trang 9IA-64 Execution UnitsTrang 10Instruction Format ... Detail• Completes 5 iterations in 7 cycles —Compared with 20 cycles in original code • Assumes two memory ports —Load and store can be done in parallel Trang 20Software Pipeline Example DiagramTrang

Ngày tải lên: 30/01/2020, 00:03

... Stallings Computer Organization and Architecture 6th Edition Chapter 4 Cache Memory Trang 3• CPU • Internal • External Trang 9Memory Hierarchy - DiagramTrang 13• Physical arrangement of bits into words ... Mapping SummaryTrang 36Set Associative MappingTrang 37Set Associative MappingTrang 38Two Way Set Associative Cache OrganizationTrang 39Set Associative MappingTrang 40Two Way Set Associative Mapping ... OrganizationTrang 28Direct Mapping ExampleTrang 29Direct Mapping SummaryTrang 30Direct Mapping pros & consTrang 32Fully Associative Cache OrganizationTrang 33Associative Mapping ExampleTrang 34Tag   22 bit

Ngày tải lên: 30/01/2020, 00:03

... 1William Stallings Computer Organization and Architecture 6th Edition Chapter 9 Computer Arithmetic Trang 2Arithmetic & Logic Unit• Does the calculations • Everything else in the computer is there to service this unit ... Everything else in the computer is there to service this unit • Handles integers • May handle floating point (real) numbers • May be separate FPU (maths co­processor) • May be on chip separate FPU (486DX +) Trang 3ALU Inputs and OutputsTrang ... Unsigned Binary Integers 1011 00001101 10010011 1011 001110 1011 1011 100 Quotient Dividend Remainder Partial Remainders Divisor Trang 25Flowchart for Unsigned Binary DivisionTrang 28Floating Point

Ngày tải lên: 30/01/2020, 00:07

... Stallings Computer Organization and Architecture 6th Edition Chapter 5 Internal Memory Trang 2Semiconductor Memory TypesTrang 4Memory Cell OperationTrang 6Dynamic RAM StructureTrang 9Stating RAM ... Adding one more pin doubles range of values so x4 capacityTrang 16Typical 16 Mb DRAM (4M x 4)Trang 17PackagingTrang 18Module Organization Trang 19Module Organization (2)Trang 21Error Correcting ... Organization Trang 19Module Organization (2)Trang 21Error Correcting Code FunctionTrang 22Advanced DRAM OrganizationTrang 23Synchronous DRAM (SDRAM)Trang 24IBM 64Mb SDRAMTrang 25SDRAM OperationTrang 27RAMBUS

Ngày tải lên: 30/01/2020, 01:38

... 1William Stallings Computer Organization and Architecture Trang 2What is an instruction set?Trang 4Where have all the Operands gone?Trang 5Instruction Cycle State DiagramTrang 7Simple Instruction ... 19Pentium Floating Point Data TypesTrang 20PowerPC Data Types• Floating point —IEEE 754 —Single or double precision Trang 24Shift and Rotate OperationsTrang 25• Bitwise operations • AND, OR, NOT ... Trang 26• E.g. Binary to Decimal Trang 30Branch InstructionTrang 31Nested Procedure CallsTrang 32Use of StackTrang 33Exercise For Reader• Find out about instruction set for Pentium and  PowerPC

Ngày tải lên: 30/01/2020, 02:23

... Stallings Computer Organization and Architecture 6th Edition Chapter 18 Parallel Processing Trang 2Multiple Processor Organization• Single instruction, single data stream ­ SISD • Single instruction, multiple data stream ­ SIMD ... • Multiple instruction, single data stream ­ MISD • Multiple instruction, multiple data stream­ MIMD Trang 3Single Instruction, Single Data Stream - SISD• Single processor • Single instruction stream ... Single instruction stream • Data stored in single memory • Uni­processor Trang 4Single Instruction, Multiple Data Stream - SIMDTrang 5Multiple Instruction, Single Data Stream - MISDTrang 6Multiple Instruction, Multiple

Ngày tải lên: 30/01/2020, 03:38

... 1William Stallings Computer Organization and Architecture 6th Edition Chapter 13 Reduced Instruction Set Computers Trang 2Major Advances in Computers(1)Trang 3Major Advances in Computers(2)Trang ... Trang 23Referencing a Scalar - Window Based Register File Trang 24Referencing a Scalar - CacheTrang 25Compiler Based Register OptimizationTrang 27Graph Coloring ApproachTrang 31RISC v CISC• Not clear cut ... Step - RISCTrang 5Comparison of processorsTrang 6Driving force for CISCTrang 10Relative Dynamic FrequencyTrang 14Large Register FileTrang 15Registers for Local VariablesTrang 17Register Windows

Ngày tải lên: 30/01/2020, 04:03

... Stallings Computer Organization and Architecture 6th Edition Chapter 8 Operating System Support Trang 2Objectives and Functions• Convenience —Making the computer easier to use • Efficiency —Allowing better use of computer resources ... Allow users to interact directly with the computer —i.e. Interactive • Multi­programming allows a number of users to  interact with the computer Trang 19Long Term SchedulingTrang 20Medium Term SchedulingTrang ... —Allowing better use of computer resources Trang 3Layers and Views of a Computer SystemTrang 4Operating System ServicesTrang 5O/S as a Resource ManagerTrang 6Types of Operating System• Interactive • Batch • Single program (Uni­programming)

Ngày tải lên: 30/01/2020, 04:16

... identify the module issuing the interrupt? § How you deal with multiple interrupts? • i.e an interrupt handler being interrupted Identifying Interrupting Module (1) § Different line for each module ... IRQ7 8086 INTR ISA Bus Interrupt System § ISA bus chains two 8259As together § Link is via interrupt § Gives 15 lines • 16 lines less one for link § IRQ is used to re-route anything trying to use ... module in turn • Slow • Priority is established by the order in which module are polled Identifying Interrupting Module (2) § Daisy Chain or Hardware poll • Interrupt Acknowledge sent down a chain...

Ngày tải lên: 05/11/2013, 22:15

... re-linking and re-loading § Lends itself to sharing among processes § Lends itself to protection § Some systems combine segmentation with paging Required Reading § Stallings chapter § Stallings, ... Error detection and response Accounting O/S as a Resource Manager Types of Operating System § § § § Interactive Batch Single program (Uni-programming) Multi-programming (Multi-tasking) Early Systems ... I/O § Interrupts • Allows for relinquishing and regaining control Multi-programmed Batch Systems § I/O devices very slow § When one program is waiting for I/O, another can use the CPU Single...

Ngày tải lên: 12/12/2013, 09:15

... Moterola 680x0 (Mac), and most RISC are big-endian § Internet is big-endian • Makes writing Internet programs on PC more awkward! • WinSock provides htoi and itoh (Host to Internet & Internet to Host) ... Divide Signed Integer Floating point ? May include • Increment (a++) • Decrement (a ) • Negate (-a) Logical § Bitwise operations § AND, OR, NOT Conversion § E.g Binary to Decimal Input/Output ... arbitrary binary contents Integer - single binary value Ordinal - unsigned integer Unpacked BCD - One digit per byte Packed BCD - BCD digits per byte Near Pointer - 32 bit offset within segment...

Ngày tải lên: 12/12/2013, 09:15

... to find operand § Hence slower Indirect Addressing Diagram Instruction Opcode Address A Memory Pointer to operand Operand Register Addressing (1) § § § § § Operand is held in register named in ... Operand Indirect Addressing (1) § Memory cell pointed to by address field contains the address of (pointer to) the operand § EA = (A) • Look in A, find address (A) and look there for operand ... programming or compiler writing • N.B C programming ü register int a; § c.f Direct addressing § § § § Register Addressing Diagram Instruction Opcode Register Address R Registers Operand Register Indirect...

Ngày tải lên: 12/12/2013, 09:15

... loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be fetched Data Flow (Interrupt Diagram) Prefetch § § § § Fetch accessing main memory Execution ... instruction Decode instruction Calculate operands (i.e EAs) Fetch operands Execute instructions Write result § Overlap these operations Timing of Pipeline Branch in a Pipeline Dealing with Branches ... pointing to: • Process control blocks (see O/S) • Interrupt Vectors (see O/S) § N.B CPU design and operating system design are closely linked Example Register Organizations Foreground Reading...

Ngày tải lên: 12/12/2013, 09:15

... points Example of supporting line for two convex hulls Partitioning a set of points using four extreme points Angles among points and the Points in labeled with Illustration of contact points and ... Proximity indexing Euler tour of a tree Preorder-inorder traversal Merging preorder and inorder traversals Finding distances in a directed graph List ranking with a balanced subset Embedding a list in ... configuration and graph Broadcasting on an R-Mesh Permutation routing Adding bits addition on an R-Mesh Examples of and Neighbor localization example Chain sorting Concatenating lists in chain sorting...

Ngày tải lên: 01/06/2014, 07:46

... Network Outline of the Book (1) • • • • • • • • Computer Evolution and Performance Computer Interconnection Structures Internal Memory External Memory Input/Output Operating Systems Support Computer ... CPU CPU Computer Arithmetic and Login Unit Registers I/O System Bus Memory CPU Internal CPU Interconnection Control Unit Structure - The Control Unit Control Unit CPU Sequencing Login ALU Internal ... smart devices or other computers Control • Something needs to monitor operation and maintain control of data processing, data storage, and data movement • Automated control of computer s resources...

Ngày tải lên: 02/07/2014, 04:21

... http://www.di.uminho.pt William Stallings, “ Computer Organization and Architecture 5th Ed., 2000 , § Increasing Speed § Increasing Number of I/O Ports § Increasing Memory Size § Increasing Cost § ... computer components, to the increasing use of parallel organization concepts in combining those components In spite of the variety and pace of change in the computer field, certain fundamental concepts ... http://www.shore.net/~ws PROJECTS FOR TEACHING COMPUTER ORGANIZATION AND ARCHITECTURE For many instructors, an important component of a computer organization and architecture course is a project or...

Ngày tải lên: 14/08/2014, 14:20

... Pins - includes clock and reset § Address and Data Pins - 32 time-multiplexed lines for addresses and data, plus lines to interpret and validate these § Interface Control Pins - control timing ... interrupt handler routine • Multiple interrupts o Can be handled by disabling some or all interrupts Disabled interrupts generally remain pending and are handled sequentially o Can be handled by ... line: polling - when line goes high, CPU polls devices to determine which caused interrupt § Multiple lines: addressable interrupts - combination of lines indicates both interrupt and which device...

Ngày tải lên: 14/08/2014, 14:20