M morris mano, charles kime logic and computer design fundamentals (4th edition) solutions textbook prentice hall (2007)

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th EditionVerification of DeMorgan’s Theorem The Second Distributive Law X Y Z YZ X+YZ X+Y X+Z X+YX+Z...

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

8|1 1 0

(7562.45)10 = (16612.3463)8

b) (1938.257)10 = (792.41CB)16c) (175.175)10 = (10101111.001011)2

1-11*

a) (673.6)8 = (110 111 011.110)2

= (1BB.C)16b) (E7C.B)16 = (1110 0111 1100.1011)2

= (7174.54)8c) (310.2)4 = (11 01 00.10)2

1001101( )2 = 26+23+22+20 = 771010011.101

( )2 = 26+24+21+20+2 1+2 3 = 83.62510101110.1001

( )2 = 27+25+23+22+21+2 1+2 4 = 174.5625

11×r2+14×r1+14×r0 = 2699

11×r2+14×r–2685 = 0

Problem Solutions – Chapter 1

= (101111010.11)2

1-19*

(694)10 = (0110 1001 0100)BCD(835)10 = (1000 0011 0101)BCD

011 1001 0Subtract 3 -0011

01 1001 Move R 0 1100 110 100 column > 0111Subtract 3 -0011

0 1001 110 Move R 0100 1110

001 1001 1000 1Move R 00 1100 1100 01 101 and 100 columns > 0111

3×r2+6×r1+5×r0 = 194

3×r2+6×r–189 = 0

Problem Solutions – Chapter 1

1-25*

a) (11111111)2b) (0010 0101 0101)BCDc) 011 0010 011 0101 011 0101ASCIId) 0011 0010 1011 0101 1011 0101ASCII with Odd Parity

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

Verification of DeMorgan’s Theorem

The Second Distributive Law

X Y Z YZ X+YZ X+Y X+Z (X+Y)(X+Z)

Problem Solutions – Chapter 2

Problem Solutions – Chapter 2

11

Problem Solutions – Chapter 2

2-19.*

2-22.*

2-25.*

2-32.*

Prime = XZ WX X Z WZ, , , Prime = CD AC BD A BD BC, , , , Prime = AB AC AD BC BD CD, , , , ,

Essential = X Z XZ, Essential = A C BD ABD, , Essential = A C BC BD, ,

Z

A

BC

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

D

11

Problem Solutions – Chapter 3

A04 6

A1

A2

DECODER

0 2 3

11

1X

11

Problem Solutions – Chapter 3

S(2:0)

8x1 MUX

D(6:0) Y0

S(2:0)

D(7:0)

D(14:8)

D(7)A(2:0)

S0

S1C

D

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

Problem Solutions – Chapter 4

X3 X4

f

N3 N4 N5

N6

begin

F <= (X and Z) or ((not Y) and Z);

end;

The solution given is very thorough since it checks each of the carry connections between adjacent cells

transferring 0 and 1 In contrast a test applying C0 = 1 and A = 15 with B = 0 would allow a whole

variety of incorrect connections between cells that would not be detected

1

Problem Solutions – Chapter 4

4-34.*

4-38.*

4-43.*

X1 X2

X3 X4

f

N3 N4 N5

The solution given is very thorough since it checks each of the carry connections between adjacent cells

transferring 0 and 1 In contrast a test applying C0 = 1 and A = 15 with B = 0 would allow a whole

variety of incorrect connections between cells that would not be detected

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

Present state Input Next state

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

State diagram is the combination of the above two diagrams.

0 0 1 1 0 0 1 1

1 0 1 0 0 1 0 1

0 1 1 0 1 0 0 1

1/1 0/0

11

Problem Solutions – Chapter 5

Format: XY/Z (x = unspecified)

Present state Inputs Next state Output

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 0 1 0 1 0

0 X 1 X 1 X 0 X

To use a one-hot assignment, the two flip-flops A and B

need to be replaced with four flip-flops Y4, Y3, Y2 Y1

Present State Input Next State Output

No Reset State Specified

D1 = Y1’= X·Y1 + X·Y4D2 = Y2’ = X·Y1 + X·Y2D3 = Y3’ = X·Y2 + X·Y3D4 = Y4’ = X·Y3 + X·Y4

Y4

Problem Solutions – Chapter 5

Format: SRb)

Present state Input Next state

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 1 1 0 1 1

0 0 1 1 x 0 x x

x x 0 0 0 1 0 0

S R

A Q

S R

11/0 x0/1, 01/0

x0/0, 01/1

11/0 10/1

7

8

9 11

12

13

14 15

Reset, 00, 01, 00, 01, 11, x0, x0, 01, 10,

01, 01, 11, 11, 11, 10

Problem Solutions – Chapter 5

This simulation was performed without initializing the state of the latches of the flip-flop beforehand

Each gate in the flip-flop implementation has a delay of 1 ns The interaction of these delays with the

input change times produced a narrow pulse in Y at about 55 ns In this case, the pulse is not harmful

since it dies out well before the positive clock edge occurs Nevertheless, a thorough examination of such

a pulse to be sure that it does not represent a design error or important timing problem is critical

Problem Solutions – Chapter 5

(continued in the next column)

architecture mux_4to1_arch of mux_4to1 isbegin

process (S, D)begin case S iswhen "00" => Y <= D(0);

if CLK'event and CLK='0' then CLK falling edge

(continued in the next column)

case J is when '0' =>

if K = '1' then q_out <= '0';

when '1' =>

if K = '0' then q_out <= '1';

module JK_FF (J, K, CLK, Q) ; always @(negedge CLK)

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

a) The longest direct path delay is from input X through the two XOR gates to the output Y

tdelay = tpdXOR + tpdXOR = 0.20 + 0.20 = 0.40 nsb) The longest path from an external input to a positive clock edge is from input X through the XOR gate and

the inverter to the B Flip-flop

tdelay = tpdXOR + tpd INV + tsFF = 0.20 + 0.05 + 0.1 = 0.35 ns

c) The longest path delay from the positive clock edge is from Flip-flop A through the two XOR gates to the

output Y

tdelay = tpdFF + 2 tpdXOR = 0.40 + 2(0.20) = 0.80 ns

d) The longest path delay from positive clock edge to positive clock edge is from clock on Flip-flop A through

tdelay-clock edge to clock edge = tpdFF + tpdXOR + tpdINV + tsFF = 0.40 + 0.20 + 0.05 + 0.10 = 0.75 ns

e) The maximum frequency is 1/tdelay- clock edge to clock edge For this circuit, tdelay-clock edge to clock edge

is 0.75 ns, so the maximum frequency is 1/0.75 ns = 1.33 GHz

the XOR gate and inverter to clock on Flip-flop B

into its environment Calculation of this frequency cannot be performed in this case since data for paths through

the environment is not provided

Comment: The clock frequency may need to be lower due to other delay paths that pass outside of the circuit

Problem Solutions – Chapter 6

6-13.* (Errata: Change "32 X 8" to "64 X 8" ROM)

D

A

BC

D

A

BC

D

A

BC

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

Problem Solutions – Chapter 7

7-13.*

7-14.*

The equations given on page 364-5 can be manipulated into SOP form as follows: D1 =

Q1, D2 = Q2 ⊕ Q1Q8 = Q1Q2Q8 + Q1Q2 + Q2Q8, D4 = Q4⊕ Q1Q2 = Q1Q2Q4 + Q1Q4+ Q2Q4, D8 = Q8⊕ (Q1Q8 + Q1Q2Q4) = Q8(Q1Q8+Q1Q2Q4) + Q8(Q1 + Q8)(Q1 + Q2+ Q4) = Q1Q2Q4Q8 + Q1 Q8 These equations are mapped onto the K-maps for Table7-9 below and meet the specifications given by the maps and the table

01

0 0

00

00

11

11

func-Present state Next state a) DB = C b) DA = BC + AC

Problem Solutions – Chapter 7

Q0

Q1

Q2

Q3C

ADD 4 CI

A(0-3)

B(0-3)

Load

Q(0-3)CO

CTR 4 Count

D(0-3)

C(0-3)CO

ADD 4 CI

Q(0-3)

REG 4

D(0-3)R2L

L

C1 C2

Clock

Problem Solutions – Chapter 7

b) Source Registers -> Destination R0 -> R4

R1 -> R0, R3 R2 -> R0, R4 R3 -> R2 R4 -> R1, R2

c) The minimum number of buses needed for operation of the transfers

is three since transfer Cb requires three different sources

MUX

MUX

MUXd)

X1 + X2

Z1X1 + X2

X1 + X2

X1 · X2

Problem Solutions – Chapter 7

Reset

X

X

XX

Z

XXX

0 0

W

W

1 0

0 1

0 0

0 0 0

XY X

X Y

1 0 0

0 0 0

0 1

by the above equations and three D flip-flops withReset connected to S on the first flip-flop and to R

on the other two flip-flops

CLK

L R

simultaneous synchronous transfer.

LB

LC

LB = 0, LC = 0

Problem Solutions – Chapter 7

7-48.*

D C R

D C R

D C R G

Problem Solutions – Chapter 7

architecture process_3 of prob_7_53 is

type state_type is (STA, STB, STC);

signal state, next_state: state_type;

begin

Process 1 - state register

state_register: process (clk, RESET)

Process 2 - next state function

next_state_func: process (W, X, Y, state)

elsenext_state <= STA;

end if;

when STB =>

if X = '0' and Y = '1' thennext_state <= STA;

elsenext_state <= STC;

case state is when STA =>

Problem Solutions – Chapter 7

7-54.*

// State Diagram in Figure 5-40 using Verilog

module prob_7_54 (clk, RESET, W, X, Y, Z);

elsenext_state <= STC;

STC:

next_state <= STA;

endcaseend

// Output Functionalways@(X or Y or state)begin

Z <= 0;

case (state)STB: if (X == 0 & Y == 0)

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

Number of bits in array = 216 x 24 = 220 = 210 * 210

Row Decoder size = 210

a) Row Decoder = 10 to 1024, AND gates = 210 = 1024 (assumes 1 level of gates with 10 inputs/gate)

Column Decoder = 6 to 64, AND gates = 26 = 64 (assumes 1 level of gates with 6 inputs/gate)

Total AND gates required = 1024 + 64 =1088

b) (32000)10 = (0111110100 000000)2, Row = 500, Column = 0

a) 2 MB/128 K x 16 = 2MB/ 256 KB = 8 b) With 2 byte/word, 2MB/2B = 220, Add Bits = 20

128K addresses per chip implies 17 address bits c) 3 address lines to decoder, decoder is 3-to-8-line

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

Y

G0Adder

C2

S1

S1

S0 S1 S0

D0 D1 D2 D3

B0

0

0

D0 D1 D2 D3

D0 D1 S

A0

A0

D0 D1 S

Y FA

S0 S1

Bi

Bi

0

D0 D1 D2 D3

Bi

a) XOR = 00, NAND = 01, NOR = 10 XNOR = 11 Out = S1 A B + S1AB + S1AB + S1S0AB + (one of S0 A B + S1 S0 A)

Problem Solutions – Chapter 9

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

LD R2, CDIV R1, R2, R1

LD R2, A

LD R3, BADD R2, R2, R3MUL R1, R1, R2

ST Y, R1

MOV T1, AADD T1, BMUL T1, CMOV T2, EMUL T2, FMOV T3, DSUB T3, T2DIV T1, T3MOV Y, T1

Problem Solutions – Chapter 10

Smallest Number = 0.5 × 2–255Largest Number = (1 – 2–26) × 2+255

E e (e)2+8 15 1111 +7 14 1110 +6 13 1101 +5 12 1100 +4 11 1011 +3 10 1010 +2 9 1001 +1 8 1000

0 7 0111 –1 6 0110 –2 5 0101 –3 4 0100 –4 3 0011 –5 2 0010 –6 1 0001 –7 0 0000

TEST (0001)16, R (AND Immediate 1 with Register R)BNZ ADRS (Branch to ADRS if Z = 0)

Problem Solutions – Chapter 10

A software interrupt provides a way to call the interrupt routines normally associated with

external or internal interrupts by inserting an instruction into the code Privileged system

calls for example must be executed through interrupts in order to switch from user to

system mode Procedure calls do not allow this change

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

a) The latency time = 0.5 ns x 8 = 4.0 ns

b) The maximum throughput is 1 instruction per cycle or 2 billion instructions per second.

c) The time required to execute is 10 instruction + 8 pipe stages -1 = 17 cycles *0.5ns = 8.5ns

Problem Solutions – Chapter 11

Problem Solutions – Chapter 11

AX4

S1

D0 D1

DA3:0

BA3:0

FBA3:0FBA4

BA3:0

DA3:0

FDA3:0FDA4

Action Address MZ CA W DX D BS S W FS C MA B AX BX CS

LMPM

Problem Solutions – Chapter 11

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

b) Since two bits must be used to address the four registers, there are 14 bits remaining and

214 or 16,384 distinct I/O Interface Units can be supported

A given address can be shared by two registers if one is write only and one is read only If a register

is both written to and read from the bus, then it needs its own address An 8-bit address provides

256 addresses Suppose that the 50 % of registers requiring 1 address is X Then the remaining 50

% of the registers, also X can share addresses requiring only 0.5 addresses So 1.5 X = 256 and X =

170.67 registers for a total of 341.33 registers To meet the original constraints exactly, the total

number of registers must be divisible by 4, so 340 registers can be used, 170 of which are read/

write, 85 of which are read only and 85 of which are write only There is one more address available

for either one read/write register or up to a pair with a read only register and a write only register

Data Bus Address Bus

RD Strobe

WR Strobe CPU I/O Device

Data bus

Strobe

Address bus Read Strobe Write

From I/O Read Operation

Write Operation From CPU Data bus

Strobe Address bus Read Strobe Write

From CPU

There are 7 edges in the NRZI waveform for the SYNC pattern that can be used for synchronization

Problem Solutions – Chapter 12

4 bits 0110 1001

4 bits Type

0100111

Endpoint Address 0010

EOP CRC

(a) Output packet

SYNC

8 bits

Check

4 bits 0011 1100

4 bits Type

SYNC

8 bits

Check

4 bits 1000 0111

4 bits Type

EOP CRC

EOP

Data 010000101001111010100110

(b) Data packet (Data0 type) (bits LSB first)

(c) Handshake packet (Stall type)

Device 0 Device 1 Device 2 Description PI PO RF VAD PI PO RF VAD PI PO RF VAD Initially 0 0 0 - 0 0 0 - 0 0 1 - Before CPU acknowledges Device 2 0 0 1 - 0 0 0 - 0 0 1 -

After CPU sends acknowledge 1 0 1 0 0 0 0 - 0 0 1

-Replace the six leading 0’s with 000110

This is Figure 13-17 with the Interrupt and Mask Registers increased to

6 bits each, and the 4x2 Priority Encoder replaced by a 8x3 Priority Encoder Additionally, VAD must accept a 3rd bit from the PriorityEncoder

When the CPU communicates with the DMA, the read and write lines are used as DMAinputs When the DMA communicates with the Memory, these lines are used asoutputs from the DMA

Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition

M, M, M, M, M, M, M, M, M, M, M, H, H, H, since there are 12 locations indexed appropriately for instructionsand four indexed appropriately for data

Since the lines are 32 bytes, 5 bits are used to address bytes in the lines

Since there are 1K bytes, there are 1024/32 = 25 cache lines

a) Index = 5 Bits,b) Tag = 32 – 5 – 5 = 22 Bitsc) 32 × (32 × 8 + 22 + 1) = 8928 bits

a) See Instruction and Data Caches section on page 635 of the text

b) See Write Methods section on page 631 of the text

a) Effective Access Time = 0.91 * 4ns + 0.09 * 40 ns = 7.24 nsb) Effective Access Time = 0.82 * 4ns + 0.18* 40 ns = 10.48 nsc) Effective Access Time = 0.96 * 4ns + 0.04 * 40 ns = 5.44 ns

a) Each page table handles 512 pages assuming 64-bit words Thereare 4263 pages which requires 4263/512 8.33 page tables So 9 pagetables are needed

b) 9 directory entries are needed, requiring 1 directory page

c) 4263 - 8*512 = 167 entries in the last page table

In section 14-3, it is mentioned that write-through in caches can slow down processing, but this can be

avoided by using write buffering When virtual memory does a write to the secondary device, the amount of

data being written is typically very large and the device very slow These two factors generally make it

impossible to do write-through with virtual memory Either the slow down is prohibitively large, or the

buff-ering cost is just too high