Tài liệu Logic Design with VHDL doc

States which have the same next state NS for a given input should be given adjacent assignments look at the columns of the state table.. CONTROL SECTION DATA SECTION Condition Signals Da

Figure 1-2 Full Adder

(a) Full adder module

(b) Truth Table

Cout = X'YCin + XY'Cin + XYCin' + XYCin = XY + XCin + YCin Sum = X'Y'Cin + X'YCin' + XY'Cin' + XYCin = X + Y + Cin

1 1 1

1

1

01

00 11 10 01

00

11 10

AB CD

1

X 1

5 13

15

14 10

12 1

3

8 9 11 2

1

1

1 1

1

01

01 00

11

10

AB CD

Figure 1-4 Selection of Prime Implicants

F = A'C' + A'B'D' + ACD + A'BD

or

F = A'C' + A'B'D' + ACD + BCD

X 1 X

11 10

AB CD

E = F = 0 MS0 = A'B' + ACD

X

X X X

X X

1 X X

01

01 00

11 10

AB CD

E = 0, F = 1 MS2 = AD

11 10

AB CD

E = 1, F = 0 MS1 = A'D

G = MS + EMS + FMS = A'B' + ACD + EA'D + FAD

A B

Figure 1-6 NAND and NOR Gates

D C

A

E F

Z

A

G' D

C' B'

E F

Z

Double inversion cancels

Complemented input

cancels inversion

Figure 1-7 Conversion to NOR Gates

(a) AND-OR network

(b) Equivalent NOR-gate network

Conversion of AND-OR Network to NAND Gates

(a) AND_OR network

(b) First step in NAND conversion

(c) Completed conversion

Figure 1-9 Elimination of 1-Hazard

0 1

0 1

1 0 1 0

1 0

01 00

11 10

A BC

F

0 1

0 1

1 0 1 0

1 0

01 00

11 10

A BC

Q = D +

CK FF

J K

FF

Q Q'

+

Q = QT' + Q'T = Q + T

Q

D G

Combinational Network

State Reg Next state

0/1

1/0 0/1

S1 S3 S4 S5 S5 S0 S0

S2 S4 S4 S5 S6 S0 –

Z

X = 0 X = 1

1 1 0 0 1 0 1

0 0 1 1 0 1 –

Figure 1-17 State Graph and Table

for Code Converter

(a) Mealy state graph

(b) State Table

From Page 20

I States which have the same next state (NS) for a given input should be given adjacent

assignments (look at the columns of the state table)

II States which are the next states of the same state should be given adjacent assignments(look at the rows)

III States which have the same output for a given input should be given adjacent assignments

I (1,2) (3,4) (5,6) (in the X=1 column, S1 and S2 both have NS S4;

in the X=0 column, S3 & S4 have NS S5, and S5 & S6 have NS S0)

II (1,2) (3,4) (5,6) (S1 & S2 are NS of S0; S3 & S4 are NS of S1;

and S5 & S6 are NS of S4)III (0,1,4,6) (2,3,5)

Figure 1-18(a) State Assignment Map

00 01 11 10

Q1 Q2 Q3

S0

S5 S3 S6 S4

S1 S2

Figure 1-17(b) State Table Figure 1-18(b) Transition Table

1 1

0 0

1 1

0

1 X

0

1 X 0 0

01

01 00

11 10

XQ1 Q2Q3

D1 = Q1+ = Q2'

0 1

1 1

1 1 1

1 X

0

0 X 0 0

01

01 00

11 10

XQ1 Q2Q3

D 2 = Q2+= Q1

0 1

1 1

0 0

1

0 X

0 X

0

1 X 0 0

01

01 00

11 10

0 1 1

0 X

0

0 X 1 1

01

01 00

11 10

XQ1

Q 2Q3

Z = X'Q3' + XQ3 Figure 1-19

Karnaugh Maps for Figure 1-17

G6

G7

Q1 Q2 Q3

Q1 Q3'

Q1' Q2'

X

G3 G2

FF1

FF2

FF3 I1

Figure 1-20 Realization of Code Converter

1 1

0 0

1 1 0

0 X

1 X

0

1 X 0 0

1 1 1

1 X

1 X

0

0 X 0 0

01

00 11 10

01 00

11 10

XQ1 Q2Q3

0 1

1 1

0 0 1

0 X

0 X

0

1 X 0 0

01

00 11 10

01 00

11 10

XQ 1 Q2Q3

J2

1 1

0 0

1 1 0

0 X

1 X

0

1 X 0 0

X X X

X X

X X

0

1 X 0 0

01

00 11 10

01 00

11 10

XQ1 Q2Q3

J1= Q2'

X 0

1 1

0 0 1

1 X

0 X

X

X X X X

01

00 11 10

01 00

11 10

XQ1 Q2Q3

K1 = Q2

J1 = Q2' K1 = Q2

J2 = Q1 K2 = Q1' J3 = X'Q1 + XQ1' K3 = Q1' + Q2'

Figure 1-21 Derivation of J-K Input Equations

(a) Derivation using separate J-K map

(b) Derivation using the shortcut method

NRZ NRZI RZ Manchester

bit sequence

1 bit time Figure 1-22

Coding Schemes for Serial Data Transmission

Conversion Network

X NRZ data

S 2 1

S 3 –

Present State

Present Output (Z)

Figure 1-23 Moore network for NRZ-to-Manchester Conversion

(a) Conversion network

0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0

X (NRZ)

CLOCK2

State Z

(Manchester)

S0 S1 S2 S3 S0 S3 S0 S3 S0 S1 S2 S1 S2 S3 S0 S1

1 bit time

1 bit time

Figure 1-24 Timing for Moore Network

Figure 1-25 Determination of Equivalent States

for every input sequence

Figure 1-26(i) State Table Reduction

Present

State

Next State

X = 0 1

Present Output

Figure 1-26(ii) State Table Reduction

a ≡ b iff c ≡ d and e ≡ f

a ≡ b, c ≡ d, e ≡ f

Figure 1-26(iii) State Table Reduction

Present

State

Next State

X = 0 1

Present Output

a c e 0 0

c a g 0 0

e e a 0 1

g c g 0 1 Final Reduced Table

a ≡ b, c ≡ d, e ≡ f

Figure 1-28 Timing Diagram for Figure 1-20

D

t su th Figure 1-29 Setup and Hold Times for D Flip-flop

CONTROL SECTION

DATA SECTION Condition

Signals

Data In

Data Out

Clock

Control

Inputs

Control Signals Figure 1-31 Synchronous Digital System

Control Signal Clock·CS

State Change Initiated Here

Uncertain

Figure 1-32 Timing Chart for System with Falling-Edge Devicves

Figure 1-33 Gated Control Signal

Control Signal (CS) CLK1 = Clock · CS

CS

State Change Initiated Here

CLK2 = Clock + CS

Figure 1-34 Timing Chart with Rising-Edge Devices

CK

Clock CS

CK Clock

CLK2

Figure 1-36 Correct Design Figure 1-35 Incorrect Design

Synchronous Design Principals (from page 34)

Method: All clock inputs to flip-flops, registers, counters, etc are driven

directly from the system clock or from the clock ANDed with a control signal.

Result: All state changes occur immediately following the active edge of

the clock signal.

Advantage: All switching transients, switching noise, etc occur between clock

pulses and have no effect on system performance.

VHDL = VHSIC Hardware Description Language

VHSIC = Very High Speed Integrated Circuit

Hardware description, simulation, and synthesis

Describes hardware at different levels:

behavioral, logic equation, structural

Top-down design methodology

Technology Independent

Figure 2-1 Gate Network

A B

From Page 45-46

entity FullAdder is

Cout, Sum: out bit); Outputs

end FullAdder;

architecture Equations of FullAdder is

Sum <= X xor Y xor Cin after 10 ns;

Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 10 ns;

end Equations;

X Y Cin

Cout

Sum FULL

ADDER

Figure 2-2 VHDL Program Structure

Entity Architecture

Entity Architecture

Module 1

Entity Architecture

Module 2

Entity Architecture

Module N

entity entity-name is

[port(interface-signal-declaration);]

end [entity] [entity-name];

architecture architecture-name of entity-name is

Figure 2-3 4-bit Binary Adder

Full Adder Full Adder Full Adder Full Adder Ci

B(0) A(0)

B(1) A(1)

B(2) A(2)

A(3) B(3)

Figure 2-4(i) Structural Description of 4-bit Adder

entity Adder4 is

port (A, B: in bit_vector(3 downto 0); Ci: in bit; Inputs

S: out bit_vector(3 downto 0); Co: out bit); Outputs

end Adder4;

Figure 2-3 4-bit Binary Adder

Full Adder Full Adder Full Adder Full Adder Ci

B(0) A(0)

B(1) A(1)

B(2) A(2)

A(3) B(3)

Figure 2-4(ii) Structural Description of 4-bit Adder

architecture Structure of Adder4 is

component FullAdder

port (X, Y, Cin: in bit; Inputs

Cout, Sum: out bit); Outputs

end component;

signal C: bit_vector(3 downto 1);

begin instantiate four copies of the FullAdder

FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0));

FA1: FullAdder port map (A(1), B(1), C(1), C(2), S(1));

FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2));

FA3: FullAdder port map (A(3), B(3), C(3), Co, S(3));

end Structure;

From Page 49

10 +0 1 2 3 4 (statements 1,2,3 execute; then update A,B,C)

10 +1 2 3 4 4 (statements 1,2,3 execute; then update A,B,C)

10 +2 3 4 4 4 (statements 1,2,3 execute; then update A,B,C)

10 +3 4 4 4 4 (no further execution occurs)

Concurrent Statements Simulation Results

A <= B; statement 1 time ∆ A B C D

B <= C; statement 2 0 +0 1 2 3 0

C <= D; statement 3 10 +0 1 2 3 4 (statement 3 executes first)

10 +1 1 2 4 4 (then statement 2 executes)

10 +2 1 4 4 4 (then statement 1 executes)

10 +3 4 4 4 4 (no further execution occurs)

Figure 2-5 D Flip-flop Model

entity DFF is

port (D, CLK: in bit;

Q: out bit; QN: out bit := '1');

initialize QN to '1' since bit signals are initialized to '0' by default

Figure 2-7 J-K Flip-flop Model

entity JKFF is

port (SN, RN, J, K, CLK: in bit; inputs

Q: inout bit; QN: out bit := '1'); see Note 1

if RN = '0' then Q<= '0' after 10 ns; RN=0 will clear the FF

elsif SN = '0' then Q<= '1' after 10 ns; SN=0 will set the FF

elsif CLK = '0' and CLK'event then see Note 3

Q <= (J and not Q) or (not K and Q) after 10 ns; see Note 4

end if;

end process;

end JKFF1;

Note 1: Q is declared as inout (rather than out) because it appears on both the left and right sides of an

assignment within the architecture.

Note 2: The flip-flop can change state in response to changes in SN, RN, and CLK, so these 3 signals are in the

sensitivity list.

Note 3: The condition (CLK = '0' and CLK'event) is TRUE only if CLK has just changed from '1' to '0'.

Note 4: Characteristic equation which describes behavior of J-K flip-flop.

Note 5: Every time Q changes, QN will be updated If this statement were placed within the process, the old

value of Q would be used instead

of the new value.

T F

T F

T F

if (C1) then S1; S2; if (C1) then S1; S2;

else if (C2) then S3; S4; elsif (C2) then S3; S4;

else if (C3) then S5; S6; elsif (C3) then S5; S6;

else S7; S8; else S7; S8;

end if;

end if;

Figure 2-9 4-to-1 Multiplexer

F <= (not A and not B and I0) or

(not A and B and I1) or (A and not B and I2) or (A and B and I3);

MUX model using a conditional signal assignment statement:

F <= I0 when Sel = 0

else I1 when Sel = 1 else I2 when Sel = 2 else I3;

In the above concurrent statement, Sel represents the integer equivalent of a 2-bit binary

number with bits A and B

General form of conditional signal assignment statement:

signal_name <= expression1 when condition1

else expression2 when condition2

Multiplexer Example From Page 55

If a MUX model is used inside a process, a concurrent statement cannot be used As an

alternative, the MUX can be modeled using a case statement:

Figure 2-10 Compilation, Elaboration, and Simulation of VHDL Code

SimulationCompiler

(Analyzer)

workinglibrary Elaborator Simulator

SimulatorCommands

SimulatorOutput

mediate

Inter-VHDL

Source

Resource Libraries

Structure

Synthesize Components &Connections

Figure 2-11 VHDL Code for Simulation Example

entity simulation_example is

end simulation_example;

architecture test1 of simulation_example is

signal A,B: bit;

Figure 2-12 Signal Drivers for Simulation Example

A B '1' @ 10

'0' '0' time = 5

A B

'1' time = 10

B

'1' '0' @ 20

A B

'0' '1' '0' @ 20 time = 15

After initialization:

time = 0

A B

'0'

A B

'0' '1' @ 10

'0' '0'

Current value Queued

values

if X='0' then Z<='1'; Nextstate<=1; end if;

if X='1' then Z<='0'; Nextstate<=2; end if;

when 1 =>

if X='0' then Z<='1'; Nextstate<=3; end if;

if X='1' then Z<='0'; Nextstate<=4; end if;

when 2 =>

if X='0' then Z<='0'; Nextstate<=4; end if;

if X='1' then Z<='1'; Nextstate<=4; end if;

when 3 =>

if X='0' then Z<='0'; Nextstate<=5; end if;

if X='1' then Z<='1'; Nextstate<=5; end if;

when 4 =>

if X='0' then Z<='1'; Nextstate<=5; end if;

if X='1' then Z<='0'; Nextstate<=6; end if;

PS X = 0 X = 1

NS

S0S1S2S3S4S5S6

S1S3S4S5S5S0S0

S2S4S4S5S6S0–

Z

X = 0 X = 1

1100101

001101–

Figure 2-13(b) Behavioral model for Figure 1-17

when 5 =>

if X='0' then Z<='0'; Nextstate<=0; end if;

if X='1' then Z<='1'; Nextstate<=0; end if;

when 6 =>

if X='0' then Z<='1'; Nextstate<=0; end if;

when others => null; should not occur

A simulator command file that can be used to test Figure 2-13 is as follows:

wave CLK X State NextState Z

force CLK 0 0, 1 100 -repeat 200

force X 0 0, 1 350, 0 550, 1 750, 0 950, 1 1350

run 1600

Execution of the preceding command file produces the waveforms shown in Figure 2-14

Figure 2-14 Waveforms for Figure 2-13

Figure 2-15 Sequential Machine Model Using Equations

The following is a description of the sequential machine of

Figure 1-17 in terms of its next state equations

The following state assignment was used:

Q3<=(Q1 and Q2 and Q3) or (not X and Q1 and not Q3) or

(X and not Q1 and not Q2) after 10 ns;

end if;

end process;

Z<=(not X and not Q3) or (X and Q3) after 20 ns;

end Equations1_4;

Figure 2-16 Structural Model of Sequential Machine

The following is a STRUCTURAL VHDL description of the network of Figure 1-20

I1: Inverter port map (X,XN);

G1: Nand3 port map (Q1,Q2,Q3,A1);

G2: Nand3 port map (Q1,Q3N,XN,A2);

G3: Nand3 port map (X,Q1N,Q2N,A3);

G4: Nand3 port map (A1,A2,A3,D3);

FF1: DFF port map (Q2N,CLK,Q1,Q1N);

FF2: DFF port map (Q1,CLK,Q2,Q2N);

FF3: DFF port map (D3,CLK,Q3,Q3N);

G5: Nand2 port map (X,Q3,A5);

G6: Nand2 port map (XN,Q3N,A6);

G7: Nand2 port map (A5,A6,Z);

end Structure

Figure 2-18(a) Behavioral Model for Figure 1-17 Using a Single Process

library BITLIB;

use BITLIB.Bit_pack.all;

entity SM1_2 is port(X, CLK: in bit; Z: out bit); end SM1_2;

architecture Table of SM1_2 is signal State, Nextstate: integer := 0;

if X='0' then Z<='1'; Nextstate<=1; end if;

if X='1' then Z<='0'; Nextstate<=2; end if;

when 1 =>

if X='0' then Z<='1'; Nextstate<=3; end if;

if X='1' then Z<='0'; Nextstate<=4; end if;

when 2 =>

if X='0' then Z<='0'; Nextstate<=4; end if;

if X='1' then Z<='1'; Nextstate<=4; end if;

when 3 =>

if X='0' then Z<='0'; Nextstate<=5; end if;

if X='1' then Z<='1'; Nextstate<=5; end if;

when 4 =>

if X='0' then Z<='1'; Nextstate<=5; end if;

if X='1' then Z<='0'; Nextstate<=6; end if;

when 5 =>

if X='0' then Z<='0'; Nextstate<=0; end if;

if X='1' then Z<='1'; Nextstate<=0; end if;

Figure 2-18(b) Behavioral Model for Figure 1-17 Using a Single Process

when 6 =>

if X='0' then Z<='1'; Nextstate<=0; end if;

when others => null; should not occur

Figure 2-19 Process Using Variables

entity dummy is

end dummy;

architecture var of dummy is

signal trigger, sum: integer:=0;

begin

process

variable var1: integer:=1;

variable var2: integer:=2;

variable var3: integer:=3;

Figure 2-20 Process Using Signals

entity dummy is

end dummy;

architecture sig of dummy is

signal trigger, sum: integer:=0;

signal sig1: integer:=1;

signal sig2: integer:=2;

signal sig3: integer:=3;

begin

process

begin

wait on trigger;

sig1 <= sig2 + sig3; sig1 = 2 + 3 = 5 (after ∆)

sum <= sig1 + sig2 + sig3; sum = 1 + 2 + 3 = 6 (after ∆)

end process;

end sig;

From Page 67

Predefined VHDL types include:

bit '0' or '1'

boolean FALSE or TRUE

integer an integer in the range –(231–1) to +(231–1)

(some implementations support a wider range)real floating-point number in the range –1.0E38 to +1.0E38

character any legal VHDL character including upper- and lower-case letters, digits,

and special characters; each printable character must be enclosed in singlequotes; e.g., 'd','7','+'

time an integer with units fs, ps, ns, us, ms, sec, min, or hr

Note that the integer range for VHDL is symmetrical even though the range for a 32-bit 2's

From Page 68

Example of array type:

type SHORT_WORD is array (15 downto 0) of bit;

Examples of array objects of type SHORT_WORD

signal DATA_WORD: SHORT_WORD;

variable ALT_WORD: SHORT_WORD := "0101010101010101";

constant ONE_WORD: SHORT_WORD := (others => '1');

General forms of the array type and array object declarations:

type array_type_name is array index_range of element_type;

signal array_name: array_type_name [ := initial_values ];

(signal may be replaced with variable or constant)

Two-dimensional array example:

type matrix4x3 is array (1 to 4, 1 to 3) of integer;

variable matrixA: matrix4x3 := ((1, 2, 3), (4, 5, 6), (7, 8, 9), (10, 11, 12));

The variable matrixA, will be initialized to:

1 2 3

4 5 6

7 8 9

10 11 12