compal la-1271 r0.1 schematics

THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC.. NEITHER THIS SHEET NOR THE INFORMATION CONT





+3V +5V +2.5V

+1.25V

+3VS +5VS +1.8VS +1.5VS +1.2VP +CPU_CORE

Power Managment table

YES S/W disable

CHIPS Rev CHIPS Rev



HA#27

HA#14HA#11

HD#41HD#39

HD#9

HA#22HA#20HA#12

HD#26

HD#63

HD#19HD#15HD#10

HREQ#4

HA#23HA#17

HD#33

HD#16

HA#30HA#21

HA#9HA#3

HD#51HD#42

HD#32HD#30

HD#12HA#16

HA#26HA#24HA#18

HD#62

HD#8HD#6

HD#11

HD#5HD#3

HA#31HA#29

HD#57HD#55HD#53HD#49HD#47HD#45

HD#18

HD#29HD#1

HREQ#3

HD#28

HREQ#2HREQ#0HA#28

HA#15

HA#7HA#4

HD#24HD#22HD#20HD#17HD#13HD#2

HA#25

HA#10HA#5

HD#61

HD#7HD#4

HA#13HA#8

HD#59

HD#37HD#35HA#19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC

U4A

NorthWood

K2L6L3M6L2M3N1N2N5T1R2P3R3T2U1P6U3T4R6W1T5U4V3W2Y1AB1

J1K5J4H3

AC1V5AA3AC3

G2H6

G4

E2F3

B21A23C21B24C24G22C26J21D25E24F23E25F26D26L21G26M21L22K23M23N22M24N23M26N26R21R25T26T22U26U23U21V24W26Y26W25Y23Y21AA25AA24

A10 A14 A18 A8 AA12 AA16 AA8 AB13 AB17 AB7 AC10 AC14 AC18 AD11 AD15 AD19 AD9 AE12 AE16 AE20 AE8 AF13 AF17 AF2 AF5 AF9 B13 B17 B7 C10 C14 C18 C8 D13 D17 D7

REQ#0REQ#2REQ#4ADS#

AP#0BINIT#

If used ITP port must depop

1 Place R_A and R_B near CPU.

2 Place decoupling cap 220PF near CPU.(Within 500mils)

H_DBI#0H_DSTBN#1H_SMI#

H_DBI#1H_DSTBP#0

H_NMIH_INTR

H_DSTBP#2

H_A20M#

H_RESET#

H_DBI#2H_THERMDC

H_PWRGDH_STPCLK#

H_DSTBN#2H_INIT#

H_DBI#3H_DSTBP#3

ITP_TMSITP_TRST#

H_F_FERR#

H_THERMTRIP#

ITP_TDIITP_TMSITP_TRST#

+CPU_CORE

+1.2VP

+H_GTLREF1+CPU_CORE

+CPU_CORE+CPU_CORE

+CPU_CORE

+5VALW+VL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC

R12410K_0402

R1271K_0402

R12510K_0402

910121416NC

VCCDXPDXNNCADD1GNDNCADD0ALERTSMBDATANCSMBCLKSTBYNC

R79100_1%

C1651UFC175220PF

R18 1 21K_0402R19 1 21K_0402

R32 1 21K_0402

R102 200_0402

12

R100 200_0402

12

R104 200_0402

12

R117 200_0402

12

R83 200_0402

12

R103 200_0402

12

R95 200_0402

12

R110 200_0402

12

R84 200_0402

12

R97 56_0402

12

R85 51.1_1%

12

R89 300_0402

12

R96 200_0402

1

2

Mobile NorthWood

U4B

NorthWood

F1G5F4AB2J6

C6B6B5AB23Y4AD25D1E5W5AB25

H2

C4B3

C1F7

P1L24

J26K25L25

AE11 AE15 AE19 AE24 AE7 AF1 AF12 AF16 AF20 AF6 B10 B14 B18 B23 B4 C11 C15 C19 C22 C5 C9 D12 D16 D20 D24 D6 E1 E13 E17 E23 E4 E9 F12 F16 F2 F25

AE5 AE3 AE1

AA21AA6F20F6A22A7

AD24AA2AC21AC24AA20U6W4Y3

F8 G24 G6 J22 J5 K24 K6 L23 L4 M22 M5 N24 N6 P22 P5 R23 R4 T24 T6 U22 U5 V23 V4 W24 W6 Y22 Y5

AD6

AC6AB5AC4Y6AA5

E22R22W22

F21P23W23

AC26

L5R5

E21P26

AE25AD20

A5AE23

A2

C3V6AB26

AD22A4

AD2

AF25AF3

RS#0RS#2RSP#

DPSLP#

LINT0INIT#

COMP1

DP#0DP#2

GTLREF0GTLREF2NC1

TESTHI0TESTHI2TESTHI4TESTHI6TESTHI8TESTHI10GHI#

BSEL0

BPM#0BPM#2BPM#4

DSTBN#0DSTBN#2

DSTBP#0DSTBP#2

ITP_CLK0

ADSTB#0

DBI#0DBI#2

DBR#

VCCAVCCSENSEVCCIOPLL

R382470_0402

R118470_0402

R119300_0402

R106 51.1_1%

12

Place 22uF caps underneath balls on solder side.

Use 2~3 vias per PAD.

Place 10uF caps on the peripheral near balls.

Place close to CPU, Use 2~3 vias per PAD.

Please place these cap in the socket cavity area

CPU Voltage ID

PM_GMUXSEL = 0 : for low Voltage A-C

1 : for high Voltage B-C

Please place these cap on the socket north side

Please place these cap on the socket south side

Used ESR 25m ohm cap total ESR=2.5m ohm

Layout note :

Place close to CPU power and ground pin as possible (<1inch)

C47.22UF_X7R

C45.22UF_X7R

C48.22UF_X7R

C49.22UF_X7R

C31.22UF_X7R

C35.22UF_X7R

C33.22UF_X7R

C18310UF_6.3V_1206_X5R

C34.22UF_X7R

C18210UF_6.3V_1206_X5R

C19910UF_6.3V_1206_X5R

67

1011

1213

1617

2021

24BE#

C0A0

C1A1

C2A2

GNDBX

C3A3

C4A4

VCC

RP48P4R_10K

C20010UF_6.3V_1206_X5R

C18410UF_6.3V_1206_X5R

C20210UF_6.3V_1206_X5R

C3010UF_6.3V_1206_X5R

C3710UF_6.3V_1206_X5R

C1710UF_6.3V_1206_X5R

C7710UF_6.3V_1206_X5R

C21010UF_6.3V_1206_X5R

C21410UF_6.3V_1206_X5R

C19210UF_6.3V_1206_X5R

C18010UF_6.3V_1206_X5R

C20310UF_6.3V_1206_X5R

C17810UF_6.3V_1206_X5R

C18610UF_6.3V_1206_X5R

C17310UF_6.3V_1206_X5R

C20410UF_6.3V_1206_X5R

C21210UF_6.3V_1206_X5R

C17910UF_6.3V_1206_X5R

C20510UF_6.3V_1206_X5R

R208240

R199 @0_0402

U23C

74HCT08

910

8

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC

D151SS355

D141N4148

Q192SA1036K2

31

Q20FMMT619231R169

3.48K_1%

C3482.2UF_16V_0805

D131N4148

R34610K_0402

@1000PF_0402

R19010K_0402

D31N4148

Q32SA1036K2

31

Q9FMMT619231R8

3.48K_1%

C152.2UF_16V_0805

D91N4148

R7710K_0402

7SDA

SCLA2VCCOS#

GNDA0

C547.1UF_0402

1 Place R_E and R_F near MCH

2 Place decoupling cap 220PF near MCH pin.(Within 500mils)

GTL Reference Voltage

Layout note :

HUB Interface Reference

1 Place R_C and R_D in middle of Bus.

2 Place capacitors near MCH.

Layout note :

Place this resistor

closely ball AE17

Place closely ball P26

Tracewidth>=7mila

AGP_ST1 0=533Mhz

Place this cap near AGP

HA#22HA#20HA#12

HREQ#4

HA#23HA#17

HA#30HA#21

HA#9HA#3

HA#16

HA#26HA#24HA#18

HA#31HA#29

HREQ#3HREQ#1

HA#28

HA#15

HA#7HA#4

HA#25

HA#10HA#5

HA#13HA#8

HA#19

HD#52HD#43

HD#14

HD#41HD#39

HD#9

HD#26

HD#63

HD#19HD#15HD#10

HD#33HD#16

HD#51HD#42

HD#32HD#30HD#12

HD#62

HD#8HD#6

HD#11

HD#5HD#3

HD#57HD#55HD#53HD#49HD#47HD#45

HD#18

HD#29HD#1

HD#28HD#24HD#22HD#20HD#17HD#13HD#2

HD#61

HD#7HD#4

HD#59

HD#37HD#35

CLK_GHT#

CLK_GHT

H_DSTBN#3H_DSTBN#0

H_DSTBP#0

H_DSTBP#2H_DSTBN#2

AGP_ADSTB1AGP_ADSTB1#

AGP_SBSTBAGP_SBSTB#

R121K_1%

R111K_1%

T4T3U3P7R2P4R6P5N2N3K4M4L3K3J2M5J3L2H4G2L7

AE17

Y5

W2W6U6T7R7U2

AD4AE6AE11AD3AE7AD11

R5

U7Y4W5J27H26V5

V3W3V7

J8K8

AA7AD13

AD5AH9AD15

M7Y8AB11AC2

AC13

HD#0HD#2HD#4HD#6HD#8HD#10HD#12HD#14HD#16HD#18HD#20HD#22HD#24HD#26HD#28HD#30HD#32HD#34HD#36HD#38HD#40HD#42HD#44HD#46HD#48HD#50HD#52HD#54HD#56HD#58HD#60HD#62

HA#3HA#5HA#7HA#9HA#10HA#12HA#14HA#16HA#18HA#20HA#22HA#24HA#26HA#28HA#30

CPURST#

HIT#

HITM#

RS#0RS#2HREQ#0HREQ#2HREQ#4

HDSTBN#0HDSTBN#2HDSTBP#0HDSTBP#2

HSWNG0

DBI#0DBI#2

HVREF0HVREF2HVREF4HRCOMP0

V25Y25AA23

Y24W28W24W25AG24AF22

R24AC27AF27

AG25AF24AG26

P25N27M26L28M27N28M24

N25

P27

AH28AG28AE28AE24

AE22P22AD25AA21

N22K5L24M23K7J26A3A11

A19A27D5D13D21E1E26F8F12F20G26H9H11H15H19J1J6J22

G_AD0G_AD2G_AD4G_AD6G_AD8G_AD10G_AD12G_AD14G_AD16G_AD18G_AD20G_AD22G_AD24G_AD26G_AD28G_AD30

G_C/BE#0G_C/BE#2

PIPE#

AD_STB0AD_STB#0AD_STB1AD_STB#1SB_STBSB_STB#

ST0ST2

HI_0HI_2HI_4HI_6HI_8HI_10

HI_STBHI_STB#

HLRCOMPHI_REF

SBA0SBA2SBA4SBA6

RBF#

WBF#

66INGRCOMPAGPREF

VSS0VSS2VSS4VSS6VSS8VSS10

VSS11VSS13VSS15VSS17VSS19VSS21VSS23VSS25VSS27VSS29VSS31VSS33VSS35VSS37VSS39

R2224.9_0603_1%

R2524.9_0603_1%

R2336.5_1%

12

R2649.9_1%

R27100_1%

C69

220PFC42

1UF

R36 36.5_1%

R90301_1%

R91301_1%

C196.01UF_0402

C39.1UF_0402

C16.1UF_0402

R15 @6.2K_0402

12

R30 8.2K_0402

12

R20 8.2K_0402

12

R16 8.2K_0402

12

R17 @8.2K_0402

12

R21 @8.2K_0402

12

R34 @8.2K_0402

12

R13 2K_0402

12

R10 @0_0402

12

C57.01UF_0402

R9 @1K_0402

12

Trace A to ball U13/T13 or U17/T7 =1.5" Max

Layout note Place this cap closely pinJ28

Murata LQG21N4R7K10

Layout note Place R_J closely Ball H3<40mil,Ball H3 to G3 trace must

SDREF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC

A5A13A21C1C29D7D11D19D25F6F10F18G1G29H8H10H14H18H22K22K26L23K6J5

R22U22W22AA22AB21AD21AE26AF23AG29AJ25N14P13P17R16T15U14

L29N26L25M22N23

T17

U17

L1L6L22N1N8N13N17P6P14R1R13R17T6T14T22U1U15V6V22W1W8W26Y6Y22AA1

AA4AA29AB6AB10AB13AB15AB19AC1AC18AC21AC26AD6AD10AD14AD19AE1AE18AE29AF5AF9AF11AF15AF19AF25AG1AG18AG22AH21AJ3AJ7AJ11AJ15AJ27

VTT_0VTT_2VTT_4VTT_6VTT_8VTT_10VTT_12VTT_14VTT_16VTT_18

VCCSM1VCCSM3VCCSM5VCCSM7VCCSM9VCCSM10VCCSM12VCCSM14VCCSM16VCCSM18VCCSM20VCCSM22VCCSM24VCCSM26VCCSM28VCCSM30VCCSM32VCCSM34VCCSM36VCCSM38

VCC1_5_0VCC1_5_2VCC1_5_4VCC1_5_6VCC1_5_8VCC1_5_10VCC1_5_12VCC1_5_14

VCC1_5_16VCC1_5_18VCC1_5_20VCC1_5_22VCC1_5_24

VCC1_8_0VCC1_8_2VCC1_8_4

VCCGA1VCCHA1

VSSGA2

VSS41VSS43VSS45VSS47VSS49VSS51VSS53VSS55VSS57VSS59VSS61VSS63VSS65VSS67VSS69VSS71VSS73VSS75VSS77VSS79VSS81

VSS83VSS85VSS87VSS89VSS91VSS93VSS95VSS97VSS99VSS100VSS102VSS104VSS106VSS108VSS110VSS112VSS114VSS116VSS118VSS120VSS122VSS124VSS126VSS128VSS130VSS132VSS134VSS136VSS138VSS140

U10C

BROOKDALE(MCH-M)

G28F27C28H25F25B28C27C25D27E25E23E21B23B21D20D18E19E17C12C10C13D10C9E8E11B9C7D6B3B5C4E5C3F4B2C2E2G5C16B15B17C15

E14F15G25G6

G15E24H5F5

F26C26B19C8E3E15

E12F17G18E18F19G21F21E20

G12

G23H23F23K23

K25J25G17H7

E9F9G9G10

J28E16

G3

H27F11G11G8J21

SDQ0SDQ2SDQ4SDQ6SDQ8SDQ10SDQ12SDQ14SDQ16SDQ18SDQ20SDQ22SDQ24SDQ26SDQ28SDQ30SDQ32SDQ34SDQ36SDQ38SDQ40SDQ42SDQ44SDQ46SDQ48SDQ50SDQ52SDQ54SDQ56SDQ58SDQ60SDQ62

SDQ64/CB0SDQ66/CB2SDQ68/CB4SDQ70/CB6

SCK0SCK#0SCK1SCK#1SCK2SCK#2SCK3SCK#3SCK4SCK#4SCK5SCK#5

SDQS0SDQS2SDQS4SDQS6SDQS8

SMA0/CS#11

SMA3/CS#9SMA5/CS#8SMA7/CS#4SMA9/CS#0SMA10SMA11/CS#2

SBS0

SCKE0SCKE2SCKE4

SCK6SCK#6SCK7SCK#7SCK8SCK#8SCS#0SCS#2SCS#4

SMRCOMPSMA2/CS#6

RCVENIN#

RCVENOUT#

SSI_STSRAS#

R38 0_0402

12

C78 1UF_0402_X5RC81 @47PF_0402

L194.7UH_30mA

Distribute as close as possible

to MCH Processor Quadrant.(between VTTFSB and VSS pin)

Layout note :

Distribute as close as possible

to MCH Processor Quadrant.(between VCCAGP/VCCCORE

and VSS pin)

Layout note :

Distribute as close as possible

to MCH Processor Quadrant.(between VCCHL and VSS pin)

Hub-Link AGP/CORE

Distribute as close as possible

to MCH Processor Quadrant.(between VCCSM and VSS pin)

C24.1UF_0402_X5R

C27.1UF_0402_X5R

C28.1UF_0402_X5R

C61.1UF_0402_X5R

C25.1UF_0402_X5R

C29.1UF_0402_X5R

C1810UF_6.3V_1206_X5R

C54.1UF_0402_X5R

C52.1UF_0402_X5R

C50.1UF_0402_X5R

C53.1UF_0402_X5R

C62.1UF_0402_X5R

C66.1UF_0402_X5R

C9022UF_10V_1206

C75.1UF_0402_X5R

C73.1UF_0402_X5R

C86.1UF_0402_X5R

C74.1UF_0402_X5R

C79.1UF_0402_X5R

C84.1UF_0402_X5R

C9422UF_10V_1206

C225.1UF_0402_X5R

C71.1UF_0402_X5R

C89.1UF_0402_X5R

C85.1UF_0402_X5R

C83.1UF_0402_X5R

C70.1UF_0402_X5R

C87.1UF_0402_X5R

C88.1UF_0402_X5R

C82.1UF_0402_X5R

+ C93150UF_D2_6.3V

C6410UF_6.3V_1206_X5R

+ C176100UF_D_16V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC



all trace length<750mil

Place these resistor closely DIMM0, all trace length Max=1.3" Layout note

Layout note Place these resistor closely DIMM0, all trace length<=750mil

Place these resistor closely DIMM0, all trace length<=750mil Layout note

Bottom side

DDR_SDQ2

DDR_SDQ8

DDR_SDQ9DDR_SDQ12

DDR_DQ2

DDR_DQ8

DDR_DQ9DDR_DQ12

DDR_DQS1DDR_DQ13

DDR_DQ39

DDR_DQ44

DDR_DQ45

DDR_DQS5DDR_DQ41

DDR_DQ43

DDR_SDQS3

DDR_DQ29DDR_DQS3DDR_SDQ29

DDR_SDQ47

DDR_DQ46DDR_SDQ46

DDR_DQ4

DDR_DQ3

DDR_DQ7DDR_DQ12

DDR_F_SMA12DDR_F_SMA9

DDR_SMA8DDR_SMA11

DDR_F_SMA8DDR_F_SMA11

DDR_SMA7

DDR_SMA3

DDR_SMA10

DDR_SMA11DDR_SMA8

DDR_SMA6

DDR_SMA2

DDR_SBS0DDR_SWE#

DDR_F_CB3

DDR_DQ49

DDR_DQ54DDR_DQ52

DDR_DQ50DDR_DQS6DDR_DQ48

JP22

DDR-SODIMM_200_Normal

1591115192327313539

414549535761656973778185899397101105109113117121125129133137141

261014182226303438

424650545862667074788286909498100104108112116120124128132136140144145

149153157161165169173177181185189193197

146150154158162166170174178182186190194198

VREFVSSDQ1VDDDQS0DQ2DQ3VDDDQ9DQS1VSSDQ10VDDCK0CK0#

VSS

DQ16VDDDQS2VSSDQ19VDDDQ25VSSDQ26VDDCB0VSSDQS8CB2VDDCB3DUVSSCK2#

VDDCKE1DU/A13A12A9VSSA7A3VDDA10/APBA0WE#

S0#

DUVSSDQ32VDDDQS4VSSDQ35VDD

VREFVSSDQ5VDDDQ6DQ7DQ12VDDDQ13DM1VSSDQ14VDDVSS

DQ20VDDDQ22VSSDQ23VDDDQ29DM3VSSDQ30VDDCB4VSSDM8CB6VDDCB7DU/RESET#

VSSVDDCKE0DU/BA2A11A8VSSA6A2VDDBA1RAS#

S1#

DUVSSDQ36VDDDQ38VSSDQ39VDDDQ41

VSSDQ42VDDVSSDQ48VDDDQS6VSSDQ51VDDDQ57VSSDQ58VDDSDAVDD_SPDVDD_ID

DQ45DM5VSSDQ46VDDCK1#

CK1DQ52VDDDQ54VSSDQ55VDDDQ61DM7VSSDQ62VDDSA0SA2DU

DDR_F_SCAS#<12>DDR_F_SRAS#<12>

DDR_F_SMA3

DDR_F_SMA10

DDR_F_SMA11DDR_F_SMA8

DDR_F_SMA6

DDR_F_SMA2

DDR_F_SBS0

DDR_F_SBS1DDR_F_SRAS#

DDR_DQ34

DDR_DQ44DDR_DQ39

DDR_DQS5DDR_DQ45

DDR_DQ46

DDR_DQ41

DDR_DQ42

DDR_DQ47DDR_DQ43DDR_DQ40

DDR_DQ48

DDR_DQ52

DDR_DQ54DDR_DQS6

DDR_DQ50

DDR_SBS0DDR_SWE#

DDR_SRAS#

DDR_SBS1

DDR_SMA9DDR_SMA12

DDR_SMA11DDR_SMA8

DDR_SMA5

DDR_SMA4DDR_SMA7

DDR_SMA6

DDR_SMA2DDR_SMA3

DDR_DQ58

DDR_F_SWE#

DDR_DQ59

DDR_SBS0DDR_SWE#

414549535761656973778185899397101105109113117121125129133137141

261014182226303438

424650545862667074788286909498100104108112116120124128132136140144145

149153157161165169173177181185189193197

146150154158162166170174178182186190194198

VREFVSSDQ1VDDDQS0DQ2DQ3VDDDQ9DQS1VSSDQ10VDDCK0CK0#

VSS

DQ16VDDDQS2VSSDQ19VDDDQ25VSSDQ26VDDCB0VSSDQS8CB2VDDCB3DUVSSCK2#

VDDCKE1DU/A13A12A9VSSA7A3VDDA10/APBA0WE#

S0#

DUVSSDQ32VDDDQS4VSSDQ35VDD

VREFVSSDQ5VDDDQ6DQ7DQ12VDDDQ13DM1VSSDQ14VDDVSS

DQ20VDDDQ22VSSDQ23VDDDQ29DM3VSSDQ30VDDCB4VSSDM8CB6VDDCB7DU/RESET#

VSSVDDCKE0DU/BA2A11A8VSSA6A2VDDBA1RAS#

S1#

DUVSSDQ36VDDDQ38VSSDQ39VDDDQ41

VSSDQ42VDDVSSDQ48VDDDQS6VSSDQ51VDDDQ57VSSDQ58VDDSDAVDD_SPDVDD_ID

DQ45DM5VSSDQ46VDDCK1#

CK1DQ52VDDDQ54VSSDQ55VDDDQ61DM7VSSDQ62VDDSA0SA2DU

RP15 4P2R_56

1423

RP85 4P2R_56

1423

RP14 4P2R_56

1423

RP86 4P2R_56

1423

RP87 4P2R_56

1423

RP95 4P2R_56

1423

RP88 4P2R_56

1423

RP96 4P2R_56

1423

RP97 4P2R_56

1423

RP99 4P2R_56

1423

RP98 4P2R_56

1423

RP102 4P2R_56

1423

RP103 4P2R_56

1423

RP100 4P2R_56

1423

RP101 4P2R_56

1423

RP104 4P2R_56

1423

RP105 4P2R_56

1423

RP106 4P2R_56

1423

RP107 4P2R_56

1423

RP93 4P2R_56

1423

RP72 4P2R_56

1423

R142 56_0402

RP90 4P2R_56

1423

RP69 4P2R_56

1423

RP91 4P2R_56

1423

RP70 4P2R_56

1423

RP71 4P2R_56

1423

RP92 4P2R_56

1423

R160 56_0402

RP13 4P2R_56

1423

RP110 4P2R_56

1423

RP12 4P2R_56

1423

RP108 4P2R_56

1423

RP11 4P2R_56

1423

C111.1UF_0402_X5R

C102.1UF_0402_X5R

C99.1UF_0402_X5R

C119.1UF_0402_X5R

C121.1UF_0402_X5R

C120.1UF_0402_X5R

C113.1UF_0402_X5R

C76.1UF_0402_X5R

C100.1UF_0402_X5R

C104.1UF_0402_X5R

C103.1UF_0402_X5R

C300.1UF_0402_X5R

C301.1UF_0402_X5R

C326.1UF_0402_X5R

C298.1UF_0402_X5R

C325.1UF_0402_X5R

C304.1UF_0402_X5R

C324.1UF_0402_X5R

C332.1UF_0402_X5R

C297.1UF_0402_X5R

C294.1UF_0402_X5R

C250.1UF_0402_X5R

C305.1UF_0402_X5R

C331.1UF_0402_X5R

C306.1UF_0402_X5R

C293.1UF_0402_X5R

C253.1UF_0402_X5R

C251.1UF_0402_X5R

C114.1UF_0402_X5R

C311.1UF_0402_X5R

C309.1UF_0402_X5R

C308.1UF_0402_X5R

C312.1UF_0402_X5R

C310.1UF_0402_X5R

C315.1UF_0402_X5R

C319.1UF_0402_X5R

C329.1UF_0402_X5R

C316.1UF_0402_X5R

C318.1UF_0402_X5R

C314.1UF_0402_X5R

C328.1UF_0402_X5R

C317.1UF_0402_X5R

C291.1UF_0402_X5R

C296.1UF_0402_X5R

C115.1UF_0402_X5R

C292.1UF_0402_X5R

C284.1UF_0402_X5R

C322.1UF_0402_X5R

C286.1UF_0402_X5R

C323.1UF_0402_X5R

C287.1UF_0402_X5R

C288.1UF_0402_X5R

1 1

Place Crystal within 500 mils of CK_Titan

caps are internal

to CK_TITAN

Width=40 mils

*BLM21A601SPT

Note:

CPU_CLK[2:0] needs to be running in C3, C4.

Please closely pin42

200Mhz Host CLK 133Mhz Host CLK

Place resistor near R184,R185 ;Trace

CLKPCI_LANCLK_ICH14M

CLK66MCH

CLK_HT

BSEL0H_BSEL0

+3VS+3VS

R2151 233.2_1%

R2191 233.2_1%

C381 @10PF_0402

12

C3802 1@10PF_0402

Y214.318MHZ

+

C13222UF_10V_1206

C388.1UF_0402

C364.1UF_0402

C385.1UF_0402

C139.1UF_0402

C137.1UF_0402

C382.1UF_0402

C386.1UF_0402

L21BLM21A601SPT

C393.1UF_0402

R631K_0402

R57 1 2@10K_0402R64 1 2 0_0402

2

4054

2553

4852

5124

2321

75

18161210

XTAL_IN

SEL2SEL0

3V66_0/DRCG3V66_1/VCH_CLK

IREF

CPUCLKT2

CPU_CLKC2CPUCLKT1

CPUCLKC1CPUCLKT0

CPUCLKC066MHZ_IN/3V66_5

66MHZ_OUT2/3V66_466MHZ_OUT0/3V66_2

PCICLK_F2PCICLK_F0

PCICLK6PCICLK4PCICLK2PCICLK0

48MHZ_USB

48MHZ_DOT

L45BLM21A601SPT

R611K_0402

C138.1UF_0402

L48BLM21A601SPT

C13310UF_10V_1206

C39610UF_10V_1206

AGP_SBA6AGP_SBA2

AGP_SBA5AGP_SBA1AGP_ST0

3VDDCCL

AGP_AD30

AGP_AD26

AGP_AD31AGP_C/BE#3

AGP_AD24

AGP_AD25

AGP_C/BE#2AGP_AD23

AGP_AD19AGP_AD22

AGP_AD18

AGP_AD8AGP_AD12

AGP_C/BE#1

AGP_AD13AGP_AD9

AGP_AD15AGP_AD11

AGP_C/BE#0AGP_AD7

AGP_AD3AGP_AD0

INVPWR_B+

+2.5V

+3V+5V

+5VALW+5VS+1.5VS+12VALW

C1533.3PF

C83.3PF

L1FBM-11-160808-121

R694.7K_0402

C227PF

C145.1UF_0402

C13.3PF

R40_0402

R210K_0402

S

Q2SI2302DS

2

GD

S

Q82N7002

2

R747K_0402

1591115192327313539434751555963677175798387919599101105109113117121125129133137

GND48101418GND2428323640GND4448525660GND64687276GND8286909498GND102106110114118GND122126130134138GND

GND37111519GND2327313539GND4347515559GND63677175GND8185899397GND101105109113117GND121125129133137GND

C217.1UF_0402

C218.1UF_0402

C224.1UF_0402

C220.1UF_0402

C216.1UF_0402

C219.1UF_0402

C221.1UF_0402

R81100K_0402

C168.1UF_0402

GD

S

Q42N7002

2

R7875K

S

Q52N7002

2

R8010K_0402

HubLink Interface VSS

AC'97 Interface Interface LPC

Interface

Interface CPU

Interface System Managment

Interface Interrupt GPIO

unMUX Geyserville

Power Management

Place closely to ICH3-M

Place closely to

ICH3-M

Close to ICH3-M.

HUB Interface VSwing Voltage

1 Place R_G and R_H in middle of Bus.

HUB_PD5

AD14AD9

PM_STPPCI#

HUB_PD0

AD26AD20AD17AD11AD7

H_FERR#

AD22

HUB_PD9HUB_PD3AD31

CLK_ICHPCI

HUB_PD6HUB_PD1

CLK_ICH48 RTC_RST#

AD18

AD5AD0

IAC_BITCLK SDATA_IN0 SDATAO

GPIO5

+RTCVCC

+RTCVCC

+ICH_HUBREF+VS_HUBVSWING

+CPU_CORE

+1.8VS

+VS_HUBVSWING

+3VS+3VALW

+3VALW

+3VS

+3VS

+3VS+3VALW

+3VS

+1.8VS

+ICH_HUBREF+3VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC

R295 36.5_1%

R2251K_0402

C476.01UF_0402

C470.01UF_0402

J1JOPEN

C4081UF

K2N1

A4D2B4

D3F4R4E4

U22W23Y21AA23AA21J22AB22V23Y22AC5AB5AC4AB2AC3Y6H1L5W1M1G5B3D4F1M3T5

U23Y23W21

L22M21N20R22T23M19P19

PCI_C/BE#0PCI_C/BE#2

PCI_GNT#0PCI_GNT#2PCI_GNT#4

PCI_REQ#0PCI_REQ#2PCI_REQ#4

CPU_RCIN#

CPU_PWRGOODCPU_NMICPU_INTRCPU_INIT#

R2591 10K_04022

D22

RB751V

21

D29

RB751V

21

R26533_0402

C45415PF

Q32

3904

231

R318300_0402

R333470_0402

R280301_1%

Disable Timeout feature

0=I2C CTRL CPUVID select

1=Bus switch CPUVID select

1 0

Note:

R376=22.6_1% for B0(QB63 part) R376=18.2_1% for B0(QB62 & SL5LF part)

Closely Pin AB6

PDD0

PDD9

SDD11

PDD6PDD2

SDD8SDD0

SDD6

PDD11

SDD4VCC5REF

SDD3

PDD5USBP0-

AV_VID4

USBP0+

PDD4

SDD7PDD10

+VCC_RTC+V1.8_ICHLAN+1.8VALW

+3VS

+3VALW+1.8VS

+3VS

+RTCVCC+VCC_RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC

D171SS355

C5091UF

C418.1UF_0402

R2001K_0402

R34718.2_1%

R341100K_0402

R3710_0402

R3610_0805

R3760_0805

R3740_0805

R3690_0805

C5341 5PF_04022

C5351 5PF_04022

C539.1UF_0402

E12C12A12

H20F21G19E21G23F23G21E23

B21

AC15AC21

AA14AA15AA19

W12AB11AC10W11Y9AB9AC9Y10W9Y11AB10AA11

Y17W17AC17W16Y14AA13W15Y16AC16AA17Y18AC18Y13AB12AC13Y12AA18AB19H23

E13 K12 V6 F15 F7 K10 AB6 E6 C13 F9 P14 V22 C23 B23 E7 D6 C2 A21 F6 H6 M10 T6 G18 P12 V16 V18 J18 R18

U19

F17K14

E10V8

E11 K18 P18 V14

E14 E18 E20 G3 H19 J5 K13 K21 K23 L10 L12 L14 L23 M12 M20 N5 N11 N13 N21 P11 P20 R3 R21 T4 T22 AC23 W6 W10 W18 Y8 AA8 AA16 AB8 AC8

USB_PP0USB_PP2USB_PP4USB_PN#0USB_PN#2USB_PN#4

USB_OC#0USB_OC#2USB_OC#4

USB_LEDA#0/GPIO32USB_LEDA#2/GPIO34USB_LEDA#4/GPIO36USB_LEDG#0/GPIO38USB_LEDG#2/GPIO40USB_LEDG#4/GPIO42

USB_RBIAS

IDE_PDCS1#

IDE_SDCS1#

IDE_PDA0IDE_PDA2IDE_SDA1

IDE_PDD0IDE_PDD2IDE_PDD4IDE_PDD6IDE_PDD8IDE_PDD10IDE_PDD12IDE_PDD14

IDE_SDD0IDE_SDD2IDE_SDD4IDE_SDD6IDE_SDD8IDE_SDD10IDE_SDD12IDE_SDD14

IDE_PDDACK#

IDE_PDDREQIDE_PDIOR#

IDE_PDIOW#

IDE_PIORDYSPKR

VCC_SUS0 VCC_SUS2 VCC_SUS4

VCC_USB0/VCC_SUS6 VCC_AUX0/VCCLAN1_8 VCC_AUX2/VCCLAN1_8

VCCPSUS0VCCPSUS2

VCCCORE0 VCCCORE2 VCCCORE4 VCCCORE6

U21

@74AHCT1G125GW

24

C398.1UF_0402

VCC1.8SUS

+3VS+3VS

R2501 2 10K_0402R2521 2 10K_0402

C434.1UF_0402

+

C4401UF

C453.1UF_0402

C41247PF_0402

C51247PF_0402

C49947PF_0402

C416.1UF_0402

+

C53322UF_10V_1206

C505.1UF_0402

C504.1UF_0402

C459.1UF_0402

C503.1UF_0402

C527.1UF_0402

+

C40622UF_10V_1206

C423.1UF_0402

C54147PF_0402

C460.1UF_0402

C421.1UF_0402

C52847PF_0402

C457.1UF_0402

C407.1UF_0402

C546.1UF_0402

C502.1UF_0402

C526.1UF_0402

+

C54522UF_10V_1206

C524.1UF_0402

C537.1UF_0402

C538.1UF_0402

35

RP121

10P8R_8.2K

10971

35

RP119

10P8R_8.2K

10971

35

R367 @8.2K_0402

C487.1UF_0402

C45533PF_0402

C482.1UF_0402

C445.1UF_0402

C497.1UF_0402

C46633PF_0402

C432.1UF_0402

+

C458100UF_D2_6.3V

C519.1UF_0402

C540.1UF_0402

C525.1UF_0402

R224 10K_0402

R2201 2 4.7K_0402R2281 2 4.7K_0402

R3111 2 10K_0402R3751 2 10K_0402

C52210UF_6.3V_P

Placea caps near CDROM CONN.

Correct HDD pin define ,pls update layout

RSDDACK#

SDD10

SDD0SDD5

SDIORDY

SDD2

SDD15SDDREQSDD9

+5VS+5VS

C1101UF_25V_0805

C257.1UF_0402

C136.1UF_0402

C3691000PF_0402

C520.1UF_0402

C536.1UF_0402

C5231UF_25V_0805

C2581000PF_0402

135

C36710UF_16V_1206

C52910UF_16V_1206

C9610UF_16V_1206

R188470_0402

+5VINDEX+5VDRIVE SELECT+5VDISK CHANGENCREADYDENSITY OUTMOTOR ONNCDIRECTIONDENSITY 2STEPGND / NCWRITE DATAGNDWRITE GATEGNDTRACK 00

NC / GNDWRITE PROTECTGNDREAD DATAGNDSIDE 1 SELECT

R3361 @0_04022R335 0_0402

C11610UF_16V_1206

C2621000PF_0402

C263.1UF_0402

C1121UF_25V_0805

314

7

R62100K_0402

C3331 247PF_0402

C33747PF_0402

C2801 247PF_0402

R176100K_0402

C359.01UF_0402

S

Q222N7002

2

Q23SI2301DS

13