Development board for the icycam soc

The IcyCAM MiniPack includes – A PCB motherboard called IcyBoard – A daughter board on which IcyCAM is mounted – Power management, switches, LED, USB interfaces to a PC – Eclipse IDE wit

Master Project

Development Board for the IcyCAM Soc

Tuan-Thanh VU Supervisor: René Beuchat External Expert: Edoardo Franzi

Jan 2011

Table of Contents

Table of Contents i

List of Figures iii

List of Tables iv

Acknowledgments v

1 Introduction 1

1.1 IcyCAM Soc [1] 1

1.2 Project’s Objectives 3

2 System Architecture 5

2.1 Minimum Configuration 5

2.2 Complete Configuration 6

2.3 Decision for the development board 7

2.3.1 The ARM Cortex-M3 based microcontroller 7

2.3.2 The CPLD 8

3 Development board for IcyCAM and ARM Cortex-M3 9

3.1 Schematic Design 9

3.1.1 System Block Diagram 9

3.1.2 Power 9

3.1.3 Altera MAX II 10

3.1.4 ARM Cortex-M3 based STM32 microcontroller 11

3.1.5 Common Devices 12

3.1.6 Pseudo Static RAM 13

3.1.7 FTDI USB to JTAG 15

3.1.8 FTDI USB to FIFO 15

3.1.9 IcyCAM Daughter Connectors 16

3.2 Layout Design 17

4 Configuring the Altera MAX II 18

4.1 Bus control for common devices 18

4.2 PPI to FTDI FIFO and PSRAM Controller 20

4.3 Serial EEPROM multiplexer 21

4.4 Result 21

5 Software Development 22

5.1 Software development for STM32 microcontroller 22

5.2 Software development for IcyCAM 22

5.3 Demonstration Application 23

6 Conclusion 24

7 References 25

8 Annexes 26

8.1 Configuring PSRAM operation mode 26

8.2 Yagarto, OpenOCD and Eclipse for the STM32 27

8.3 IcyCAM Parallel Peripheral Interface Bridge 31

8.4 SD Card direction control in the CPLD 33

8.5 Modifications for the IcyCAM Minipack software 34

List of Figures

Figure 1.1 : The new development board with the IcyCAM sensor board 1

Figure 1.2: The IcyCAM Soc Block Diagram 2

Figure 1.3 : IcyCAM Soc Specifications 2

Figure 1.4: The CSEM IcyBoard and the IcyCAM sensor board 3

Figure 1.5: Block Diagram of the IcyCAM MiniPack 3

Figure 2.1: The minimum configuration for IcyCAM development board 6

Figure 2.2: The complete configuration for IcyCAM development board 7

Figure 3.1: System Block Schematic 9

Figure 3.2 : Porwer supply block diagram 10

Figure 3.3: Configuring the CPLD 11

Figure 3.4: Common Elements 13

Figure 3.5: 8Mi x 16b PSRAM Function Block Diagram [5] 14

Figure 3.6: USB to JTAG and UART using FTDI 4232H 15

Figure 3.7: IcyCAM GPIOs and PPI to FTDI FIFO 16

Figure 3.8: Interaction between IcyCAM sensor board and the CPLD 16

Figure 3.9: TOP Layer 17

Figure 3.10: BOTTOM Layer 17

Figure 4.1: Function Block Diagram of Altera MAX II device 18

Figure 4.2: STM32 and IcyCAM GPIO to common elements 19

Figure 4.3: Common device access timing diagram 20

Figure 4.4: PPI to FDTI FIFO and PSRAM controller block diagram in the MAX II 20

Figure 4.5: SPI multiplexer for serial EEPROM on IcyCAM daughter board 21

Figure 5.1 : Softwrare development process 22

Figure 5.2: Software Configuration 1 23

Figure 5.3: Software Configuration 2 23

Figure 8.1 : Configuration Register WRITE, Asynchronous Mode 26

Figure 8.2: Configuration Register WRITE, Synchronous Mode 26

Figure 8.3 : Load Configuration Register 27

Figure 8.4 : The IcyCAM PPI to PSRAM controller timing diagram 32

Figure 8.5 : The IcyCAM PPI to FTDI FIFO timing diagram 33

Figure 8.6: micro SD Card multiplexer 33

Figure 8.7 : SDIO Command direction control timing diagram 34

List of Tables

Table 3.1 : Power Consumption of Components 10

Table 3.2 : MAX II Family Features [3] 11

Table 3.3 : ARM Cortex-M3 based Microcontrollers comparision 12

Table 3.4 : PSRAM internal control registers [5] 14

Table 4.1 : Common devices address 19

Acknowledgments

I would like to express my gratitude to:

My supervisors – René Beuchat at Processor Architecture Laboratory – EPFL Though his valuable guidance, I have obtained relevant research skills as well as followed the right research direction

My parents and my friends who have understood and shared with me joys and

1 - INTRODUCTION

1 Introduction

Nowadays, a lot of vision applications are developed in many fields Most of usual applications do not work well with a high dynamic range of illumination because their data representation is linear with the environment illumination Moreover, they are often complicated designs including separated camera sensor, graphic processing unit and a micro-computer to control the whole system The IcyCAM Soc from CSEM (Swiss Center for Electronics and Microtechnology) provides a complete solution for these applications in an intra-scene dynamic range environment with a single chip With the help from CSEM, the main objective of this master project is to design a development board to explore different applications for this new and advanced Soc This new development board can be a Multiprocessor Embedded System with many development device and interfaces (minis SD Card, USB, CAN, SPI, I2C, etc…) to perform complex vision systems This section will make a resume on the IcyCAM Soc and the project’s objectives

Figure 1.1 : The new development board with the IcyCAM sensor board

1.1 IcyCAM Soc [1]

The IcyCAM Soc integrates a high dynamic range QVGA (320x240) monochrome camera

sensor, a 32-bit DSP/MCU icyflex1 with 64-bit memory bus, 128 KiB of SRAM together

with several peripheral interfaces on a single chip With a specific time-domain logarithmic encoding, the IcyCAM Soc gives higher quality images than original logarithmic representations in intra-scene dynamic range aspect Moreover, the images can be represented

in contrast magnitude and direction so that the system can make some vision analyses In addition, the graphic processing unit reduces workload for the icyflex1 in specific graphic tasks Figure 1.1 and Figure 1.2 show the block diagram and the key characteristics of this Soc

The main features of the IcyCAM Soc are listed below For more detail, refer to the Soc specification

1 - INTRODUCTION

– High dynamic range QVGA (320x240) pixel array

– 32-bit DSP / MCU icyflex1 processor

– DMA function, 64-bit data bus

– Contrast and Orientation computation in the data readout path

– Graphical Processing Unit (GPU)

– 32-bit 100 MHz SDRAM interface

– 12-bit Parallel Peripheral Interface (PPI)

– 2 Serial Peripheral Interfaces (SPI)

– 16-bit General Purpose I / O Interface (GPIO)

– UART interface

– JTAG interface

– Programmable in C (GNU tool suite)

– Max system clock rate: 33 MHz

Figure 1.2: The IcyCAM Soc Block Diagram

Figure 1.3 : IcyCAM Soc Specifications

1 - INTRODUCTION

To help developers getting start with this new Soc, CSEM provide the smallest development board called the IcyCAM MiniPack accompanied with development tools The IcyCAM MiniPack includes

– A PCB motherboard called IcyBoard

– A daughter board on which IcyCAM is mounted

– Power management, switches, LED, USB interfaces to a PC

– Eclipse IDE with CDT C/C++, GNU C/ASM Compiler for icyflex1 plug-in

Figure 1.4 shows the real view of this kit, and the block schematic of the IcyBoard is illustrated in next figure

Figure 1.4: The CSEM IcyBoard and the IcyCAM sensor board

Figure 1.5: Block Diagram of the IcyCAM MiniPack

1.2 Project’s Objectives

The objective of this master project is to expand the IcyCAM MiniPack to a complex vision system which is based on the IcyCAM Soc One of the applications is called “last minute images” that can store pictures from the IcyCAM Soc into a SD Card so that we can review the environment images offline for security, surveillance purposes Moreover, the system should have capability to communicate with other systems to increase its functionality

According to the objectives, following tasks were proposed and finished during the master project time:

- Investigate the system architecture and software development of the IcyCAM Soc as well as the MiniPack

1 - INTRODUCTION

- Propose and decide system architecture for the new design

- Design PCB schematic and layout of the development board using Altium Design

Summer 09 – a well-known tool for electrics design

- Test the implemented PCB

- Develop demonstration applications

The four next sections will describe the works that have been done during the project They include system architecture, schematic and layout design, hardware configuration and software development

2 - SYSTEM ARCHITECTURE

2 System Architecture

In order to explore the applications of the IcyCAM Soc in embedded system world, some development configurations which inherit from MiniPack are proposed and studied in architecture, advantages, disadvantages, available components and applications Then a final configuration is chosen for further design step

The IcyCAM sensor board from CSEM is a very nice design To reuse this module, there are two connectors so that the daughter board can be plugged in or removed from the main board This reduces workload and risks for the design and mounting process

One of the main features of the development board is to allow the captured images from the IcyCAM Soc to be saved in a SD Card Hence, we can retrieve image offline when IcyCAM

is not working This board can be used in surveillance applications to store last-minutes (hours) environment pictures Thus, the proposed architectures have to be cared about SD Card connection as well as access speed

According to the requirements, two possible configurations were proposed:

The idea is to design a small board with very low power consumption The first solution can

be a derivation of the IcyCAM MiniPack with some enhanced connections to mini SD Card and SPI connectors The same to the IcyCAM MiniPack, this architecture has two main components FTDI USB2FIFO and Altera CPLD It can connect to a PC via USB cable so that we can retrieve pictures and debug IcyCAM Soc The SPI, UART connectors allow the board to communicate with other systems Figure 2.1 presents architecture of this configuration

Since the IcyCAM Soc does not have a SD Card interface, we must connect its SPI to SD Card and operate in SPI mode The maximum SPI clock frequency (in the IcyCAM Soc) of 16MHz is a disadvantage Therefore, it only allows storing 10-15 frames/second (with 320x240x10bit frame) In addition, without any specific computational device, all processing will be done in the icyflex1 We have to implement FAT File System, SPI mode for IcyCAM Soc This also affects the frame rate and other graphic processing With this configuration, it could not be a complete system for diversified applications The next architecture which is more complicated will solve problems

SPI Aardvark Connector

EEPROM

SPI2 SDRAMC

SDRAM

UART

FTDI 2232H

IcyCam

USB Connector

Power Management

CPLD

LED DIP SWITCH Rotate

CPLD JTAG Connector

IcyCAM JTAG Connector

External Power

IcyCAM

RS232 Connector SPI

The CPLD helps the IcyCAM Soc access the SRAM by implementing Parallel Peripheral Interface (PPI) to SRAM controller Therefore, the captured images can be stored in SRAM with high frame rate The board may form a shared memory multi-processor application The workload now is shared between two processors The IcyCAM Soc captures images, makes some graphic processing then stores them in the shared memory Another processor read the images from memory write to SD-Card with high speed SDIO interface - four times faster than SPI mode

In additions to the PSRAM, both processors will share common devices (including LEDs, switches, rotary switch, external GPIOs) The CPLD provides bus controller and multiplexers These bus controller and multiplexer will decide which microcontroller will access to the shared peripheral devices

A FTDI 4232H which has four USB to multi-purpose interfaces is integrated to the configuration to provide debug capability for both the icyflex1 and the ARM Cortex-M3 core through two USB to JTAG channels Two remain channels can be used for virtual COM port

so that both microcontrollers can communicate with a PC through UART interface To inherit from IcyCAM MiniPack, the FTDI 2232H is kept However, the IcyCAM Soc can

USB Connector

Power Regulator

CPLD

ARM Cortex-M3

EBI

SRAM (SDRAM)

SPI or SDIO Switch uSD

SPI1 SD

GPIO

LED (8) SWITCH (8)

JTAG2USB JTAG

USB Connector

SPI2

UART

I2C USB

USB Connector Ext Connection

Rotate Switch

ARM uController

Ext IO Port (4 ports)

CPLD JTAG ICYCAM

MAX232

Figure 2.2: The complete configuration for IcyCAM development board

2.3 Decision for the development board

The final decision for next design steps is the complete solution which consists of another processor to explore different applications for the IcyCAM Soc

2.3.1 The ARM Cortex-M3 based microcontroller

The enhanced microcontroller provides simple processing and performs communication channels between the IcyCAM Soc and other systems Therefore, the design requires a low-

2 - SYSTEM ARCHITECTURE

power, low-voltage one accompanied mid-level performance instead of a very high speed and powerful device Then the ARM Cortex-M3 core is suitable for these reasons It is a well-know mid-range micro-computer for embedded system, easy to be developed with simple and open tools Moreover, there are a lot of available libraries and applications which have been developed for the ARM Cortex-M3 based microcontroller Hence, the development time can

be reduced significantly

2.3.2 The CPLD

The CPLD is one of the key components of the MiniPack from CSEM It makes the system flexible Therefore, this device is maintained in the new development board so that the board can be operated in different setting by reconfiguring the CPLD Most of standard interfaces

of the two microcontrollers are connected to the CPLD in order that the communication between IcyCAM and the ARM core can be set up

The CPLD provides below main functions:

- Bus Control to access common shared devices

- PPI (Parallel Peripheral Interface) to FTDI FIFO bridge

- PPI to PSRAM controller bridge

- Multiplexer for accessing Flash EEPROM (on IcyCAM daughter board)

- Multiplexer for mini SD-Card

3 – DEVELOPMENT BOARD

3 Development board for IcyCAM and ARM Cortex-M3

After making decision on the complete configuration, the next important task is to design schematics and layout for the board by using Altium tool Thanks to the IcyCAM MiniPack from CSEM and NRTR project [2] from HEPIA from which some parts of the schematics are referenced These projects help me reduce time to design library for components as well as their footprint This section will explore the schematic of the chosen configuration from system block diagram to each module, technical information about implemented PCB

3.1 Schematic Design

3.1.1 System Block Diagram

The board schematic is derived from the complete configuration The center is an Altera MAX II CPLD From the CPLD, connections are routed to the ARM based microcontroller, the IcyCAM Soc connectors, a FTD4232 chip, a FT2232 chip, a 8Mi x 16b PSRAM (or CellularRAM), mini SD connector and other common devices Figure 3.1 shows the system schematic of the design

STM32 (ARM Cortex-M3 based)

8Mi x 16b PSRAM

FTD2232 (FIFO2USB)

USB

UART

JTAG

USB mini Connector

USB mini Connector

USB mini Connector

Power Regulator

3 – DEVELOPMENT BOARD

converters to provide 3.3 Volt and 1.8 Volt for the whole board Figure 3.2 illustrates the power supply block diagram

ON/OFF CIRCUIT

TPS62111 DC/DC Converter

3.3V

1.8V

MAX1973 DC/DC Converter

Figure 3.2 : Porwer supply block diagram

Since the system consists of different components, it is necessary to collect voltages and currents used by components on the board Table 3.1 summarizes the maximum power consumption of some main components

Table 3.1 : Power Consumption of Components

IcyCAM Soc (digital) 1.8V 40mA @30fps

IcyCAM Soc (analog) 3.3V 4mA @30fps

SDRAM (IcyCAM daughter board) 3.3V 135mA

EEPROM (IcyCAM daughter board) 3.3V 25mA

3.1.3 Altera MAX II

The CPLD which makes the development reconfigurable is one of the main components Most of I/O interfaces from the IcyCAM Soc and the ARM microcontroller are connected to

it so that the communication bridges between them can be flexibly configured

An Altera MAX II CPLD is selected for its low power and low cost feature With 1.8-V core,

it reduces power consumption and increases reliability, allows longer time if a battery is used The internal clock frequency can be up to 300 MHz With real-time in-system programmability, it allows to download new configuration while the CPLD is operational The MAX II can interface with multi-volt IO devices with programmable drive strength and pull-up or pull-down resistors The popular Quartus II software makes it easy to develop and reduces design time For more detail on this CPDL, please refer Altera website

http://www.altera.com Table 3.2 describes available CPLDs in MAX II family

EPM1270 EPM1270G

EPM2210 EPM2210G

EPM240

Z

EPM57 0Z

UFM Size (bits) 8,192 8,192 8,192 8,192 8,192 8,192

The EPM2210G is selected for this development board so that we can design some controllers such as PPI to PSRAM controller and PPI to SDIO controller For multiplexer and switch purposes, it does not require such a high capacity CPLD

To configure the CPLD, a USB-Blaster is used The IcyCAM Configuration board which contains Aardvark SPI, Amontex JTAG and USB Blaster JTAG connectors is used to connect USB Blaster with the development board so that we can use Quartus II tool to configure the CPLD through USB Blaster in JTAG mode (Figure 3.3)

MAX II CPLD CPLD JTAG,

SPI Connector

IcyBoard_USB Adapter

USB Blaster

External Bus USB Cable

Dev Board

Figure 3.3: Configuring the CPLD

3.1.4 ARM Cortex-M3 based STM32 microcontroller

There are several vendors for the ARM Cortex-M3 based microcontrollers A small investigation was made to collect information about available microcontrollers Table 3.3 summarizes main features of some ARM Cortex-M3 based microcontrollers

From these options, microcontrollers which have a SDIO and external memory interface are high priority Finally, the STM32F103ZE device from ST is chosen which combine high performance with first-class peripherals and low-power, low-voltage operation [4] It consists

of following features:

- The ARM Cortex-M3 32-bit RISC processor @72MHz max

- 512KiB Flash ROM, 64KiB SRAM

- Flexible Static Memory Controller (FSMC)

- 8x16-bit Timers, 2xWDT, RTC

- 21x12-bit ADC channels, 2x12-bit DAC channels

- 3xSPI, 3xUSART (irDA), 2xUART, 2xI2C, 2xI2S

- SDIO, CAN, USB

LPC176x NXP 100 120 512 64 USB; UART; SPI; I2C; I2S; CAN;

Ethernet; ADC; Timer; RTC; DAC

0 2.4-3.6 ST32F107x ST 100 72 256 64 USB; UART; SPI; I2C; I2S; CAN;

Ethernet; ADC; Timer; RTC; DAC

0 2.0-3.6 ST32F103x ST 144 72 1024 96 USB; UART; SPI; I2C; I2S; CAN;

SDIO; ADC; Timer; RTC

64MB SRAM

2.0-3.6 LM3S97xx TI 100 80 128 64 USB; UART; SPI; I2C; I2S; CAN;

Ethernet; ADC; Timer; RTC

64MB SDRAM

3.0-3.6 LM3S9Bxx TI 100 80 256 96 USB; UART; SPI; I2C; I2S; CAN;

Ethernet; ADC; Timer; RTC

64MB SDRAM

3.0-3.6 LM3S99xx TI 100 80 256 64 USB; UART; SPI; I2C; I2S; CAN;

Ethernet; ADC; Timer; RTC; DAC

0 3.0-3.6 ATSAM3U Atmel 144 96 256 48 USB; UART; SPI; I2C; I2S; SDIO;

ADC; Timer; RTC

16MB SRAM

1.6-3.6

This component integrates a SDIO interface so that the board can access the SD Card in high speed The Flexible Static Memory Controller which can be configured as a PSRAM (pseudo static RAM or cellular static RAM) controller allows data can be written to and read from a PSRAM in burst transfer instead of asynchronous mode The integrated USB device interface makes the development board become a USB to SD Card reader or an IcyCAM webcam and other high-speed data transfer applications Besides, this microcontroller also consists of many standard interfaces to increase communication channels

From available interfaces, some of them are connected to the MAX II in order that the microcontroller can access to common devices as well as the IcyCAM Soc, others are linked

to an extension connector so that we can connect the board with specific external modules (RF, Ethernet, etc…) Figure 3.1 shows the connections between the STM32F103ZE with other components

3.1.5 Common Devices

The design consists of shared devices that are used as input and output elements for development purposes They are a hexadecimal rotary switch, 8-DIP switches, 8 LEDs, 4 GPIO pins All of them are connected directly to the CPLD so that we can select which microcontroller can access them This makes the system become an independent development board for each processor Figure 3.4 illustrates the connections between the CPLD and these common devices

Figure 3.4: Common Elements

To access these devices from the IcyCAM Soc and the STM32, a pseudo bus is proposed by CSEM which includes address, data and control signals The section 4.1 will explore the detail of this bus interface in the CPLD

3.1.6 Pseudo Static RAM

In order to enhance memory capacity for the ARM core, an external memory module is required Since the STM32 does have dynamic RAM controller, the high capacity DRAM cannot be used in this design Fortunately, the Flexible Static Memory Controller (FSMC) of the STM32 can be configured to a Pseudo Static RAM (PSRAM) controller This specific PSRAM can operate in either asynchronous or synchronous mode with the DRAM core inside (Figure 3.5) Specially, with synchronous mode it allows to read or write one 16-bit word per one clock cycle in burst transfer The MT45W8MW16GX from Micron consists of following key features [5]:

- Supports asynchronous, page, and burst operations

- Capacity: 8Mi x 16bit

- Asynchronous random access time: 70ns

- Burst mode READ and WRITE access

o 4, 8, 16, or 32 words, or continuous burst

o Burst wrap or sequential

o MAX clock rate: 133 MHz (tCLK = 7.5ns)

o Burst initial latency: 35ns (5 clocks) at 133 MHz

- Low power consumption

o Asynchronous READ: <25mA

o Initial access, burst READ: (37.5ns [5 clocks] at 133 MHz) <45mA

o Continuous burst READ: <40mA

3 – DEVELOPMENT BOARD

o Standby: <50μA (TYP at 25°C)

o Deep power-down: <3μA (TYP)

Figure 3.5: 8Mi x 16b PSRAM Function Block Diagram [5]

By default, the memory operates in asynchronous mode thus it must be configured before synchronous mode is activated The MT45W8MW16GX contains some internal registers so that the operation mode can be set up by specific procedures Table 3.4 gives a short description for each of them

Table 3.4 : PSRAM internal control registers [5]

Bus Configuration Register (BCR) The BCR defines how the memory device interfaces with the

memory bus including operation mode, latency, WAIT configuration, drive strength, burst length and burst wrap Refresh Configuration Register

From the STM32, there is a GPIO pin connects to PSRAM’s CRE pin so that we can configure the operation mode of the PSRAM before the FSMC take the control of the memory Otherwise, we can use FSMC to perform software configuration operation

Not only the STM32 but also the IcyCAM Soc can access the CellularRAM By implementing Parallel Peripheral Interface to PSRAM controller in the CPLD, the IcyCAM