ARM Architecture Reference Manual- P22

Vectors When the LEN field of the FPSCR indicates scalar mode vector length 1, FABSD performs just one absolute value operation, and vec_len=1, Dd[0]=Dd, and Dm[0]=Dm.. Vectors When th

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Absolute value function

The function abs(x) means a copy of x with its sign bit forced to zero, as defined in the Appendix to the IEEE 754-1985 standard

Flush-to-zero mode

The FZ bit of the FPSCR does not affect the operand or result of this instruction

Vectors When the LEN field of the FPSCR indicates scalar mode (vector length 1), FABSD performs

just one absolute value operation, and vec_len=1, Dd[0]=Dd, and Dm[0]=Dm When the LEN field indicates a vector mode (vector length > 1), FABSD might perform

more than one absolute value operation Addressing Mode 4 - Double-precision vectors (monadic) on page C5-19 describes how FABSD encodes the registers it uses and how vec_len, Dd[i], and Dm[i] are determined

Signaling NaNs

To comply with the VFP architecture, FABSD must not generate an exception even if the value in its source register is a signaling NaN This is a more stringent requirement than the one in the Appendix to the IEEE 754-1985 standard

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4.1.2 FABSS

The FABSS (Floating-point Absolute Value, Single-precision) instruction writes the absolute value of a single-precision register to another single-precision register It can also perform a vector version of this operation

Syntax

FABSS{<cond>} <Sd>, <Sm>

where:

<cond> Is the condition under which the instruction is executed The conditions are defined in The

condition field on page A3-5 If <cond> is omitted, the AL (always) condition is used

<Sd> Specifies the destination register Its number is encoded as Fd (top 4 bits) and D (bottom

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Absolute value function

The function abs(x) means a copy of x with its sign bit forced to zero, as defined in the Appendix to the IEEE 754-1985 standard

Flush-to-zero mode

The FZ bit of the FPSCR does not affect the operand or result of this instruction

Vectors When the LEN field of the FPSCR indicates scalar mode (vector length 1), FABSS performs

just one absolute value operation, and vec_len=1, Sd[0]=Sd, and Sm[0]=Sm When the LEN field indicates a vector mode (vector length > 1), FABSS might perform

more than one absolute value operation Addressing Mode 3 - Single-precision vectors (monadic) on page C5-14 describes how FABSS encodes the registers it uses and how vec_len, Sd[i], and Sm[i] are determined

Signaling NaNs

To comply with the VFP architecture, FABSS must not generate an exception even if the value in its source register is a signaling NaN This is a more stringent requirement than the one in the Appendix to the IEEE 754-1985 standard

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4.1.3 FADDD

The FADDD (Floating-point Addition, Double-precision) instruction adds together two double-precision registers and writes the result to a third double-precision register It can also perform a vector version of this operation

Syntax

FADDD{<cond>} <Dd>, <Dn>, <Dm>

where:

<cond> Is the condition under which the instruction is executed The conditions are defined in The

condition field on page A3-5 If <cond> is omitted, the AL (always) condition is used

<Dd> Specifies the destination register

<Dn> Specifies the register that contains the first operand for the addition

<Dm> Specifies the register that contains the second operand for the addition

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Vectors When the LEN field of the FPSCR indicates scalar mode (vector length 1), FADDD performs

just one addition, and vec_len=1, Dd[0]=Dd, Dn[0]=Dn, and Dm[0]=Dm When the LEN field indicates a vector mode (vector length > 1), FADDD might perform

more than one addition Addressing Mode 2 - Double-precision vectors (non-monadic) on

page C5-8 describes how FADDD encodes the registers it uses and how vec_len, Dd[i], Dn[i], and Dm[i] are determined

Rounding The operation is a fully-rounded addition The rounding mode is determined by the FPSCR

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4.1.4 FADDS

The FADDS (Floating-point Addition, Single-precision) instruction adds together two single-precision registers and writes the result to a third single-precision register It can also perform a vector version of this operation

Syntax

FADDS{<cond>} <Sd>, <Sn>, <Sm>

where:

<cond> Is the condition under which the instruction is executed The conditions are defined in The

condition field on page A3-5 If <cond> is omitted, the AL (always) condition is used

<Sd> Specifies the destination register Its number is encoded as Fd (top 4 bits) and D (bottom

bit)

<Sn> Specifies the register that contains the first operand for the addition Its number is encoded

as Fn (top 4 bits) and N (bottom bit)

<Sm> Specifies the register that contains the second operand for the addition Its number is

encoded as Fm (top 4 bits) and M (bottom bit)

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Vectors When the LEN field of the FPSCR indicates scalar mode (vector length 1), FADDS performs

just one addition, and vec_len=1, Sd[0]=Sd, Sn[0]=Sn, and Sm[0]=Sm When the LEN field indicates a vector mode (vector length > 1), FADDS might perform

more than one addition Addressing Mode 1 - Single-precision vectors (non-monadic) on

page C5-2 describes how FADDS encodes the registers it uses and how vec_len, Sd[i], Sn[i], and Sm[i] are determined

Rounding The operation is a fully-rounded addition The rounding mode is determined by the FPSCR

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4.1.5 FCMPD

The FCMPD (Floating-point Compare, Double-precision) instruction compares two double-precision registers, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction)

Syntax

FCMPD{<cond>} <Dd>, <Dm>

where:

<cond> Is the condition under which the instruction is executed The conditions are defined in The

condition field on page A3-5 If <cond> is omitted, the AL (always) condition is used

<Dd> Specifies the register which contains the first operand for the comparison

<Dm> Specifies the register which contains the second operand for the comparison

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Vectors FCMPD always specifies a scalar operation, regardless of the LEN field of the FPSCR

NaNs The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==,

> or unordered If either or both of Dd and Dm are NaNs, they are unordered, and all three

of (Dd < Dm), (Dd == Dm) and (Dd > Dm) are false This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1

FCMPD only raises an Invalid Operation exception if one or both operands are signaling NaNs, and is suitable for testing for ==, !=, unorderedness, and other predicates which do not raise an exception when the operands are unordered

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4.1.6 FCMPED

The FCMPED (Floating-point Compare (NaN Exceptions), Double-precision) instruction compares two double-precision registers, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction)

Syntax

FCMPED{<cond>} <Dd>, <Dm>

where:

<cond> Is the condition under which the instruction is executed The conditions are defined in The

condition field on page A3-5 If <cond> is omitted, the AL (always) condition is used

<Dd> Specifies the register which contains the first operand for the comparison

<Dm> Specifies the register which contains the second operand for the comparison

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Vectors FCMPED always specifies a scalar operation, regardless of the LEN field of the FPSCR

NaNs The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==,

> or unordered If either or both of Dd and Dm are NaNs, they are unordered, and all three

of (Dd < Dm), (Dd == Dm) and (Dd > Dm) are false This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1

FCMPED raises an Invalid Operation exception if one or both operands are any type of NaN, and is suitable for testing for <, <=, >, >=, and other predicates which raise an exception when the operands are unordered

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4.1.7 FCMPES

The FCMPES (Floating-point Compare (NaN Exceptions), Single-precision) instruction compares two single-precision registers, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction)

Syntax

FCMPES{<cond>} <Sd>, <Sm>

where:

<cond> Is the condition under which the instruction is executed The conditions are defined in The

condition field on page A3-5 If <cond> is omitted, the AL (always) condition is used

<Sd> Specifies the register which contains the first operand for the comparison The register

number is encoded as Fd (top 4 bits) and D (bottom bit)

<Sm> Specifies the register which contains the second operand for the comparison The register

number is encoded as Fm (top 4 bits) and M (bottom bit)

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Vectors FCMPES always specifies a scalar operation, regardless of the LEN field of the FPSCR

NaNs The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==,

> or unordered If either or both of Dd and Dm are NaNs, they are unordered, and all three

of (Dd < Dm), (Dd == Dm) and (Dd > Dm) are false This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1

FCMPES raises an Invalid Operation exception if the operand is any type of NaN, and is suitable for testing for <, <=, >, >=, and other predicates which raise an exception when the operands are unordered

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4.1.8 FCMPEZD

The FCMPEZD (Floating-point Compare (NaN Exceptions) with Zero, Double-precision) instruction compares a double-precision register with zero, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction)

Syntax

FCMPEZD{<cond>} <Dd>

where:

<cond> Is the condition under which the instruction is executed The conditions are defined in The

condition field on page A3-5 If <cond> is omitted, the AL (always) condition is used

<Dd> Specifies the register which contains the first operand for the comparison

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Vectors FCMPEZD always specifies a scalar operation, regardless of the LEN field of the FPSCR

NaNs The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==,

> or unordered If Dd is a NaN, it compares as unordered with zero, and all three of (Dd <

0.0), (Dd == 0.0) and (Dd > 0.0) are false This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1

FCMPEZD raises an Invalid Operation exception if the operand is any type of NaN, and is suitable for testing for <, <=, >, >=, and other predicates which raise an exception when the operands are unordered

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4.1.9 FCMPEZS

The FCMPEZS (Floating-point Compare (NaN Exceptions) with Zero, Single-precision) instruction compares a single-precision register with zero, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction)

Syntax

FCMPEZS{<cond>} <Sd>

where:

<cond> Is the condition under which the instruction is executed The conditions are defined in The

condition field on page A3-5 If <cond> is omitted, the AL (always) condition is used

<Sd> Specifies the register which contains the first operand for the comparison The register

number is encoded as Fd (top 4 bits) and D (bottom bit)

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Vectors FCMPEZS always specifies a scalar operation, regardless of the LEN field of the FPSCR

NaNs The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==,

> or unordered If Dd is a NaN, it compares as unordered with zero, and all three of (Dd <

0.0), (Dd == 0.0) and (Dd > 0.0) are false This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1

FCMPEZS raises an Invalid Operation exception if the operand is any type of NaN, and is suitable for testing for <, <=, >, >=, and other predicates which raise an exception when the operands are unordered

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4.1.10 FCMPS

The FCMPS (Floating-point Compare, Single-precision) instruction compares two single-precision registers, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction)

Syntax

FCMPS{<cond>} <Sd>, <Sm>

where:

<cond> Is the condition under which the instruction is executed The conditions are defined in The

condition field on page A3-5 If <cond> is omitted, the AL (always) condition is used

<Sd> Specifies the register which contains the first operand for the comparison The register

number is encoded as Fd (top 4 bits) and D (bottom bit)

<Sm> Specifies the register which contains the second operand for the comparison The register

number is encoded as Fm (top 4 bits) and M (bottom bit)

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Vectors FCMPS always specifies a scalar operation, regardless of the LEN field of the FPSCR

NaNs The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==,

> or unordered If either or both of Dd and Dm are NaNs, they are unordered, and all three

of (Dd < Dm), (Dd == Dm) and (Dd > Dm) are false This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1

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4.1.11 FCMPZD

The FCMPZD (Floating-point Compare with Zero, Double-precision) instruction compares a double-precision register with zero, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction)

Syntax

FCMPZD{<cond>} <Dd>

where:

<cond> Is the condition under which the instruction is executed The conditions are defined in The

condition field on page A3-5 If <cond> is omitted, the AL (always) condition is used

<Dd> Specifies the register which contains the first operand for the comparison