VHDL Reference Tables

Table B-1 lists all of the different kinds of statements alphabetically and includes an example usage.. Table B-1 Statement or Clause Examples Access Type TYPE access_type IS ACCESS type

VHDL Reference Tables

This appendix focuses on tables of information that are useful when writ-ing VHDL descriptions Most of the information in the tables is available

in the text of the book, however, these tables consolidate the information into one area for easy reference.

Table B-1 lists all of the different kinds of statements alphabetically and includes an example usage.

Table B-1

Statement or Clause Example(s)

Access Type TYPE access_type IS ACCESS type_to_be_accessed; Aggregate record_type := (first, second, third);

Alias ALIAS opcode : BIT_VECTOR (0 TO 3) IS

INSTRUCTION(10 TO 13);

Architecture ARCHITECTURE architecture_name OF entity

name IS declare some signals here BEGIN

put some concurrent statements here END architecture_name;

Array Type TYPE array_type IS ARRAY (0 TO 7) OF BIT; Assert ASSERT x > 10 REPORT “x is too small”

SEVERITY ERROR;

Attribute Declaration ATTRIBUTE attribute_name : attribute_type; Attribute Specification ATTRIBUTE attribute_name OF

entity_name : entity_class IS value;

Block Statement block_name : BLOCK

declare some stuff here BEGIN

put some concurrent statements here END BLOCK block_name;

Case Statement CASE some_expression IS

WHEN some_value =>

do_some_stuff WHEN some_other_value =>

do_some_other_stuff WHEN OTHERS =>

do_some_default_stuff END CASE;

Continued. Component Declaration COMPONENT component_name

PORT (port1_name : port1_type;

port2_name : port2_type;

port3_name : port3_type);

END COMPONENT;

Component Instantiation instance_name : component_name PORT MAP

(first_port, second_port, third_port);

instance_name : component_name PORT MAP (formal1 => actual1, formal2 => actual2); Conditional Signal Assignment target <= first_value WHEN (x = y) ELSE

second_value WHEN a >= b ELSE third_value;

Configuration Declaration CONFIGURATION configuration_name OF

entity_name IS FOR architecture_name FOR instance_name : entity_name USE ENTITY

library_name.entity_name (architecture_name);

END FOR;

FOR instance_name : entity_name USE CONFIGURATION

library_name.configuration_name;

END FOR;

END FOR;

END configuration_name;

Constant Declaration CONSTANT constant_name : constant_type :=

value;

Entity Declaration ENTITY entity_name IS

PORT (port1 : port1_type;

port2 : port2_type);

END entity_name;

Exit Statement EXIT;

EXIT WHEN a <= b;

EXIT loop_label WHEN x = z;

File Type Declaration TYPE file_type_name IS FILE OF data_type; File Object Declaration FILE file_object_name : file_type_name IS IN

“/absolute/path/name”;

For Loop FOR loop_variable IN start TO end LOOP

do_some_stuff END LOOP;

Function Declaration FUNCTION function_name (parameter1 :

parameter1_type; parameter2 : parameter2_type) RETURN return_type; Function Body FUNCTION function_name (parameter1 :

parameter1_type; parameter2 : parameter2_type) RETURN return_type IS BEGIN

do some stuff END function_name;

Generate Statement generate_label : FOR gen_var IN start TO end

GENERATE label : component_name PORT MAP ( );

END GENERATE;

Generic Declaration GENERIC (generic1_name : generic1_type;

generic2_name : generic2_type); Generic Map GENERIC MAP (generic1_name => value1, value2);

Guarded Signal Assignment g1 : BLOCK (clk = ‘1’ AND clk’EVENT)

BEGIN

q <= GUARDED d AFTER 5 NS;

END BLOCK;

IF Statement IF x <= y THEN

some statements END IF;

IF z > w THEN some statements ELSIF q < r THEN some more statements END IF;

IF a = b THEN some statements ELSIF c = d THEN some more statements ELSE

even more statements END IF;

Incomplete Type TYPE type_name;

Continued. Library Declaration LIBRARY library_name;

Loop Statement FOR loop_variable IN start TO end LOOP

do lots of stuff END LOOP;

WHILE x < y LOOP modify x and y and do other stuff END LOOP;

Next Statement IF i < 0 THEN

NEXT;

END IF;

Others Clause WHEN OTHERS =>

do some stuff Package Declaration PACKAGE package_name IS

declare some stuff END PACKAGE;

Package Body PACKAGE BODY package_name IS

put subprogram bodies here END package_name;

Physical Type TYPE physical_type_name IS RANGE start TO end

UNITS unit1 ; unit2 = 10 unit1;

unit3 = 10 unit2;

END UNITS;

Port Clause PORT ( port1_name : port1_type; port2_name :

port2_type);

Port Map Clause PORT MAP (port1_name => signal1, signal2); Procedure Declaration PROCEDURE procedure_name (parm1 : in

parm1_type; parm2 : out parm2_type; parm3 : inout parm3_type); Procedure Body PROCEDURE procedure_name (parm1 : in

parm1_type; parm2 : out parm1_type; parm3 : inout parm3_type) IS BEGIN

do some stuff END procedure_name;

Process Statement PROCESS (signal1, signal2, signal3)

declare some stuff BEGIN

do some stuff END PROCESS;

Record Type TYPE record_type IS

RECORD field1 : field1_type;

field2 : field2_type;

END RECORD;

Report Clause ASSERT x = 10 REPORT “some string”;

Return Statement RETURN;

RETURN (x + 10);

Selected Signal Assignment WITH z SELECT

x <= 1 AFTER 5 NS WHEN 0,

2 AFTER 5 NS WHEN 1,

3 AFTER 5 NS WHEN OTHERS;

Severity Clause ASSERT x > 5 REPORT “some string” SEVERITY

ERROR;

Signal Assignment a <= b AFTER 20 NS;

Signal Declaration SIGNAL x : xtype;

Subtype Declaration SUBTYPE bit8 IS INTEGER RANGE 0 TO 255; Transport Signal Assignment x <= TRANSPORT y AFTER 50 NS;

Type Declaration TYPE color is (red, yellow, blue, green, orange);

TYPE small_int is 0 to 65535;

Use Clause USE WORK.my_package.all;

Variable Declaration VARIABLE variable_name : variable_type;Wait

Statement WAIT ON a, b, c;

WAIT UNTIL clock’EVENT AND clock = ‘1’; WAIT FOR 100 NS;

WAIT ON a, b UNTIL b > 10 FOR 50 NS;

While Loop WHILE x > 15 LOOP

do some stuff END LOOP;

Table B-2 lists all of the predefined attributes that retrieve infor-mation about VHDL type data The descriptions are necessarily terse

to fit into the table cells; see Chapter 6, “Predefined Attributes” for more detailed information.

T’BASE Returns the base type of NATURAL’BASE returns

datatype it is attached to INTEGER T’LEFT Returns left value specified in INTEGER’LEFT is -2147483647

type declaration BIT’LEFT is ‘0’

T’RIGHT Returns right value specified INTEGER’RIGHT is 2147483647

in type declaration BIT’RIGHT is ‘1’

T’HIGH Returns largest value specified TYPE bit8 is 255 downto 0

in declaration bit8’HIGH is 255 T’LOW Returns smallest value TYPE bit8 is 255 downto 0

specified in declaration bit8’LOW is 0 T’POS(X) Returns position number of TYPE color IS (red, green,

argument in type (first blue, orange);

position is 0) color’POS(green) is 1 T’VAL(X) Returns value in type at TYPE color IS (red, green,

specified position number blue, orange);

color’VAL(2) is blue

T’SUCC(X) Returns the successor to the TYPE color IS (red,

value passed in green, blue, orange);

color’SUCC(green) is blue

T’PRED(X) Returns the predecessor to TYPE color IS (red, green,

the value passed in blue, orange);

color’PRED(blue) is green

T’LEFTOF(X) Returns the value to the left TYPE color IS (red, green,

of the value passed in blue, orange);

color’LEFTOF(green) is red

T’RIGHTOF(X) Returns the value to the right TYPE color IS (red, green,

of the value passed in blue, orange);

color’RIGHTOF(blue) is orange

Table B-3 lists all predefined attributes that return information about array datatypes The Nparameter for all attributes specifies to which par-ticular range the attribute is being applied This only makes sense for multidimensional arrays For single-dimensional arrays, the parameter can be ignored For more detailed information, see Chapter 6, “Predefined Attributes.”

All of the next examples apply to the following declaration:

TYPE a_type IS ARRAY(0 TO 3, 7 DOWNTO 0) OF BIT;

Table B-4 lists all predefined attributes that return information about signals or create new signals For more detailed information, see Chapter

6, “Predefined Attributes.”

Table B-5 lists all of the operators and their relative precedence Table B-6 lists all of the different types of literals and a sample usage.

In all cases, the _ character is ignored when interpreting the value of

a literal The base that the exponent in the based integer and based real examples is applied to is the base specified for interpreting the number Bit string literals are used to specify values for types that resemble the

BIT_VECTORtype.

A’LEFT(N) Returns left array bound a_type’LEFT(1) is 0

of selected index range a_type’LEFT(2) is 7 A’RIGHT(N) Returns right array bound a_type’RIGHT(1) is 3

of selected index range a_type’RIGHT(2) is 0 A’HIGH(N) Returns largest array a_type’HIGH(1) is 3

bound value of selected a_type’HIGH(2) is 7

index range

A’LOW(N) Returns smallest array a_type’LOW(1) is 0

bound value of selected a_type’LOW(2) is 0

index range

A’RANGE(N) Returns selected index a_type’RANGE(1) is 0

a_type’RANGE(2) is 7 DOWNTO 0

A’REVERSE_RANGE(N) Returns selected index a_type’REVERSE_RANGE(1)

range reversed is 3

DOWNTO 0 a_type’REVERSE_RANGE(2)

is 0 TO 7

A’LENGTH(N) Returns size of selected a_type’LENGTH(1) is 4

index range a_type’LENGTH(2) is 8

S’DELAYED(T) Creates a new signal delayed by T clock’DELAYED(10 ns) S’QUIET(T) Creates a new signal that is true reset’QUIET(5 ns)

when signal S has had no transactions for time T; otherwise,

false

S’STABLE(T) Creates a new signal that is true clock’STABLE(1 ns)

when signal S has had no events for time T; otherwise, false S’TRANSACTION Creates a signal of type BIT that load’TRANSACTION

toggles for every transaction on

signal S S’EVENT Returns true when an event has clock’EVENT

occurred for signal S this delta S’ACTIVE Returns true when a transaction load’ACTIVE

has occurred for signal S this delta S’LAST_EVENT Returns the elapsed time since the data’LAST_EVENT

last event on signal S S’LAST_ACTIVE Returns the elapsed time since the clock’LAST_ACTIVE

last transaction on signal S S’LAST_VALUE Returns the previously assigned data’LAST_VALUE

value of signal S

Table B-5

Precedence Operator Class Operator

Highest Miscellaneous ** , ABS, NOT

Multiplying * , /, MOD, REM

Sign + ,

-Adding + , -, &

Relational = , /=, <, <=, >, >=

Lowest Logical AND , OR, NAND, NOR, XOR

Decimal Integer 52

0 3E3 equals 3000 1_000_000 equals 1 million

0.0 178 1.222_333 Decimal Real with Exponent 1.2E+10

4.6E-9 Based Integer 16#FF# equals 255

8#777# equals 511 2#1101_0101# equals 213 16#FF#E1 equals 4080

16#AB.CD#E+2 8#77.66#E-10

'*' ' ' the space character String “this is a string”

" " empty string

“ABC” & “CDE” concatenation

O”770770”

B”1111_0000_1111”