Lecture Microcomputer principles and applications - Chapter 7: Timing generation and measurements

Contents: Timer functions, MSP430 Timer, Timer A, Timer A Output modes, Timer A interrupts,...

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Chapter 7

Timing generation and

measurements

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• Stop watch.

• Captures time of external events.

• Creates periodic interrupts.

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• Asynchronous 16-bit timer/counter with four operating modes.

• Selectable and configurable clock source.

• Two or three configurable capture/compare registers.

• Interrupt vector register for fast decoding of all Timer A

interrupts.

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7.3 Timer A

Generally MSP430 family contains two categories of timers

What is the difference between Timer A and Timer B?

Same in operation, but Timer B is more sophisticated than Timer A

and it has many features available than compared with Timer A.

They are:

• Bit-length of the timer is programmable as 8-bit, 10- bit, 12-bit,

16-bit.

Timer A contains three capture/compare registers.

• It contains double-buffered CCR register.

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How many timers are there in MSP430G2553?

There are two 16-bit timers are available in MSP430G2553,

excluding watch dog timer.

Each 16-bit timer starts counts from 0 to 0x0FFFF (0 to 65536) and

they operate in four different modes:

• Stop mode - Timer is in halt state or stops the timer.

TACCR0 register (other than 0xFFFF) and roll over to zero after

it reached the count value Generally this mode used to produce time delays.

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7.3 Timer A

counts up from zero to maximum value 0xFFFFh and rolls over

to zero after it reached 0xFFFF and keep going.

register and then counts down back to zero as shown in figure.

It is good for generating PWM’s and driving motors.

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TACCR0 0FFFFh

Up mode

Continous mode

Up/Down mode

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7.3 Timer A

00 01 10 11

Divider 1/2/4/8

16-bit timer TAR

0 15

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• CCR0, CCR1, CCR2 (Compare/Capture Registers) are used to

load the timer count.

• TAR (Timer A Register) is the 16-bit timer register in which the

count start increment/decrements value depends upon the timer mode settings.

stored in CCR0 register.

zero.

• IDx bit are used to divide the clock signal applied to timer.

direction (mode).

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7.4 Timer A Output modes

OUTx bit The OUTx signal updates mediately when OUTx is updated.

the TACCRx value It remains set until a reset of the timer, or until another output mode is selected and affects the output.

counts to the TACCRx value It is reset when the timer counts to the TACCR0 value.

to the TACCRx value It is reset when the timer counts to the TACCR0 value.

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OUTMODE.x Mode Description

counts to the TACCRx value The output period is double the timer period.

to the TACCRx value It remains reset til another output mode is selected and affects the output.

counts to the TACCRx value It is set when the timer counts to the TACCR0 value.

to the TACCRx value It is set when the timer counts to the TACCR0 value.

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7.4 Timer A Output modes

Example: Timer in Up Mode

TACCR0 0FFFFh

TACCR1

Output mode 1: Set

Output mode 2: Toggle/Reset

Output mode 3: Set/ResetOutput mode 4: Toggle

Output mode 5: Reset

Output mode 6: Toggle/Set

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There are two interrupt flags (CCIFG and TAIFG) and its

corresponding two interrupt vectors (TACCR0 and TAIV) available

for Timers in MSP430.

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TACTL - Timer A Control Register

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

Timer_A clock source select

(INCLK is device-specific and is often assigned to the inverted TBCLK) (see the device-specific data sheet)

Unused Bits 15-10 Unused

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/1 /2 /4 /8 Mode control Setting MCx = 00h when Timer_A is not in use conserves power.

MCx Bits 5-4

00

01

Stop mode: the timer is halted.

Up mode: the timer counts up to TACCR0.

Unused

IDx

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TACTL - Timer A Control Register

15 14 13 12 11 10 9 8

Unused Bit 3 Unused

TACLR Bit 2 Timer_A clear Setting this bit resets TAR, the clock divider, and the count

direction The TACLR bit is automatically reset and is always read as zero.

TAIE Bit 1 Timer_A interrupt enable This bit enables the TAIFG interrupt request

0 1

Interrupt disabled Interrupt enabled

TAIFG Bit 0 Timer_A interrupt flag.

Unused

IDx

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TACCRx - Timer A Capture/Compare Register

15 14 13 12 11 10 9 8

TACCRx Bits 15-0 Timer_A capture/compare register.

Compare mode: TACCRx holds the data for the comparison to the timer value in the Timer_A Register, TAR.

Capture mode: The Timer_A Register, TAR, is copied into the TACCRx register when a capture isperformed

TARx

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Capture on fallig edgeCapture on both rising and falling edgesCapture/compare input select These bits select the TACCRx input signal

See the device-specific data sheet for specific signal connections

CCISx Bits 13-12

00 CCIxA

01 10

CCIxAGND

Unused SCCI

SCS

CCIFG OUTMODx CCIE CCI OUT COV

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TACCTLx - Timer A Capture/Compare Control Register

Unused Bit 9 Unused Read only Always read as 0

TACLR Bits 7 - 5 Output mode Modes 2, 3, 6, and 7 are not useful for TACCR0,

because EQUx = EQU0

CAP CMx

SCS Bit 8 Capture mode

01

Compare modeCapture mode

000001010011

OUT bit valueSet

Toggle/resetSet/reset

100 Toggle

Unused SCCI

SCS

CCIFG OUTMODx CCIE CCI OUT COV

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CCIE Bit 4 Capture/compare interrupt enable This bit enables the interrupt request of

the corresponding CCIFG flag

01

Interrupt disabledInterrupt enabled

CCI Bit 3 Capture/compare input The selected input signal can be read by this bit

OUT Bit 2 Output For output mode 0, this bit directly controls the state of the output

01

Output lowOutput high

COV Bit 1 Capture overflow This bit indicates a capture overflow occurred COV must

be reset with software

01

No capture overflow occurredCapture overflow occurred

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TAIV - Timer A Interrupt Vector Register

9 r0

11 r0

12 r0

13 r0

14 r0

3 r-(0)

4 r0

5 r0

6 r0

7

r0

0 0

0

TAIV contents Interrupt Source Interrupt flag Interrupt priority

00h No interrupt pending - Highest 02h Capture/Compare TACCR1 CCIFG - 04h Capture/Compare TACCR2 CCIFG -

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