In this work, we present the study of the design and performance analysis of CMOS SRAM IC with pentacene p-channel and fullerene n-channel OPDK in Cadence CAD. Firstly, the basic operation of a designed organic 6TSRAM is examined to ensure the proper circuit.
Trang 1DESIGN AND SIMULATION OF ORGANIC CMOS 6T-SRAM WITH
VARIABLE THRESHOLD VOLTAGE
Dao Thanh Toan, Pham Thanh Huyen*
Abstract: In this work, we present the study of the design and performance
analysis of CMOS SRAM IC with pentacene p-channel and fullerene n-channel OPDK in Cadence CAD Firstly, the basic operation of a designed organic 6T-SRAM is examined to ensure the proper circuit Then, 6T-SRAM characteristics with variable threshold voltage p-channel element are inverstigated Simulation data show that the changes of the circuit parameters are in agreement with the physical operation of the tunable p-channel At the p-channel threshold voltage of 0.90 V, n-channel threshold voltage of 2.00 V and supply voltage of 5.00 V, low and high noise margins, cut-off frequency and power consumption are estimated to be 0.75 V, 0.70 V, 400 Hz and 80 nW This study may contribute in the structure design of SRAM using organic semiconductor
Keywords: Variable threshold voltage; Organic thin-film transistor; SRAM cell; IC design and simulation;
Cadence CAD
1 INTRODUCTION
SRAMs are the important devices for computing and data processing systems [1-3] Recently, SRAM cells with organic thin-film transistor (OTFT) are emerging devices to develop low-cost, large-area and flexible computing electronics [4-8] Several studies of organic SRAM have been demonstrated; for example, an organic SRAM had recently fabricated by M Takamiya et al [4] or Avila-Nino et al [8] In view of simulation, Kumar
et al reported on the study of design and analysis of noise margin, write ability and read stability of 6T-SRAM cell [6], where the SRAM cell was built using both organic and oxide semiconductors In the previous work, based on the organic process design kit (OPDK) in Cadence Virtuoso platform [9] and our experimental data [10], we have constructed the models for OTFTs with common semiconductors of fullerene n-channel (nOTFT) and pentacene p-channel (pOTFT) Those embedded OPDKs allow us being able
to develop a full-organic CMOS integrated circuit (IC) [11]
On the other hand, fundamentally, in order to achieve the maximum CMOS circuit performance, the balance between the saturated currents of p-channel pull-up network and n-channel pull-down network is required [12,13] To obtain that point, it is necessary to
modify the channel width/length (W/L) geometry and/or vary threshold voltage (Vth) The
former method is widely used in silicon IC where the W/L of pTFT is defined to be double
to nTFT [13] That difference however may result in a relatively complicated process in creating the mask and in manufacturing at a high intensity level as well Therefore, the later approach is a promising alternative [12] In IC industry, it is general that the IC should be examined the design before going to fabrication process to reduce the total cost
In this article, we present our timely efforts in designing and simulating an organic
full-CMOS 6T-SRAM using the OPDK where the W/L of both p-channel and n-channle is
similar The SRAM is analyzed in terms of basic digital memory operation In addition,
the dependences of the noise margin (NM), operating frequency (F) and power consumption (P) of the SRAM on the Vth,p obtaining from OTFT elements [10] are investigated to find out a suitable value To our best knowledge, this is the first report on tunale organic full-CMOS 6T-SRAM in Cadence CAD
Trang 22 SRAM DESIGN AND SIMULATION
Figure 1(a) presents the illustration of the cross-section of OTFT for the models, whose
fabrication and characterization were detailed in our previous work [10] The W/L ratio of
both p-channel and n-channel was assumed to be unchanged Here, we chosen SRAM circuit with 6 TFT elements because that is well-known as the lowest power cosumption architecture [1-8] A memory cell was created in Cadence with two cross-coupled organic
CMOS inverters and nOTFT accesses as seen in Fig 1(b) In basic simulation, the Vth,n of
nOTFT, the Vth,p of pOTFT, and the supply voltage were set at 2.00 V, 1.62 V, and 5 V,
respectively For investigation of the Vth dependence, the Vth,p of pOTFT was varied based
on the experimental data [10] to be from 4.40 to 4.60 V while the Vth,n of nOTFT was
fixed The effect of Vth,n change is no longer examined due to its funtionality of the accessor of SRAM
Pentacene
Fullerene
G (Si+n) Bilayer dielectric (60 nm)
D (Au) S (Au)
Semiconductor (40 nm)
6T-SRAM
(a)
(b)
Figure 1 (a) Structure of OTFT, and (b) Circuit diagram of organic 6T-SRAM designed
in Cadence CAD
3 ORGANIC CMOS 6T-SRAM PERFORMANCE
Transient responses at F values of 10 and 20 Hz for Word line (WL) and Bit line (BL),
respectively are plotted in Fig 2 As shown, at any time point, the read Q and Q-b signals alternately present for the “1” and “0” stored data, confirming a SRAM memory operation Figure 3(a) shows the read voltage transfer characteristic (VTC) and corresponding
gain at a supply voltage of 5 V From the VTC curve, the NM can be extracted from plot
of superimposed VTCs [12] as presented in Fig 3(b) The low NM (NML) and high NM (NMH) were found to be 0.80 and 0.70 V, respectively The relationship of the Q-b/Q and
the frequency is shown in Fig 4(a) The cut-off frequency FC is extracted to be about 420
Hz The FC value is relatively low in comparing with that in current industrial SRAM,
Trang 3however, the FC is in line with other reports on organic SRAM [4-8] and can be improved
by increasing the carrier mobility of the organic semiconductor [13]
Figure 4(b) presents the P versus the F It is a general concept that the P increases with
F, we have observed a similar phenomenon in Fig 4(b) in which the P increases from 20
to about 1000 nW, when the F goes from 1 to 420 Hz
0 3 6
Time (ms)
0 3 6
1
0 3 6
0 3 6
Figure 2 Transient responses of organic 6T-SRAM
0 3 6 9 12 15 18
0 1 2 3 4 5 0
1 2 3 4 5
Q-b (V)
1 2 3 4 5
0.8 V
0.7 V
Figure 3 (a) VTC curve and corresponding gain, and (b) Analysis of read static noise
margin of organic SRAM at Vth,p of 1.62 V
101 102 103 104105 106 0
10 20 30 40
0
101 102 103
101
102
103
104
Frequency (Hz)
Figure 4 (a) Frequency response characteristics, and (b) Power consumption versus
frequency of organic SRAM at V th,p of 1.62 V
Trang 4101102103104105106 0
10 20 30 40
Frequency (Hz)
101102103104105106
0
10
20
30
40
Frequency (Hz)
101102103104105106 0
10 20 30 40
Frequency (Hz)
101102103104105106
0
10
20
30
40
Frequency (Hz)
(d)
101102103104105106 0
10 20 30 40
Frequency (Hz)
101102103104105106 0
10 20 30 40
Frequency (Hz)
Figure 5 Frequency response at Vth,p of (a) 4.40 V, (b) 3.80 V, (c) 2.90 V, (d) 0.90 V,
(e) 0.20 V, and (f) 4.60 V
1 2 3 4 5
1
2
3
4
5
30 %
38 %
1 2 3 4 5 1
2 3 4 5
32 %
28 %
1 2 3 4 5
1
2
3
4
5
28 %
30 %
1 2 3 4 5 1
2 3 4 5
30 %
38 %
1 2 3 4 5 1
2 3 4 5
12 %
17 %
0 1 2 3 4 5 0
1 2 3 4 5
8 %
8.5 %
Figure 6 Read static noise margin depends on the Vth,p of (a) 4.40 V, (b) 2.90 V, (c)
1.62 V, (d) 0.90 V, (e) 0.20 V, and (f) 4.60 V
0.3 0.4 0.5 0.6
FC
Vth,p (V)
Optimal
0 40 80 120 160
Vth,p (V)
Optimal
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vth,p (V)
Figure 7 Impacts of Vth,p on (a) NML and NMH, (b) FC and (c) P of SRAM Solid arrow indicates direction of Vth,p shift Dotted arrow stands from optimal values
Trang 5In later simulation, we have further investigated the impacts of Vth,p on the 6T-SRAM
performance where the Vth,p varied from 4.40 to 4.60 V while the Vth,n of nOTFT was kept
stable at 2.00 V Figures 5 and 6 show the frequency response and NM characteristics at the different Vth,p parameters The NML and NMH were realized to decrease with the Vth,p
shift as summarized in Fig 7(a) In our variable pOTFT, the electrons trapped at the
bilayer dielectric causes a positive shift in Vth,p, to enhance hole accumulation at the transistor channel [10,13] That in turn leads to the increase in the operating frequency
The simulation results agree with that consideration as shown in Fig 7(b), the FC increases
with positively shift in Vth,p On the other hand, the enhancement of accumulated hole
density also results in a reduction in the operating voltage As the result, the P decreases from 157.70 to 20.30 nW when the Vth,p changes from 4.40 to 4.60 V (Fig 7(c)) From
tendencies in Fig 7, we define an optimal value of Vth,p is obtained to be 0.90 V, that
results in the NML, NMH, FC, and P of 0.75 V, 0.70 V, 400 Hz and 80 nW, respectively
It should be noted here that as mentioned in introduction section, there are a few works
on the organic SRAM so far, resulting in the fact that is hard to fairly compare the circuit performance obtained from our study and other works However, in terms of energy, the simulation results indicate that, if the n-channel and p-channel OTFT components in the
current SRAM have the Vth,n of 2.00 V and the Vth,p of 0.90 V, respectively, the P of 80
nW can be comparable to that in the best achivement shown in literature [5]
4 CONCLUSION
In conclusion, we have demonstrated the studies of designing and simulating an organic full-CMOS 6T-SRAM with variable thresold voltage using the OPDKs in
Cadence Simulation results indicated that when the Vth,p shifts from negative to positive
region, the changes of the NM, FC, and P agree with the physical operation of the tunable pOTFT element From obtained simulation data, we propose that, at the fixed Vth,n of 2.00
V, the Vth,p should be chosen at 0.90 V to achieve the best circuit performance The designed SRAM well operated in Cadence with the fixed or changeable input values, suggesting that our OPDK models can be extended to simulate other organic CMOS circuits Futhermore, even it is necessary to do calibration with the result measuring after SRAM fabrication, this work clearly helps to optimize the organic 6T-SRAM structure
Acknowledgement: This work partly funded by the National Foundation for Science
and Technology Development (NAFOSTED) under grant no 103.99-2013.13
REFERENCES
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TÓM TẮT
NGHIÊN CỨU VỀ THIẾT KẾ VÀ MÔ PHỎNG 6T-SRAM CMOS HỮU CƠ
VỚI ĐIỆN ÁP NGƯỠNG THAY ĐỔI
Trong bài báo này chúng tôi trình bày mô phỏng và phân tích hiệu năng của SRAM CMOS với OPDK pentacene kênh p và fullerene kênh n trong phần mềm thiết kế vi mạch Cadence Đầu tiên, hoạt động cơ bản của mạch được kiểm tra để đảm bảo mạch hữu cơ thiết kế đúng với tính năng của SRAM Sau đó, các đặc tính của SRAM với điện áp ngưỡng của transistor kênh p thay đổi được nghiên cứu Dữ liệu mô phỏng chỉ ra rằng sự thay đổi của các tham số của mạch tương đồng với cơ chế vật lý của OTFT kênh P có điện áp ngưỡng thay đổi được Tại giá trị của điện
áp ngưỡng kênh p 0.90 V, kênh n 2.00 V và điện áp nguồn 5 V, lề nhiễu thấp và cao, tần số cắt và công suất tiêu thụ của mạch được xác định tương ứng là 0.75 V, 0.70 V, 400 Hz and 80 nW Kết quả từ nghiên cứu này sẽ góp phần vào việc thiết kế cấu hình tối ưu cho SRAM sử dụng bán dẫn hữu cơ
Từ khóa: Điện áp ngưỡng thay đổi; Transistor màng mỏng hữu cơ; SRAM; Thiết kế và mô phỏng IC;
Cadence CAD
Received date, 14 th March, 2017 Revised manuscript, 30 th July, 2017 Published, 18 th August, 2017
Author affiliations:
Faculty of Electrical-Electronic Engineering, University of Transport and Communications; No.3 Lang Thuong, Cau Giay, Ha Noi, Vietnam
*
Corresponding authors: huyenktdt@utc.edu.vn