The instruction set of AVR

LD Rd, X ; Load a byte Indirectly from Data Space into a Register pointed by pointer register X Loads one byte of data indirectly from data space into the destination register Rd using

Assembler Directives

While instructions tell the CPU what to do, directives (also called pseudo instructions) give directions to the assembler

.EQU (Equate)

This is used to define a constant value or fixed address The EQU directive does not set aside storage for a data item, but associates a constant number with a data or an address label so that when the label appears in the program, its constant is substituted for the label

LDI R16, COUNT; R 0x25 When executing the above instruction “LDI R16, COUNT”, the register R2 will be loaded with the value 25H

.SET

This directive is used to define a constant value or a fixed address In this regard, the SET and .EQU directives are indentical The only difference is that the value assigned by the SET directive may

be reassigned later

.ORG (origin)

The ORG directive is used to indicate the beginning of the address It can be used for both code and data

.INCLUDE

The INCLUDE directive tells the AVR assembler to add the contents of a file to our program The instruction set of AVR microcontroller is classified into the following groups

Ex: .INCLUDE “M8DEF.INC” ; use ATMega8

.INCLUDE “M16DEF.INC” ; use ATMega16

.INCLUDE “M32DEF.INC” ; use ATMega32

The instruction set of AVR microcontroller is classified into the following groups

1 Data transfer instructions

2 Arithmetic instructions

3 Logical instructions

4 Branching instructions

5 Call and Return instructions

6 Bit wise instructions

Data Transfer Instructions

MOV Rd, Rr ( Copy a Register)

d 0 to 31, r 0 to 31

Byte of data is copied from source register to into destination register The source register Rr is unchanged, while the destination register Rd is loaded with a copy of Rr No flags are affected Ex: MOV R5, R4; contents of source register R4 copied into the destination register R5

LDI Rd, K ; Load Immidiate

d 16 to 31, K 0 to FFH ( 0 to 255)

This instruction loads an 8-bit number (K) into a destination register Rd No flags are affected Ex: LDI R16, 25H; Loads 25H into the destination register R16

LDS Rd, k ; Load Direct from Data Space memory

d 0 to 31, k 0 to FFFFH ( 0 to 65535)

Loads one byte (k) of data from the data space into a destination register Rd No flags are affected

Ex: LDS R2, $9050; Loads one byte of data from 9050 into the destination register R2

STS k, Rr ; Store Direct to Data Space

k 0 to FFFFh (0 to 65535), r 0 to 31

Stores one byte from a register to the data space specified by 16-bit address

Ex: STS $9060, R3; The contents of register R3 into the dataspace ($9060) specified in the operand

LD Rd, X ; Load a byte Indirectly from Data Space into a Register pointed by pointer register X

Loads one byte of data indirectly from data space into the destination register Rd using pointer register X The pointer register X holds the 16-bit address of the data location The X-pointer can be left unchanged by the operation, or it can be post-incremented or pre-decremented Example:

1 LD Rd, X; Loads one byte of data from data space pointed by X-pointer register The

pointer register X is unchanged after executing the instruction

2 LD Rd, X+; Loads one byte of data from data space pointed by X-pointer register The pointer register X is incremented after executing the instruction

3 LD Rd, - X; The pointer register X is decremented and loads one byte of data from data space pointed by X-pointer register

LD Rd, Y ; Load a byte Indirectly from Data Space into a Register pointed by pointer register Y

Loads one byte of data indirectly from data space into the destination register Rd using pointer register Y The pointer register Y holds the 16-bit address of the data location The Y-pointer can be left unchanged by the operation, or it can be post-incremented or pre-decremented

Example:

1 LD Rd, Y; Loads one byte of data from data space pointed by Y-pointer register The

pointer register X is unchanged after executing the instruction

2 LD Rd, Y+; Loads one byte of data from data space pointed by Y-pointer register The pointer register Y is incremented after executing the instruction

3 LD Rd, - Y; The pointer register Y is decremented and loads one byte of data from data space pointed by Y-pointer register

LD Rd, Z ; Load a byte Indirectly from Data Space into a Register pointed by pointer register Z

Loads one byte of data indirectly from data space into the destination register Rd using pointer register Z The pointer register Z holds the 16-bit address of the data location The Z-pointer can be left unchanged by the operation, or it can be post-incremented or pre-decremented

Example:

1 LD Rd, Z; Loads one byte of data from data space pointed by Z-pointer register The pointer register Z is unchanged after executing the instruction

2 LD Rd, Z+; Loads one byte of data from data space pointed by Z-pointer register The pointer register Z is incremented after executing the instruction

3 LD Rd, - Z; The pointer register Z is decremented and loads one byte of data from data space pointed by Z-pointer register

ST X, Rd; Store a byte Indirectly from a Register into a Data Space pointed by pointer register Z

Loads one byte of data indirectly from a register into data space using pointer register X The pointer register X holds the 16-bit address of the data location The X-pointer can be left

unchanged by the operation, or it can be post-incremented or pre-decremented

1 ST X, Rd; Stores one byte of data from the Register Rd into data space pointed by

X-pointer register The X-pointer register X is unchanged after executing the instruction

2 ST X+, Rd; Loads one byte of data from the register Rd into data space pointed by X-pointer register The pointer register X is incremented after executing the instruction

3 ST -X, Rd; The pointer register X is decremented and stores one byte of data from the register Rd into data space pointed by X-pointer register

ST Y, Rd; Store a byte Indirectly from a Register into a Data Space pointed by pointer register Y

Loads one byte of data indirectly from a register into data space using pointer register Y The pointer register Y holds the 16-bit address of the data location The Y-pointer can be left

unchanged by the operation, or it can be post-incremented or pre-decremented

1 ST Y, Rd; Stores one byte of data from the Register Rd into data space pointed by

Y-pointer register The Y-pointer register Y is unchanged after executing the instruction

2 ST Y+, Rd; Loads one byte of data from the register Rd into data space pointed by Y-pointer register The pointer register Y is incremented after executing the instruction

3 ST -Y, Rd; The pointer register Y is decremented and stores one byte of data from the register Rd into data space pointed by Y-pointer register

ST Z, Rd; Store a byte Indirectly from a Register into a Data Space pointed by pointer register Z

Loads one byte of data indirectly from a register into data space using pointer register Z The pointer register Z holds the 16-bit address of the data location The Z-pointer can be left

unchanged by the operation, or it can be post-incremented or pre-decremented

1 ST Z, Rd; Stores one byte of data from the Register Rd into data space pointed by Z-pointer register The pointer register Z is unchanged after executing the instruction

2 ST Z+, Rd; Loads one byte of data from the register Rd into data space pointed by Y-pointer register The pointer register Z is incremented after executing the instruction

3 ST -Z, Rd; The pointer register Z is decremented and stores one byte of data from the register Rd into data space pointed by Z-pointer register

IN Rd, A; Load an I/O location to Register

d 0 to 31

Loads data from the I/O space (ports, timers etc) into the destination register Rd

Ex: IN R25, $16; Loads a byte from port B into the register R25

OUTA, Rr ; Store Register to I/O location

r 0 to 31

Arithmetic Instructions

ADD Rd, Rr; Add a register

d 0 to 31, r 0 to 31; Rd Rd + Rr

Adds two registers and the result is placed in the destination register Rd The flags H, S, V, N, Z & C are modified according to the result of the operation

Example: ADD R0, R4 ; Adds the registers R0 and R4, the result is placed in the destination register R0

ADC Rd, Rr; Add a register with a Carry

d 0 to 31, r 0 to 31 ; Rd Rd + Rr + C (Carry Flag)

Adds two register and the contents of the carry flag (C) and the result is placed in the destination

register Rd The flags H, S, V, N, Z & C are modified according to the result of the operation

Ex: ADC R1, R14; Adds register R1, R14 and carry flag, the result is placed in the destination register

Rd

SUB Rd, Rr; Subtract a Register

d 0 to 31, r 0 to 31; Rd Rd – Rr

Substracts the source register Rr from the destination register Rd and the result is placed in the

destination register Rd The flags H, S, V, N, Z & C are modified according to the result of the

operation

Ex: SUB R2, R6; Subtracts the contents of register R6 from the contents of register R2 and the result is placed in R2

SUBI Rd, K; Subtract Immediate

d 16 to 31, K 0 to 255 ( 00h to FFh) Rd Rd - K

Subtracts a byte K from the register Rd and the result is placed in the destination register Rd This instruction works on registers R16 to R31 The flags H, S, V, N, Z & C are modified according to the result of the operation

Ex: SUBI R2, 62H

SBC Rd, Rr; Subtract with a Carry

d 0 to 31, r 0 to 31; Rd Rd – Rr

Substracts the source register Rr and carry flag (C) from the destination register Rd and the result is placed in the destination register Rd The flags H, S, V, N, Z & C are modified according to the result

of the operation

Ex: SBC R1, R6; Subtracts the contents of register R6 and carry flag from the contents of register R1 and the result is placed in R1

SBCI Rd, K; Subtract Immediate with a Carry

d 0 to 31, K 0 to 255 ( 00h to FFh) Rd Rd – K - C

Subtracts a byte (K) and carry flag from the register Rd and the result is placed in the destination

register Rd The flags H, S, V, N, Z & C are modified according to the result of the operation

Ex: SBC R1, 25H; Subtracts the 25H and carry flag from the contents of register R1 and the result is placed in R1

INC Rd; Increment a Register

d 0 to 31; Rd Rd + 1

Adds one to the contents of the register Rd and the result is placed in the same register The Carry flag

is not affected The flags S, V, N & Z are modified according to the result of the operation

Ex: INC R6; The contents of Register R6 are incremented by one and the result is placed in the same register

DEC Rd; Decrement a Register

d 0 to 31; Rd Rd - 1

Subtracts one from the contents of the register Rd and the result is placed in the same register The Carry flag is not affected The flags S, V, N & Z are modified according to the result of the operation

Ex: DEC R8; The contents of Register R8 are decremented by one and the result is placed in the same register

ASR Rd ; Arithmetic Shift Right

d 0 to 31

Shifts all bits in register Rd on place to the right Bit 7 is held constant Bit 0 is loaded into the carry flag and Bit 1 into Bit 0, Bit 2 into Bit1 and so on

Ex: ASR R3;

Logical Instructions

OR Rd, Rr; Logical OR

d 0 to 31, r 0 to 31; Rd Rd OR Rr

The contents of the source register Rr are logically ORed with the contents of the destination register

Rd The result is placed in the destination register Rd The flag V resets and S, N & Z are modified according to the result of the operation

Ex: OR R1, R3;

OR Rd, K; Logical OR with Immidiate

d 16 to 31, K 0 to 255 (00H to FFH); Rd Rd OR K

The contents specified in the operand(K) are logically ORed with the contents of the destination

register Rd The result is placed in the destination register Rd The flag V resets and S, N & Z are modified according to the result of the operation

Ex: OR R5, 25H;

AND Rd, Rr; Logical AND

d 0 to 31, r 0 to 31; Rd Rd AND Rr

The contents of the source register Rr are logically ANDed with the contents of the destination register

Rd The result is placed in the destination register Rd The flag V resets and S, N & Z are modified according to the result of the operation

Ex: AND R4, R2;

ANDI Rd, K; Logical AND with Immidiate

d 16 to 31, K 0 to 255 (00H to FFH); Rd Rd AND K

The contents specified in the operand(K) are logically ANDed with the contents of the destination register Rd The result is placed in the destination register Rd The flag V resets and S, N & Z are modified according to the result of the operation

Ex: AND R5, 4FH;

EOR Rd, Rr; Exclusive OR

d 0 to 31, r 0 to 31; Rd Rd Rr

The contents of the source register Rr are Exclusiv ORed with the contents of the destination register

Rd The result is placed in the destination register Rd The flag V resets and S, N & Z are modified according to the result of the operation

Ex: EOR R3, R2;

COM Rd; Complement a Register (One’s complement)

d 0 to 31;

This instruction performs a one’s complement of register Rd The flag V is reset, Z is set and S, N & C are modified according to the result of the operation

Ex: COM R2; The conetents of the register R2 are complemented (one’s complement)

NEG Rd; Two’s complement a Register

d 0 to 31;

This instruction performs Two’s complement of register Rd and the result is placed in the register Rd The flags H, S, V, N Z & C are modified according to the result of the operation

Ex: NEG R7; The conetents of the register R7 are two’s complemented

LSL Rd; Logical Shift Left

d 0 to 31;

Shifts all bits in the register Rd one place to the left Bit 0 is cleared Bit 7 is loaded into the Carry flag, Bit 6 into Bit 7, Bit 5 into Bit 6 and so on; The flags H, S, V, N Z & C are modified according to the result of the operation

Ex: LSL R3;

ROL Rd ; Rotate Left through Carry Flag

d 0 to 31;

Shifts all bits in the register Rd one place to the left Bit 7 is placed in carry flag, the carry flag bit in Bit0, Bit 6 into Bit 7, Bit 5 into Bit 6 and so on The flags H, S, V, N Z & C are modified according to the result of the operation

Ex: ROL R4;

LSR Rd; Logical Shift Right

d 0 to 31;

Shifts all bits in the register Rd one place to the right Bit 7 is cleared Bit 0 is loaded into the Carry flag, Bit 6 into Bit 5, Bit 5 into Bit 4 and so on; The flags H, S, V, N Z & C are modified according to the result of the operation

Ex: LSR R2;

ROR Rd ; Rotate Right through Carry Flag

d 0 to 31;

Shifts all bits in the register Rd one place to the right Bit 0 is placed in carry flag, the carry flag bit in Bit7 , Bit 7 into Bit 6, Bit 6 into Bit 5 and so on The flags H, S, V, N Z & C are modified according to the result of the operation

Ex: ROR R1;

SWAP Rd; Swap Nibbles

d 0 to 31

Swaps high and low nibbles in the regster Rd No flags are affected

Ex: SWAP R5;

Branch Instructions

JMP k ; Unconditinal Jump

k 0 to 4Kbytes

The sequence of the program execution is transferred to an address specified in the operand No flags are affected

RJMP k; Relative Jump

k -2Kb to 2Kb

The sequence of the program execution is transferred to relative address specified in the operand No flags are affected

IJMP ; Indirect Jump

The sequence of the program execution is transferred to the address pointed by the Z (16-bits) pointer register The X-pointer register is 16-bits wide and allows jumps within the lowest 128K bytes of the program memory

Ex: IJMP; Jump to the address pointed by Z-pointer register

BREQ k; Branch if Equal (Unsigned)

k - 64Kb to 63Kb

This is Conditional relative branch instruction This instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI The sequecnce of the program execution is transferred to an address specified in the operand if the two numbers (after comparision or subtraction) are equal or else instruction is ignored and goes to the next instuction

BRNE k; Branch if Not Equal (Unsigned)

k - 64Kb to 63Kb

This is Conditional relative branch instruction This instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI The sequecnce of the program execution is transferred to an address specified in the operand if the two numbers (after comparision or subtraction) are not equal or else instruction is ignored and goes to the next instuction

BRLO k; Branch if Lower (Unsigned)

k - 64Kb to 63Kb

This is Conditional relative branch instruction This instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI The sequecnce of the program execution is transferred to an address specified in the operand if the contents of the destination register (after comparision or subtraction) are less than the contents of the source register or number or else instruction is ignored and goes to the next instuction

BRSH k; Branch if Same or Highter (Unsigned)

k - 64Kb to 63Kb

This is Conditional relative branch instruction This instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI The sequecnce of the program execution is transferred to an address specified in the operand if the contents of the destination register (after comparision or subtraction) are same or greater than the contents of the source register or number or else instruction is ignored and goes to the next instuction

CALL k; Call a Subroutine

k - 64Kb to 63Kb

Calls to a subroutine within the entire program memory The execution sequence is transferred to an address of subroutine specified in the operand The return address will be stored onto the stack

RET ; Return from Subroutine

Returns from a subroutine The return address is loaded from the stack

PUSH Rr ; Push Register on Stack

This instruction stores the contents of register Rr on the STACK The stack pointer is post incremented

by 1 after the PUSH

Ex: PUSH R4; Saves contents of the register R4 on the STACK