CHAPTER 13 Programmable Logic Device Architectures

Lời giải CHAPTER 13 Programmable Logic Device Architectures bộ môn Hệ Thống Số. Lời giải bao gồm các bài tập trong sách Digital Systems Principles and Applications 11th edition giúp sinh viên rèn luyện thêm khả năng tư duy giải bài tập

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CHAPTER THIRTEEN - Programmable Logic Device Architectures

13.1 (a) Standard logic refers to SSI and MSI chips that provide basic digital functions

(b) ASICs are ICs that are designed to implement a specific application

(c) Microprocessor/DSP devices control components in a system and manipulate data by

executing a program of instructions,

13.2 The necessary speed of operation for the circuit, cost of manufacturing, system power

consumption, system size, amount of time available to design the product, etc

13.3 Because its functionality is determined by the program of instructions, the "software."

13.4 Speed of operation

13.5 (a) PLDs use programmable electronic switches to create the desired functionality using the logic

hardware available on the IC

(b) Gate arrays use customized interconnections, created during IC fabrication, between the

prefabricated gates on a silicon wafer to create the desired functionality

(b) Standard cells use predefined logic function building blocks to create the desired functionality

in an IC

(c) Full custom employs layout of components and interconnections to design an IC for the

desired application

13.6 Advantages: highest speed and smallest die area

Disadvantages: design/development time and expense

13.7 Fuse, EPROM, EEPROM, Flash, SRAM, Antifuse;

OTP: Fuse and Antifuse;

Volatile: SRAM

13-8 SRAM-based PLDs must be configured (programmed) upon power-up

13-9 (a) LAB (Logic Array Block) is a set of 16 macrocells

(b) PIA (Programmable Interconnect Array) is a bus that connects signal sources and destinations within the CPLD

(c) Macrocell is the programmable logic block containing an AND/OR circuit & a flip-flop to create desired logic functions

13-10 In a PLD programmer or in-system (via JTAG interface)

13-11 Joint Test Action Group (JTAG) interface

13-12 EEPROM

13-13 MAX7000S uses AND/OR array and the MX II uses a look-up table (LUT)

13-14 SRAM

13-15 By configuring itself automatically at power-up from the on-chip configuration flash memory

(CFM)

13-16 Cyclone

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13-17 Volatile

13-18 Cyclone devices can be configured using an external controller (such as a non-volatile PLD or a

microprocessor), a configuration memory device, or a download cable from a PC

13-19 RAM

13-20 Phase-lock loops (PLLs)