PROGRAMMING LIST of EXERCISES

FIGURE 1 Basic 8086 and 8088 systems 2. (a) The 8086 system, illustrating the 16bit data bus, the 20bit address bus, and the control bus. (b) The 8088 system, illustrating the 8bit data bus, the 20bit address bus, and the control bus.

PROGRAMMING

Prof Yung-Sheng Chen

Department of Electrical Engineering

August 1997

TABLE of CONTENTS

CHAPTER 1 INTRODUCTION TO MICROCOMPUTER SYSTEM 6

1 T IME T ABLE OF M ICROPROCESSOR (µP) [1] 6

2 B ASIC M IRCOPROCESSOR A RCHITECTURE 7

3 B ASIC D IAGRAM OF A M ICROCOMPUTER S YSTEM 9

4 CPU B EHAVIOR 10

5 M EMORY I NTERFACE 13

6 I NPUT /O UTPUT I NTERFACE 15

7 O NE -C HIP M ICRO C OMPUTER S YSTEM (MCS-51, 8051 CORE ) 17

CHAPTER 2 8051 ARCHITECTURAL OVERIEW 18

1 P IN D ESCRIPTIONS 18

2 M EMORY S TRUCTURE AND H ARDWARE C ONFIGURATION 21

3 R EGISTER D ESCRIPTIONS 24

4 S UMMARY OF THE 8051 O N -C HIP D ATA M EMORY 28

CHAPTER 3 PROGRAMMER’S GUIDE AND INSTRUCTION SET 29

1 P ROGRAM S TATUS W ORD 29

2 A DDRESSING M ODES 29

3 A RITHMETIC I NSTRUCTIONS 30

4 L OGICAL I NSTRUCTIONS 31

5 D ATA T RANSFERS 33

6 B OOLEAN I NST RUCTIONS 35

7 J UMP I NSTRUCTIONS 37

8 8051 I NSTRUCTION S ET S UMMARY 40

CHAPTER 4 BASIC EXERCISES 47

CHAPTER 5 INTERRUPTS 65

1 I NTERRUPT E NABLES 66

2 I NTERRUPT P RIORITIES 67

3 O PERATION 68

4 E XERCISES FOR I NTERRUPTS 69

CHAPTER 6 TIMER/COUNTERS 71

1 MODE 0 72

2 MODE 1 74

3 MODE 2 75

4 MODE 3 78

5 T IMER S ET -U P 79

CHAPTER 7 SERIAL INTERFACE 80

1 M ODE 0 80

2 M ODE 1 86

3 M ODE 2 AND 3 86

4 B AUD R ATES 86

5 S ERIAL P ORT S ET -U P 91

6 E XERCISES FOR M ODES 1, 2, AND 3 92

CHAPTER 8 REFERENCES 95

LIST of FIGURES

FIGURE 1 B ASIC 8086 AND 8088 SYSTEMS [2] ( A ) T HE 8086 SYSTEM , ILLUSTRATING THE 16- BIT DATA BUS , THE

20- BIT ADDRESS BUS , AND THE CONTROL BUS ( B ) T HE 8088 SYSTEM , ILLUSTRATING THE 8- BIT DATA BUS , THE

20- BIT ADDRESS BUS , AND THE CONTROL BUS 7

FIGURE 2 STRUCTURE OF THE I NTEL 8085 MICROPROCESSOR [3] 8

FIGURE 3 68020- BASED MICROCOMPUTER WITH FLOATING - POINT COPROCESSOR [3] .9

FIGURE 4 B US ACTIVITY FOR AN OPCODE FETCH CYCLE 10

FIGURE 5 O VERVIEW OF CPU BEHAVIOR [3] .11

FIGURE 6 ( A ) A SIMPLE ACCUMULATOR - BASED CPU ( B ) O PERATION OF THE CPU OF ( A ) [3] .12

FIGURE 7 S IMPLIFIED 8086/8088 READ BUS CYCLE [2] 13

FIGURE 8 A PSEUDO - MEMORY COMPONENT ILLUSTRATING THE ADDRESS , DATA , AND CONTROL CONNECTIONS [2] .13

FIGURE 9 ( A ) T HE PINOUT OF THE 2716, 2K × 8 EPROM ( B ) P INOUT DIAGRAM OF THE 62256, 32K × 8 STATIC RAM ( C ) A SIMPLE NAND GATE DECODER USED TO SELECT A 2716 EPROM MEMORY COMPONENT FOR MEMORY LOCATIONS FF800 H -FFFFF H 14

FIGURE 10 T HE BASIC INPUT INTERFACE ILLUSTRATING THE CONNECTION OF EIGH T SWITCHES N OTE THAT THE 74ALS244 IS A THREE - STATE BUFFER THAT CON T ROLS THE APPLICATION OF THE SWITCH DATA T O THE DATA BUS [2] .15

FIGURE 11 T HE BASIC OUTPUT INTERFACE CONNECTED TO A SET OF LED DISPLAYS [2] 15

FIGURE 12 A PORT DECODER THAT DECODES 8- BIT I/O PORT S T HIS DECODER GENERATES ACTIVE LOW OUTPUTS FOR PORTS F0 H -F7 H [2] 16

FIGURE 13 B LOCK DIAGRAM OF THE 8051 CORE [4] 17

FIGURE 14 ( A ) P INOUTS OF 8051 ( B ) S PECIAL FEATURES OF P ORT 3 ( C ) O SCILLATOR CONNECTIONS 18

FIGURE 15 A MORE DETAIL BLOCK DIAGRAM OF 8051 .20

FIGURE 16 MCS-51 MEMORY STRUCTURE 21

FIGURE 17 ( A ) MCS-51 P ROGRAM M EMORY ( B ) E XECUTING FROM E XTERNAL P ROGRAM M EMORY 22

FIGURE 18 ( A ) A CCESSING EXTERNAL D ATA M EMORY I F THE P ROGRAM M EMORY IS INTERNAL , THE OTHER BITS OF P2 ARE AVAILABLE AS I/O ( B ) I NTERNAL D ATA M EMORY ( C ) T HE LOWER 128 BYTES OF INTERNAL RAM ( D) SFR (SPECIAL FUNCTION REGISTERS ) SPACE 23

FIGURE 19 ( A ) R EGISTERS ’ LOCATIONS , AND ( B ) THE SFR MAP IN MCS-51 24

FIGURE 20 128 BYTES OF RAM DIRECT AND INDIRECT ADDRESSABLE 25

FIGURE 21 ( A ) CONTAINS A LIST OF ALL THE SFR S AND THEIR ADDRESSES , ( B ) LISTS THE CONTENTS OF EACH SFR AFTER POWER - ON OR A HARDWARE RESET N OTE THAT , ALL OF THE SFR S THAT ARE BYTE AND BIT ADDRESSABLE ARE LOCATED ON THE FIRST COLUMN OF T HE DIAGRAM IN F IG 19( B ) .26

FIGURE 22 PSW: P ROGRAM S TATUS W ORD R EGISTER 27

FIGURE 23 S UMMARY OF THE 8051 ON - CHIP DATA MEMORY 28

FIGURE 24 A LIST OF THE MCS-51 ARITHMETIC INSTRUCTIONS 31

FIGURE 25 A LIST OF THE MCS-51 LOGICAL INSTRUCTIONS 32

FIGURE 26 A LIST OF THE MCS-51 DATA TRANSFER INSTRUCTIONS THAT ACCESS INTERNAL D ATA M EMORY SPACE

33

FIGURE 27 S HIFTING A BCD NUMBER TWO DIGITS TO THE RIGHT 34

FIGURE 28 A LIST OF THE MCS-51 DATA TRANSFER INSTRUCTIONS THAT ACCESS EXTERNAL D ATA M EMORY SPACE 34

FIGURE 29 T HE MCS-51 LOOKUP TABLES READ INSTRUCTIONS 35

FIGURE 30 A LIST OF THE MCS-51 B OOLEAN INSTRUCTIONS 36

FIGURE 31 U NCONDITIONAL J UMPS IN MCS-51 D EVICE 37

FIGURE 32 C ONDITIONAL J UMPS IN MCS-51 D EVICE 38

FIGURE 33 T HE FIRST CIRCUIT HAVING 8-LED DISPLAY 47

FIGURE 34 D ATA SHEET OF TTL’245 [5] 48

FIGURE 35 B OUNCING SIGNAL 51

FIGURE 36 A 4 × 4 KEY 55

FIGURE 37 T HE ASCII (A MERICAN S TANDARD C ODE FOR I NFORMATION I NTERCHANGE ) CODE [2] 58

FIGURE 38 7- SEGMENT DISPLAY FOR ONE - DIGIT 59

FIGURE 39 7- SEGMENT DISPLAY FOR TWO - DIGIT 60

FIGURE 40 8051 INTERRUPT CONTROL SY STEM 65

FIGURE 41 IE (I NTERRUPT E NABLE ) REGISTER IN THE 8051 .66

FIGURE 42 IP (I NTERRUPT P RIORITY ) REGISTER IN THE 8051 .67

FIGURE 43 I NTERRUPT RESPONSE TIMING DIAGRAM 68

FIGURE 44 TMOD: T IMER /C OUNTER MODE CONTROL REGISTER 71

FIGURE 45 T IMER /C OUNTER 1 M ODE 0: 13- BIT COUNTER 72

FIGURE 46 TCON: T IMER /C OUNTER CONTROL REGISTER 72

FIGURE 47 T IMER /C OUNTER 1 M ODE 2: 8- BIT AUTO - RELOAD 75

FIGURE 48 T IMER /C OUNTER 0 M ODE 3: TWO 8- BIT COUNTERS 78

FIGURE 49 S ETUP OF T IMER /C OUNTER 0 .79

FIGURE 50 S ETUP OF T IMER /C OUNTER 1 .79

FIGURE 51 SCON: SERIAL PORT CONTROL REGISTER 80

FIGURE 52 S ERIAL P ORT M ODE 0 81

FIGURE 53 ( A ) T HE DIAGRAM USING SIPO, AND ( B ) THE FLOWCHART OF THIS PROGRAM 83

FIGURE 54 ( A ) T HE DIAGRAM USING PISO, AND ( B ) THE FLOWCHART OF THIS PROGRAM 84

FIGURE 55 S ERIAL P ORT M ODE 1 TCLK, RCLK AND T IMER 2 ARE PRESENTED IN THE 8052 ONLY 87

FIGURE 56 S ERIAL P ORT M ODE 2 88

FIGURE 57 S ERIAL P ORT M ODE 3 TCLK, RCLK, AND T IMER 2 ARE PRESENT IN THE 8052 ONLY 89

FIGURE 58 PCON: P OWER C ONTROL R EGISTER 90

FIGURE 59 T IMER 1 GENERATED COMMONLY USED BAUD RATES 91

FIGURE 60 ( A ) T HE DIAGRAM , AND ( B ) THE FLOWCHART OF THIS PROGRAM 92

LIST of EXERCISES

EXERCISE 1 NAND, NOR, XOR G ATES 49

EXERCISE 2 20 MSEC T IME D ELAY S UBROUTINE [D ELAY 1] 50

EXERCISE 3 8-LED O N -O FF D ISPLAY W ITH 1 S EC D ELAY 51

EXERCISE 4 K EY -P RESSED C OUNT 51

EXERCISE 5 R UNNING LED S WITH S HIFT I NSTRUCTIONS 53

EXERCISE 6 R UNNING LED S WITH L OOKUP T ABLES 54

EXERCISE 7 4- BY -4 K EY S CAN 55

EXERCISE 8 7-S EGMENT D ISPLAY FOR O NE -D IGIT 59

EXERCISE 9 7-S EGMENT D ISPLAY FOR T W O -D IGIT 60

EXERCISE 10 T HE U SE OF “DIV AB” I NSTRUCTION 62

EXERCISE 11 T HE U SE OF “MUL AB” I NSTRUCTION 63

EXERCISE 12 T HE U SE OF “DA A” I NSTRUCTION 64

EXERCISE 13 E XTERNAL I NTERRUPT 0 69

EXERCISE 14 E XTERNAL I NTERRUPTS 0 A ND 1 70

EXERCISE 15 F OR M ODE 0 73

EXERCISE 16 F OR M ODE 1 74

EXERCISE 17 F OR M ODE 2 75

EXERCISE 18 M EASURING THE C YCLE T IME OF A S QUARE -W AVE 76

EXERCISE 19 E XERCISE FOR M ODE 0: S ERIAL -I N -P ARALLEL -O UT (SIPO, 74LS164) 82

EXERCISE 20 E XERCISE FOR M ODE 0: P ARALLEL -I N -S ERIAL -O UT (PISO, 74LS165) 84

EXERCISE 21 T RANSMIT AND R ECEIVE D ATA BY U SING S ERIAL P ORT M ODE 1 92

EXERCISE 22 T RANSMIT AND R ECEIVE D ATA BY U SING S ERIAL P ORT M ODE 2 OR 3 94

Chapter 1 INTRODUCTION TO

MICROCOMPUTER SYSTEM

1 Time Table of Microprocessor ( µP) [1]

1971 Intel 4004 (↓ 1

MHz)

4-bit 2,300 l First MicroProcessor ( µP)

l 45 instructions

1972 Intel 8008 8-BIT 3,500 First 8-bit MicroProcessor

1974 Intel 8080 (2 MHz) 8-bit (16-bit

8,500 Used in the first O.S., CP/M

1976 MOS Tech 6502 16-bit 9,000 Apple II, Graphic & games

1979 Intel 8088 16-bit (8-bit bus) 29,000 PC & DOS

1979 Motorola 68000 32-bit 68,000 Platform of UNIX and Machintosh

1989 Intel 486 32-bit 1,200,000 l Internal Floating Processor Unit

(PU) and 8 Kbytes Cache

1993 Intel Pentium 32-bit 3,100,000 l Super Vector Structure

l Two pipelines, two instructions can

be executed at the same time

l 2 integer PU and 1 floating PU

1995 Intel Pentium Pro 32-bit 5,500,000 l SUPER VECTOR STRUCTURE

l Three instructions can be executed

at the same time

l The Level 2 cache (256 kbytes or

512 kbytes) is included

2 Basic Mircoprocessor Architecture

FIGURE 1 Basic 8086 and 8088 systems [2] (a) The 8086 system, illustrating the 16-bit data bus,

the 20-bit address bus, and the control bus (b) The 8088 system, illustrating the 8-bit data bus, the 20-bit address bus, and the control bus

FIGURE 2 Structure of the Intel 8085 microprocessor [3]

3 Basic Diagram of a Microcomputer

System

FIGURE 3 68020-based microcomputer with floating-point coprocessor [3]

4 CPU Behavior

FIGURE 4 Bus activity for an opcode fetch cycle

FIGURE 5 Overview of CPU behavior [3]

FIGURE 6 (a) A simple accumulator-based CPU (b) Operation of the CPU of (a) [3]

5 Memory Interface

FIGURE 7 Simplified 8086/8088 read bus cycle [2]

FIGURE 8 A pseudo-memory component illustrating the address, data, and control connections [2]

FIGURE 9 (a) The pinout of the 2716, 2K×8 EPROM (b) Pinout diagram of the 62256, 32K×8 static RAM (c) A simple NAND gate decoder used to select a 2716 EPROM memory component for memory locations FF800h-FFFFFh

(a) (b)

(c)

6 Input/Output Interface

FIGURE 10 The basic input interface illustrating the connection of eight switches Note that the

74ALS244 is a three-state buffer that controls the application of the switch data to the data bus [2]

FIGURE 11 The basic output interface connected to a set of LED displays [2]

FIGURE 12 A port decoder that decodes 8-bit I/O ports This decoder generates active low outputs

for ports F0h-F7h [2]

7 One-Chip MicroComputer System

(MCS-51, 8051 core)

l 8-bit CPU optimized for control applications

l Extensive Boolean processing (single-bit logic) capabilities

l 64 K Program Memory address space

l 64 K data Memory address space

l 4 K bytes of on-chip Program Memory

l 128 bytes of on-chip Data RAM

l 32 bidirectional and individually addressable I/O lines

l Two 16-bit timer/counters

l Full duplex UART

l 6-source/5-vector interrupt structure with two priority levels

l On-chip clock oscillator

FIGURE 13 Block diagram of the 8051 core [4]

Chapter 2 8051 ARCHITECTURAL OVERIEW

l V CC: Supply voltage

l V SS: Circuit ground

l Port 0: 8-bit open drain bidirectional I/O port As an output port each pin can sink 8 LS TTL inputs

The pins have 1’s written to them float, an in that state can be used as high-impedance inputs It is

also the multiplexed low-order address and data bus during accesses to external Program and

Data Memory

l Port 1: 8-bit bidirectional I/O port with internal pullups The output buffers can sink source 4 LS

TTL inputs

l Port 2: 8-bit bidirectional I/O port with internal pullups The output buffers can sink/source 4 LS

TTL inputs It emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @DPTR) During

accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), it emits the contents of the P2 Special Function Register

l Port 3: 8-bit bidirectional I/O port with internal pullups The output buffers can sink/source 4 LS

TTL inputs It also serves the functions of various special features of the MCS-51 as listed in Fig 14(b)

l RST: Reset input

l ALE: Address Latch Enable output pulse for latching the low byte of the address during accesses to

external memory

l PSEN : Program Store Enable is the read strobe to external Program Memory

l EA : External Access enable EAshould be strapped to VCC for internal program executions EA

must be strapped to VSS in order to enable any MCS-51 device to fetch code from external Program memory locations starting at 000h up to FFFFh

l XTAL1: Input to the inverting oscillator amplifier (see Fig 14(c))

l XTAL2: Output from the inverting oscillator amplifier

FIGURE 15 A more detail block diagram of 8051

2 Memory Structure and Hardware

Configuration

All MCS-51 devices have separate address spaces for Program and Data Memory, as shown in Fig 16 The logical separation of Program and Data Memory allows the Data Memory to be accessed by 8-bit addresses, which can be more quickly stored and manipulated by an 8-bit CPU Nevertheless, 16-bit Data Memory addresses can also be generated through the DPTR register

FIGURE 16 MCS-51 memory structure

Fig 17(a) shows a map of the lower part of the Program Memory After RESET, the CPU begins

execution from location 0000h The interrupt service locations are spaced at 8-byte intervals: 0003h for

External Interrupt 0, 000Bh for Timer 0, 0013h for External Interrupt 1, 001Bh for Timer 1, etc

FIGURE 17 (a) MCS-51 Program Memory (b) Executing from External Program Memory

Fig 18(a) shows a hardware configuration for accessing up to 2K bytes of external RAM The CPU in this case is executing from internal ROM Port 0 serves as a multiplexed address/data bus to the RAM, and 3 lines of Port 2 are being used to page the RAM The CPU generates RD and WR signals as needed during external RAM accesses External Data Memory addresses can be either 1 or 2 bytes wide One-byte addresses are often used in conjunction with one or more other I/O lines to page the RAM as shown in Fig 18(a) Two-byte addresses can also be used, in which case the high address byte

is emitted at Port 2

FIGURE 18 (a) Accessing external Data Memory If the Program Memory is internal, the other bits of

P2 are available as I/O (b) Internal Data Memory (c) The lower 128 bytes of internal RAM (d)

SFR (Special Function Registers) space

3 Register Descriptions

(a)

(b) FIGURE 19 (a) Registers’ locations, and (b) the SFR map in MCS-51

DIRECT AND INDIRECT ADDRESS AREA

The 128 bytes of RAM, which can be accessed by both direct and indirect addressing, can be divided into

3 segments as listed below and shown in Fig 20

l Register Banks 0-3: Locations 0 through 1Fh (32 bytes) The device after reset default to

register bank 0 Each register bank contains 8 one-byte registers, 0 through 7

l Bit Addressable Area: 16 bytes have been assigned for this segment, 20h-2Fh Each one of the

128 bits of this segment can be directly addressed (0-7Fh) One way is to refer to their addresses, i.e 0 to 7Fh The other way is with reference to bytes 20h to 2Fh Thus, bits 0-7 can also be referred to as 20.0-20.7, and bits 8-Fh are the same as 21.0-21.7 and so on Each of the 16 bytes

in this segment can also be addressed as a byte

l Scratch Pad Area: Bytes 30h through 7Fh are available to the user as data RAM However, if

the stack pointer has been initialized to this area, enough number of bytes should be left aside to prevent SP data destruction

FIGURE 20 128 bytes of RAM direct and indirect addressable

SPECIAL FUNCTION REGISTERS

(a) (b)

FIGURE 21 (a) contains a list of all the SFRs and their addresses, (b) lists the contents of each SFR

after power-on or a hardware reset Note that, all of the SFRs that are byte and bit addressable are located on the first column of the diagram in Fig 19(b)

ACCUMULATOR (ACC)

ACC is the Accumulator register The mnemonics for Accumulator-Specific instructions, however, refer

to the Accumulator simply as A

B REGISTER

The B register is used during multiply and divide operations For other instructions it can be treated as

another scratch pad register

PROGRAM STATUS WORD (PSW)

The PSW register contains program status information as detailed in Fig 22

FIGURE 22 PSW: Program Status Word Register

P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and 3, respectively

SERIAL DATA BUFFER

The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register When data is moved to SBUF, it goes to the transmit buffer where it is held for serial transmission (Moving a byte to SBUF is what initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer

4 Summary of the 8051 On-Chip Data

Memory

FIGURE 23 Summary of the 8051 on-chip data memory

Chapter 3 PROGRAMMER’S GUIDE AND INSTRUCTION SET

1 Program Status Word

The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU

The PSW, shown in Fig 22, resides in SFR space It contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register bank select bits, the Overflow flag, a Parity bit, and two

user-defined status flags

l Example: MOV A, @R0 (indirect addressing)

REGISTER INSTRUCTIONS

The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry

a 3-bit register specification within the opcode of the instruction Instructions that access the registers this way are code efficient, since this mode eliminates an address byte When the instruction is executed, one

of the eight registers in the selected bank is accessed One of four banks is selected at execution time by the two bank select bits (RS0, RS1) in the PSW

l Example: MOV A, R7 (register addressing)

REGISTER-SPECIFIC INSTRUCTIONS

Some instructions are specific to a certain register For example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is needed to point to it The opcode itself does that Instructions that refer to the Accumulator as A assemble as accumulator-specific opcodes

IMMEDIATE CONSTANTS

The value of a constant can follow the opcode in Program Memory

l Example: MOV A, #100 (immediate constant)

loads the Accumulator with the decimal number 100 The same number could specified in hex digits as

64h

INDEXED ADDRESSING

Only Program Memory can be accessed with indexed addressing, and it can only be read This

addressing mode is intended for reading look-up tables in Program Memory A 16-bit base register (either DPTR or the Program Counter) points to the base of the table, and the Accumulator is set up with the table entry number The address of the table entry in Program Memory is formed by adding the

Accumulator data to the base pointer Another type of indexed addressing is used in the “case jump”

instruction In this case the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data

l Example: MOVC A, @A+DPTR

l Example: MOVC A, @A+PC

l Example: MOV A, ENTRY_NUMBER

The subroutine “TABLE” would look like this:

TABLE: MOVC A, @A+PC

RET

3 Arithmetic Instructions

The menu of arithmetic instructions is listed in Fig 24 The execution times listed assume a 12 MHz clock frequency

FIGURE 24 A list of the MCS-51 arithmetic instructions

Note that any byte in the internal Data Memory space can be incremented or decremented without going through the Accumulator

The “DA A” instruction is for BCD arithmetic operations In BCD arithmetic, ADD and ADDC

instructions should always be followed by a “DA A” operation, to ensure that the results is also in BCD Note that “DA A” will not convert a binary number to BCD The “DA A” operation produces a

meaningful result only as the second step in the addition of two BCD bytes

l Example: ADD A, 7Fh (direct addressing)

l Example: ADD A, @R0 (indirect addressing)

l Example: ADD A, R7 (register addressing)

l Example: ADD A, #127 (immediate constant)

4 Logical Instructions

Fig 25 shows the list of MCS-51 logical instructions Boolean operation (AND, OR, Exclusive OR, NOT) on bytes perform the operation on a bit-by-bit basis That is, if the Accumulator contains

00110101b and <byte> contains 01010011b, then

l Example: ANL A, <byte>

will leave the Accumulator holding 0001001b

FIGURE 25 A list of the MCS-51 logical instructions

l Example: ANL A, 7Fh (direct addressing)

l Example: ANL A, @R1 (indirect addressing)

l Example: ANL A, R6 (register addressing)

l Example: ANL A, #53h (immediate constant)

Note that Boolean operations can be performed on any byte in the lower 128 internal Data Memory space

or the SFR space using direct addressing, without having to use the Accumulator The “XRL <byte>,

#data” instruction, for example, offers a quick and easy way to invert port bits

l Example: XRL P1, #0FFh

The “SWAP A” instruction interchanges the high and low nibbles within the Accumulator This is a useful operation in BCD manipulations For example, if the Accumulator contains a binary number which is known to be less than 100, it can be quickly converted to BCD by the following code:

5 Data Transfers

INTERNAL RAM

Fig 26 shows the menu of instructions that are available for moving data around within the internal memory spaces, and the addressing modes that can be used with each one The “MOV <des>, <src>” instruction allows data to be transferred between any two internal RAM or SFR locations without going through the Accumulator Remember the Upper 128 bytes of data RAM can be accessed only by indirect

addressing, and SFR space only by direct addressing

FIGURE 26 A list of the MCS-51 data transfer instructions that access internal Data Memory space

Note that in all MCS-51 devices, the stack resides in on-chip RAM, and grows upwards The PUSH instruction first increments the Stack Pointer (SP), then copies the byte into the stack PUSH and POP use only direct addressing to identify the byte being saved or restored, but the stack itself is accessed by indirect addressing using the SP register

The “XCH A, <byte>” instruction causes the Accumulator and addressed byte to exchange data The

“XCHD A, @Ri” instruction is similar, but only the low nibbles are involved in the exchange

Consider the problem of “shifting an 8-digit BCD number two digits to the right” Fig 27 shows how this can be done using direct MOVs, and for comparison how it can be done using XCH instructions To aid

in understanding how the code works, the contents of the registers that are holding the BCD number and the content of the Accumulator are shown alongside each instruction to indicate their status after the

instruction has been executed

FIGURE 27 Shifting a BCD number two digits to the right

EXTERNAL RAM

Fig 28 shows a list of the Data Transfer instructions that access external Data Memory Only indirect addressing can be used Note that in all external Data RAM accesses, the Accumulator is always either the destination or source of the data

FIGURE 28 A list of the MCS-51 data transfer instructions that access external Data Memory space

LOOKUP TABLES

Fig 29 shows the two instructions that are available for reading lookup tables in Program Memory Since these instructions access only Program Memory, the lookup tables can only be read, not updated The mnemonic is MOVC for “move constant”

FIGURE 29 The MCS-51 lookup tables read instructions

An example has given in the INDEXED ADDRESSING section of “2 Addressing Modes” In that

example, the table itself immediately follows the RET (return) instruction in Program Memory This type

of table can have up to 255 entries, numbered 1 through 255 Number 0 can not be used, because at the time the MOVC instruction, the PC contains the address of the RET instruction An entry numbered 0 would be the RET opcode itself

6 Boolean Instructions

MCS-51 devices contain a complete Boolean (single-bit) processor The internal RAM contains 128 addressable bits, and the SFR space can support up to 128 other addressable bits All of the port lines are bit-addressable, and each one can be treated as a separate single bit port The instructions that access these bits are not just conditional branches, but a complete menu of move, set, clear, complement,

OR, and AND instructions These kinds of bit operations are not easily obtained in other architectures with any amount of byte-oriented software

Fig 30 shows the instruction set for the Boolean processor

In this example, FLAG is the name of any addressable bit in the Lower 128 or SFR space An I/O line (the LSB of Port 1, in this case) is set or cleared depending on whether the flag bit is 1 or 0

FIGURE 30 A list of the MCS-51 Boolean instructions

Note that the Boolean instruction set includes ANL and ORL operations, but not the XRL (Exclusive OR)

operation An XOR operation (for example: C = bit1 XRL bit2)can be implemented as follows:

CPL C OVER: (continue)

Note that the range of the jump is –128 to +127 Program Memory bytes relative to the first byte following the instruction

7 Jump Instructions

Fig 31 lists a single “JMP addr” instruction, but in fact there are three – SJMP, LJMP and AJMP – which differ in the format of the destination address JMP is a generic mnemonic which can be used if the

programmer does not care which way the jump is encoded

FIGURE 31 Unconditional Jumps in MCS-51 Device

The SJMP instruction encodes the destination address as a relative offset The instruction is 2 bytes long, consisting of the opcode and the relative offset byte The jump distance is limited to a range of –128 to +127 bytes relative to the instruction following the SJMP

The LJMP instruction encodes the destination address as a 16-bit constant The instruction is 3 bytes long, destination address can be anywhere in the 64K Program Memory space

The AJMP instruction encodes the destination address as an 11-bit constant The instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the 11 address bits, followed by another byte containing the low 8 bits of the destination address When the instruction is executed, these 11 bits are simply substituted for the low 11 bits in the PC Hence the destination has to be within the same 2K block as the instruction following the AJMP

For “JMP @A + DPTR” instruction, typically DPTR is set up with the address of a jump table, and the Accumulator is given an index to the table In a 5-way branch, for example, an integer 0 through 4 is loaded into the Accumulator The code to be executed might be as follows:

l Example: MOV DPTR, #JUMP_TABLE

The “RL A” instruction converts the index number (0 through 4) to an even number on the range 0 through

8, because each entry in the jump table is 2 bytes long:

Subroutines should end with a RET instruction, which returns execution to the instruction following the CALL RETI is used to return from an interrupt service routine The only difference between RET and RETI is that RETI tells the interrupt control system that the interrupt in progress is done If there is no interrupt in progress at the time RETI is executed, then the RETI is functionally identical to RET

Fig 32 shows the list of conditional jumps available to the MCS-51 user All of these jumps specify the destination address by the relative offset method, and so are limited to a jump distance of –128 to +127 bytes from the instruction following the conditional jump instruction

FIGURE 32 Conditional Jumps in MCS-51 Device

The DJNZ instruction (Decrement and Jump if Not Zero) is for loop control To execute a loop N times, load a counter byte with N and terminate the loop with a DJNZ to the beginning of the loop, as shown below for N = 10:

LOOP: (begin loop)

LOOP: (begin loop)

(end loop) DEC R1 CJNE R1, #2Ah, LOOP (continue)