03 specification and design of embedded systems

"If the elevator is stationary and the floor requested is equal to the current floor, If the elevator is stationary and the floor requested is less than the current floor, If the eleva

SPECIFICATION AND DESIGN

OF EMBEDDED SYSTEMS

by

Daniel D Gajski Frank Vahid Sanjiv Narayan Jie Gong

University of California at Irvine Department of Computer Science Irvine, CA 92715-3425

Structural components Physical objects Levels

PCBs, MCMs

Differential eq., current−voltage diagrams

Boolean equations, finite−state machines

Executable spec., programs

Processors, controllers, memories, ASICs

Adders, comparators, registers, counters, register files, queues

Gates, flip−flops

Transistors, resistors, capacitors

Analog and digital cells

Modules, units

Microchips, ASICs

Algorithms, flowcharts, instruction sets, generalized FSM

Design methodologies

Capture-and-simulate

Schematic capture Simulation

Specication renement

Languages

Partitioning Estimation Refinement

Video accelerator

Behavioral synthesis Logic synthesis

Software compilation Physical design

Test generation Manufacturing

Introduction Design models and architectures System-design languages

An example Translation Partitioning Estimation Renement Methodology and environments

Models and architectures

Implementation

Design process

Models are conceptual views of the system’s functionality

Models and architectures

Model: a set of functional objects and rules for composing these objects Architecture: a set of implementation components and their connections

Models of an elevator controller

then the elevator remains idle.

then lower the elevator to the requested floor.

"If the elevator is stationary and the floor requested is equal to the current floor,

If the elevator is stationary and the floor requested is less than the current floor,

If the elevator is stationary and the floor requested is greater than the current floor, then raise the elevator to the requested floor."

(req_floor < curr_floor) / direction := down

(req_floor = curr_floor) / direction := idle

(req_floor > curr_floor) / direction := up (req_floor = curr_floor)

/ direction := idle (req_floor = curr_floor) / direction := idle

(req_floor > curr_floor) / direction := up

(req_floor < curr_floor) / direction := down

(req_floor < curr_floor)

/ direction := down (req_floor < curr_floor)

/ direction := up

Up Idle

Down

(a) English description (b) Algorithmic model

(c) State−machine model

Architectures for implementing the elevator controller

Bus

req_floor curr_floor direction

(b) System level (a) Register level

State oriented: Finite-state machine (Mealy model)

S3

start

r2/u1 r1/d1

r3/u2 r1/d2 r2/d1

r3/u1

r2/n

r3/n r1/n

S = { s1, s2, s3}

I = {r1, r2, r3}

O = {d2, d1, n, u1, u2}

f: S x I −> S h: S x I −> O

State oriented: Finite-state machine (Moore model)

r2 r1

r1

r1

r2 r2 r1 r1

r1 r2

r2 r3

r3 r2 r2

r3 r3

r3 r2

r3

r2

r3 r3 r3

State oriented: Finite-state machine with datapath

S

1

(curr_floor != req_floor) / output := req_floor − curr_floor; curr_floor := req_floor

(curr_floor = req_floor) / output := 0

start

State oriented: Petri nets

t3

t2 t1

u(p2) = 1 u(p3) = 2 u(p4) = 0 u(p5) = 1

O(t1) = {p5}

O(t2) = {p3,p5}

O(t3) = {p4}

O(t4) = {p2,p3}

Petri nets

t1

(d) Resource contention (e) Concurrency

Activity oriented: Dataow graphs (DFG)

Output

Output

Dataow graphs

Merits:

support hierarchy suitable for specifying complex transformational systems represent problem-inherent data dependencies

Demerits:

do not express temporal behaviors or control sequencing weak for modeling embedded systems

Activity oriented: Flowchart (CFG)

MAX = MEM(J)

J = 1 MAX = 0

J = J+1

J > N MEM(J) > MAX

start

No Yes

Yes No

end

Structure oriented: Component-connectivity diagrams

Register file

ALULIR RIR

Rightbus

Left

Processor

Programmemory Datamemory

I/Ocoprocessor

Application specific hardware

System bus

Data oriented: Entity-relationship diagram

Order Customer

Product Supplier

Availability

P.O.

instance

Request

Data oriented: Jackson’s diagram

OR

AND Shape

Radius

Users

Heterogeneous: Control/dataow graph

disableenable

, enable / disable A1 A3/ enable A1,enable A2

Data flow graphs

Control flow graph

C

Control/dataow graphs

Merits:

correct the inability of DFG in representing the control of a system correct the inability of CFG to represent data dependencies

Heterogeneous: Structure chart

A,BA,B

Branch

Iteration

Heterogeneous: Programming languages

Imperative vs declarative programming languages:

C, Pascal, Ada, C++, etc.

LISP, PROLOG, etc.

Sequential vs concurrent programming languages:

Pascal, C, etc.

CSP, ADA, VHDL, etc.

Heterogeneous: Object-oriented paradigm

Data Operations

Object

Data Operations

Object

Data Operations Object

Transformation function

Heterogeneous: Program-state machine

variable A: array[1 20] of integer

variable i, max: integer ;

max = 0;

for i = 1 to 20 do

if ( A[i] > max ) then max = A[i] ; end if;

end for

Program-state machines

Merits:

represent system’s states, data, control and activities in a single model overcome the limitations of programming languages and HCFSM models

Heterogeneous: Queueing model

Queue ServerArriving

requests

Arrivingrequests

(a) One server

(b) Multiple servers

Queueing model

Characteristics:

used for analyzing system’s performance, and can nd utilization, queueing length, throughput

Application-specic architectures

Controller architecture, Datapath architecture, Finite-state machine with datapath (FSMD).

General-purpose processors

Complex instruction set computer (CISC) Reduced instruction set computer (RISC) Vector machine

Very long instruction word computer (VLIW)

Parallel processors

Controller architecture

Next−state function

Output

Inputs State register

(a) Three stage pipeline

(b) Four stage pipeline

Next−state function

Microprogram memory

Address selection logic

PC

MicroPC

Control

RISC architecture

Status

Control unit Instruction reg.

Hardwired output and next−state logic

Memory

Register file

ALU

Instr.

cache

Data cache

Datapath

State register

Control

Vector machines

Interleaved memory

Vectorregisters

Scalarregisters

Memory pipes Memory pipes

Vectorfunctional unit

Scalarfunctional unit

Parallel processors: SIMD/MIMD

Control unit

Proc 0Mem 0

Proc 1Mem 1

Proc N−1Mem N−1

(b) Shared memory

Different models focus on different aspects

Proper model needs to represent system’s features

Models are implemented in architectures

Smooth transformation of models to architectures increases productivity

System specication

For every design, there exists a conceptual view

Conceptual view depends on application

Computation : conceptualized as a program Controller : conceptualized as a state-machine

Goal of specication language

Capture conceptual view with minimum designer effort

Ideal language

1-to-1 mapping between conceptual model & language constructs

Characteristics of commonly used conceptual models:

Concurrency, hierarchy, synchronization

Requirements for embedded system specication Evaluate HDLs with respect to embedded systems

VHDL, Verilog, Esterel, CSP, Statecharts, SDL, SpecCharts

Behavior: a chunk of system functionality

e.g process, procedure, state-machine

System often conceptualized as set of concurrent behaviors

Concurrency can exist at different abstraction levels:

Job-level Task-level Statement-level Operation-level Bit-level

Two types of concurrency within a behavior

Data-driven, Control-driven

Data-driven concurrency

Operations execute when input data is available Execution order determined by data dependencies

1: Q = A + B 2: Y = X + P

Q

process A();

process B();

process C();

end behavior X;

Systems often are state-based, e.g controllers

State may represent

mode or stage of being

computation

Difcult to capture using programming constructs

v

w x

Required for managing system complexity

Allows system modeler to focus on one subsystem at a time Enhances comprehension of system functionality

Scoping mechanism for objects like types and variables

Two types of hierarchy

Structural hierarchy Behavioral hierarchy

Structural hierarchy

System represented as set of interconnected components Interconnections between components represent wires Several levels: systems, chips, RT-components, gates

System

e4

e6 e5

e7

e8

behavior P variable x, y;

begin Q(x) ; R(y) ; end behavior P;

Programming constructs

Some behaviors easily conceptualized as sequential algorithms

Wide variety of constructs available

Assignment, branching, iteration, subprograms, recursion, complex data types (records, lists)

type buffer_type is array (1 to 10) of integer;

variable buf : buffer_type;

variable i, j : integer;

for i = 1 to 10 for j = i to i

if (buf(i) > buf(j)) then SWAP(buf(i), buf(j));

end if;

end for;

end for;

X2

q0

q1

q2

q3

start

final state

process P

begin variable x

receive (y);

end

channel C

Concurrent behaviors execute at different speeds

Synchronization required when

Data exchanged between behaviors Different activities must be performed simultaneously

Two types of synchronization mechanisms

Control-dependent Data-dependent

fork A(); B(); C(); join;

R();

end behavior X;

synchronization point

Synchronization by

common event

Synchronization by common variable

Q

Required to represent real world implementations

Functional timing: affects simulation of system specication

min 50 ns

behavior B

behavior Q

behavior P

Embedded system specication

Embedded system: behavior dened by interaction with environment

Essential characteristics

IEEE standard, intended for documentation

and exchange of designs [IEE88]

Characteristics supported

Behavioral hierarchy : single level of processes Structural hierarchy : nested blocks and component instantiations Concurrency : task-level (process), statement-level (signal assignment) Programming constructs

Communication : shared-memory using global signals

Synchronization : wait on and wait until statements Timing : wait for statement, after clause in assignments

Characteristics not supported

Exceptions : partially supported by guarded signal assignments State transitions

Verilog and Esterel

Verilog [TM91] developed as proprietary language

for specication, simulation

Esterel [Hal93] developed for specication of reactive systems

Characteristics supported:

Behavioral hierarchy : fork-join

Structural hierarchy : hierarchy of interconnected modules

Programming constructs Communication : shared registers (Verilog) and broadcasting (Esterel)

Synchronization : wait for an event on a signal

Timing : modeling of gate, net, assignment delays in Verilog

Exceptions : disable (Verilog), watching, do-upto, trap statements (Esterel)

SDL (Specication and Description language)

CCITT standard in telecommunication

for protocol specication [BHS91]

Characteristics supported

Behavioral hierarchy : nested dataow

Structural hierarchy : nested blocks

State transitions : state machine in processes

Communication : message passing

Timing : timeouts generated by timer object

Characteristics not supported

Exceptions

Programming constructs

system block

signal route

CSP (Communicating Sequential Processes)

Intended to specify programs running on multiprocessor machines [Hoa78]

Characteristics supported

Behavioral hierarchy : fork-join using parallel command

Programming constructs

Communication : message passing using input, output commands

Synchronization : blocking message passing

Characteristics not supported

Exceptions State transitions Structural hierarchy Timing

Behavioral hierarchy : sequential/concurrent behaviors

State transitions: TOC (transition on completion) arcs

Communication : shared memory, message passing

Exceptions : TI (transition immediately) arcs

variable MAX : integer ;

MAX := 0;

for J in 0 to 15 loop

if ( A(J) > MAX ) then max := A(J) ; end if;

end loop

type sequential subbehaviors is P : (TOC, u, Q) ; Q : (TOC, v, P), (TOC, w, R); R : (TOC, x, Q);

behavior MAIN begin behavior P behavior Q behavior R end MAIN;

behavior MAIN begin behavior P behavior Q_R begin behavior Q behavior R end Q_R; behavior S end MAIN;

type sequential subbehaviors is P : (TOC, true, Q_R); Q_R : (TOC, true, S); S : ; type concurrent subbehavior is Q : (TOC, true, halt); R : (TOC, true, halt); .

type sequential subbehaviors is P : (TI, e, Q); Q : ; .

behavior MAIN begin behavior P behavior P1 behavior P2 behavior Q end MAIN;

Concurrency Behavioral

Completion Exceptions

VHDL Verilog

CSP Statecharts

SDL Esterel

SpecCharts

Behavioral Hierarchy

State Transitions

Program Constructs

Embedded System Features Language

Feature fully supported

Feature partially supported

Feature not supported

Specication example

An executable specication-language enables:

Early verication Precision

Automation Documentation

A good language/model match reduces:

Capture time Comprehension time Functional errors

Capture an example’s model in a particular language

PSM model in the SpecCharts language

Point out the benets of a good language/model match Highlight experiments that demonstrate those benets

Answering machine controller’s environment

Controller

Line circuitry

recann

hearann

memo

stop rew play fwd

playmsgs

Highest-level view of the controller

The SystemOn behavior

System usually responds

to the line

Pressing any machine button

gets immediate response

SystemOn

RespondToLine

RespondToMachineButton rising(any_button_pushed)

Controller

Line circuitry

The RespondToMachineButton behavior

Controller

Line circuitry

begin

if (play=’1’) then HandlePlay;

elsif (fwd=’1’) then HandleFwd;

elsif (rew=’1’) then HandleRew;

elsif (memo=’1’) then HandleMemo;

elsif (stop=’1’) then HandleStop;

elsif (hear_ann=’1’) then HandleHearAnn;

elsif (rec_ann=’1’) then HandleRecAnn;

elsif (play_msgs=’1’) then HandlePlayMsgs;

The RespondToLine behavior

Monitors line for rings Answers line

Responds to exceptions

Hangup Machine turned off

Controller

Line circuitry

rec ann hear ann memo

play msgs

mic

Announcement unit Tape unit

The Monitor behavior

wait on tollsaver, machine_on;

end loop;

function DetermineRingsToWait return integer is begin

if ((num_msgs > 0) and (tollsaver=’1’) and (machine_on=’1’)) then return(2);

elsif (machine_on=’1’) then return(4);

else return(15);

The Answer behavior

wait until hangup=’1’ for 100 s;

The RemoteOperation behavior

Owner can operate machine remotely by phone Owner identies himself by four button ID

RemoteOperation

code_ok=’1’ code_ok=’0’

hangup=’1’

RespondToCmds CheckCode

if (tone /= user_code(i)) then code_ok <= false;

The answering machine controller specication

Controller

Line circuitry

CheckUserCode

rising(any_button_pushed)

Executable specication use

Precision

Readability/precision compete in a natural language Executable specication encourages precision

Designer asks questions, specication answers them

Language/model match (SpecCharts/PSM):

Hierarchy State-transitions Programming constructs Concurrency

Exceptions Completion Equivalence of states and programs