The architecture of computer hardware and systems software an information technology approach ch12

The CPU Downward software compatibility  Disabled protected mode  Compatible with the original 8088 architecture  Original Intel 8088 CPU  16-bit processing and registers  16-bit i

Chapter 12

Three System Examples

The Architecture of Computer Hardware

and Systems Software:

An Information Technology Approach

3rd Edition, Irv Englander John Wiley and Sons 2003

Three System Examples

 X86 Family

 PowerPC

 IBM System 360/370/390/zSeries

Family

System Overview

 Bus-oriented system I/O

 Nonmaskable interrupts

 Emergency situations

 Single maskable interrupt

 Supports 32 prioritized interrupts

 IRQ0 to IRQ31

 Upon receiving an interrupt, the CPU

reads an address on the data lines that

is used to jump to the interrupt routine

The CPU

 Downward software compatibility

 Disabled protected mode

 Compatible with the original 8088 architecture

 Original Intel 8088 CPU

 16-bit processing and registers

 16-bit internal data bus

 8-bit external data bus

 20-bit memory addressing – 1Mbyte total

 Current Pentium CPUs

 256-bit internal data bus

 64-bit external data bus

 2 levels of memory caching

 Added floating point, multimedia, virtual storage, and multitasking support

 Instruction pointer, and various control registers

 80386 – added 2 segment registers

 80486

 8 80-bit floating point registers

 Various floating point control registers

 Pentium MMX

 added registers for multimedia support

 Pentium III

General Purpose Registers

Instruction Set and Format

Real Mode vs Protected Mode

Real Mode

Protected Mode

Advanced Design Features

 Calculates addresses the same way as real mode

 Allows the system to run several 8086 tasks at

once

X86 Protection Levels

CPU Organization

 Early processors

 Pipelined instruction fetch unit

 Single integer execution unit

 Current processors

 Modern superscalar, pipelined design

 Instruction decoder creates an intermediate set of micro-operations, μopsops

 μopsops translate variable length and complex

instructions into a 3-operand fixed length format

IA-64 Itanium Architecture

 EPIC Architecture

 Incorporates entire X86 instruction set and memory model

 128 65-bit registers for programs

 128 80-bit floating point registers

 8 64-bit branch registers

 64 1-bit predicate registers

 Instead of instruction reordering, speculation and

predication is used for branch predictions

 IA-64 Mode

 64-bit logical addresses

 63-bit physical addresses

System Overview

 Developed by Apple, Motorola, and IBM

 Bus-oriented I/O architecture that can

be interfaced with standard buses of

other personal computers

 Permits system components, bus

adapters, and devices developed for

other computers to be used with the

PowerPC processor

 Prioritized multi-level internal interrupts

The CPU

 RISC design

 32-bit implementation

 32-bit registers and addressing

 Up to 36-bit physical and 52-bit virtual addresses

 64-bit implementation

 64-bit registers and addressing

 Superscalar design

 Only 40 bits of interface to physical storage

 Can run programs written for the 32-bit implementation

 Supports floating point calculations, memory caching, and virtual memory

 More current implementations also support vector

PowerPC Processor

Characteristics

 32 general purpose registers

 32 floating point registers

 32 128-bit vector processing registers

 2 vector control registers

PowerPC User Registers

 15 Different instruction formats

 No specifically designed I/O instructions

because PowerPC uses memory mapped I/O

Typical Instruction Formats

Addressing Modes

Address Translation Mechanisms

Advanced Design Features

 Two levels of system access

 Supervisor (privileged) state

 User (problem) state

 Memory is protected at the segment,

page, and block levels

 “Hint” bits in branching instructions aid

in making accurate branch predictions

CPU Organization

 Superscalar, pipelined design

 Cache memory is standard

 Execution units in the PowerPC 4751 CPU

The IBM 360/370/390/zSeries

The CPU

 Architecture is compatible for every model of the zSeries

 24-bit, 31-bit, and 64-bit addressing

 16 address space registers permits access to one of fifteen 16EByte spaces

 Present and previous Program Status Word (PSW) formats are supported

 64-bit partitioned, segmented, and paged

virtual storage and cache memory

zSeries Specifications

S/390 Registers

 16 64-bit general purpose registers

 16 64-bit floating point registers

 16 special 64-bit control registers

zSeries User Registers

 Similar to storage addressing with the

addition of an index value

Address Translation Mechanisms

Real-to-Absolute Translation

Advanced Features

 Many features can be enabled or disabled with simple control register instructions

 Clock synchronization between systems

 Cluster support with data integrity control and workload

balancing

 Built-in diagnostics that can shift work from one CPU to another

 Multiple forms of hardware system protection

 System Protection Features

CPU Organization

 S/360 and S/370

 Traditional control unit – arithmetic/logic

unit model

 More current processors

 Modern CPU design with multiple fetch and execution units

S/390 System Block Diagram