victor grimblatt rd group director, digital IC design,

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Digital IC Design

Victor Grimblatt R&D Group Director

SASE 2012

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Introduction

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Mobile

0 20 40 60 80 100

2010 2011 2012 2013 2014 2015

Handset IC Market Value ($B)

0 3 6 9 12 15

2010 2011 2012 2013 2014 2015

Tablet IC Market Value ($B)

$38B to $109B in non-memory ICs in 5 years!

Source IBS, February 2011

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Smart Everything

Lines of Code

SW & E/E

% Vehicle Cost

Software Sensors Microprocessors

Storage Communication

“Smart”

33% 1M

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Applications

Electronics

~$1.31T Semi

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What Drives the Drivers?

Power Performance

Cloud

Infrastructure

Power/Cost/Perf Integration

“Smart”

Performance

Power

Mobile

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Advanced Designs and Tapeouts

Source: Synopsys Global Technical Services

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Leading the Way at 32/28nm Design

> 370 32/28nm Active Designs

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Advanced Design Trends

56% of Respondents Currently Designing at 45nm or Below

Source: 2011 Synopsys Global User Survey

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Last Current Next

Power Performance Requirements Drive Node Migrations

48% of “Next Designs” ≤ 32nm!

“Next Design” is this Year!

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Clock Frequency Trends

Frequency is Increasing Over 1GHz

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Designs Are Growing More Complex

Memory = 48% of Gate Count (on average)

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OS Support Design Management Post-silicon Validation Masks

Physical Design RTL Verification RTL Development Spec Development

IP Qualification

Hardware/Software Development Costs

Software Is Half of Time-to-Market

Source: IBS, Synopsys

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Electronic Systems, an Historic Prospective

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Key Innovations in Electronics: Audio/Video

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Key Innovations in Electronics:

Audio/Video

2005 Sonos

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Key Innovations in Electronics: Computers & Communications

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Going to a satellite not so far away!

Apollo Guidance Computer, ~100 Microns, MIT

Source: MIT, 1961

1961

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Key Innovations in Semiconductors

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Once Upon a Time …

April, 1961 first integrated circuit developed by Robert Noyce, from Fairchild Semiconductor

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A 10,000X Improvement, Thanks To…

“A Computer Code Entitled SCALD […] Speeds the Job”

Source: Lawrence Livermore National Laboratory, Newsline, January 10 th , 1979

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Time Flies Away …

DEC Alpha 21064, 64bits, 750 nm CMOS, 200Mhz

Source: Wikimedia Commons; Courtesy of A Domic

1991

300 DMIPS

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Another Time Stamp …

Itanium, 180 Nanometers, Intel

Source: Intel, 2001

2001

~25 GOPS

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DDR CTRL1

CSI

DSS

• Application processor for

smart phones and tablets

– Dual ARM Cortex A9

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Area = 1

Area = 0.5

Gordon E Moore’s Law

Twice the Number of Transistors for the Same Price, Every Two Years

“The complexity for minimum component

costs has increased at a rate of roughly a

factor of two per year Certainly over

the short term this rate can be expected to

continue, if not to increase Over the

longer term, the rate of increase is a bit

more uncertain, although there is no

reason to believe it will not remain nearly

constant for at least 10 years.” Gordon E

Moore, Electronic Magazine, April 19 th ,

1965

The Scaling Factor

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Ley de Moore

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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Wafer 1” – 1959

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Wafer 300 mm

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Proyecciones para el 2000 en 1975

Moore no siempre tuvo razón

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Design - Layout

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Design - Layout

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Plotter

1970 – From Manual Layout to Manufacturing

Mainframe-500 lbs 128k; 8-16 bit

33 MB Disk

Keyboard, Tablet and CRT

Digitizing Table/Tablet

Mag Tape-Output

Photo-Mask Generation

* Computer Aided Manufacturing

The Age of the Gods SENSES

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Design - Layout

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Standard Cells & Channel Routing

Source: GE Avionics, 1968

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Technology Or… Art?

Source: Intel & MoMA, 1974

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Design - Synthesis

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Design - Fab

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Design - Fab

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Design - Verification

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Logic Synthesis

Flex Cathedral Ptolemy

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Place &

Route Logic

Synthesis High-Level

Design DRC/LVS Discipline Multi

Innovators

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Synopsys Design Flow

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Verify: verify the correctness of

design and implementation

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Bottom – up / Top – down

• Bottom – up

– Start from simple modules

– Goes to complex modules

– Suitable to create small parts that will be reused

• Top – down

– Start from complex modules

– Goes to simple modules

– Suitable for big systems

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Bottom – up / Top – down

Complex system

Module (one function)

Register and gates

Transistors

Top – down Bottom – up

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Front End

Architecture

Functional Verification

RTL Design/Logic Synthesis

Physical Design Integrity Design

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The Front End

Architecture:

• Key Algorithms (filtering, for example)

• Amount of on-chip Memories, sizes?

• How many Integer Proc Units?

RTL: Register Transfer Language

• Verilog (1988), VHDL, SystemVerilog: an executable spec for the chip, amounting to over a million lines of code

• Lots of simulations to verify the spec (literally billions of cycles)

• Timing constraints, clock definitions, etc

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The Front End

Logic Design: convert the RTL to logic gates

(NAND-NORs, NOTs, Registers)

• A manual process in the past, still mostly manual for Analog

• Logic Synthesis (1989): automate the process

• Many discrete optimization techniques used here: boolean minimization, static timing analysis, state equivalence, etc, etc

• End point is a “netlist”, meaning a set of logic gates and their connections A large netlist is in the 10s of millions of gates

• Can be simulated or “formally verified” versus the RTL

• Key technique: how do you prove that two logic equations are equivalent?

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complete the connections

• Note that connections do have R and C (to substrate and coupling between wires) so they introduce delay! Meeting timing can be very difficult!

• The Power and Ground lines usually get decided here

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• Note may have to add logic: repeaters to

restore signals a key example

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The Back End

Routing

• Complete all the connections!

• But, need to meet timing and keep signal integrity This also involve separating some wires, for example, to avoid bad

couplings

• Automation is the norm here (1980)

Verification:

• Spacing and sizing rules are checked for all polygons (1980)

• Parasitics are extracted, netlists back annotated and time

analyzed using static techniques (1990)

• Manufacturing requires complicated rules, such as wire density been “uniform”

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Design Goes to Fabrication

Sounds simple, but have a host of

very hard problems to solve!

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…the steps you take to design a chip!

What’s a design flow?

Technology Process

Blah blah blah yada yada Blah blah blah yidie yadie

So on and so forth

on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back

Gate-level netlist

Testbench

on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Specification

Scripts Initial constraints

System Analysis

System Studio

Logic Modeling

Select Architecture

Module Compiler

Models / IP

Library Compiler DesignWare Library VERA

Gate-level verification

Links-to- Layout Design Planning

on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back GDSII

Physical Compiler JupiterXT

Proteus

Physical Design Checks

STAR-RCXT Hercules

RTL Gates

Design Constraints

Mask Writer

CATS

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Technology Process

Gate-level netlist

Testbench

on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Specification

Scripts Initial constraints

System Analysis

System Studio

Logic Modeling

Select Architecture

Module Compiler

Models / IP

Library Compiler DesignWare Library VERA

Gate-level verification

Links-to- Layout Design Planning

on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back GDSII

Physical Compiler JupiterXT

Proteus

Physical Design Checks

STAR-RCXT Hercules

RTL Gates

Design Constraints

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Verification IP Implementation

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Classic IC Design Flow

Architectural choices, RTL compilation and simulation

(VCS)

Logic synthesis (Design Compiler)

Formal verification (Formality)

Generation of test patterns (TetraMAX)

Physical design (IC Compiler)

Physical verification (Hercules)

Layout parasitics extraction (StarRC)

SPICE level simulation of completed design (HSPICE)

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Architectural choices, RTL Compilation and Simulation (VCS)

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• Trace drivers and loads of a

signal at any time to see the

drivers and loads that caused a value change and see all the

drivers/loads that possibly

contributed to a signal value

RTL and Gate Signal

Comparison

Highlighting the net in level schematic and Verilog

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Logic Synthesis

(Design Compiler)

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Introduction to Design Compiler

Design Compiler performs logic synthesis and

optimization of design

• Synthesizes HDL designs into optimized

technology-dependent gate-level designs

• Results in smallest and fastest logical representation of a given function

• Design Compiler supports a wide range of flat and

hierarchical design styles

• Combinational and sequential designs can be optimized for

• timing

• area

• power

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