Embedded systems structure

o Between I/O devices, memories, and CPUo Data bus: transfers data o Address bus: transfers address information o Control bus: transfers control signals... Types of MemoriesProgram and D

Embedded Systems Structure

Amr Ali Abdel-Naby Embedded Systems Developer

amraldo@hotmail.com

+2-012-3600-207

Part I: Embedded Systems Structure

• Composition of Embedded Systems

• Processor

• System Bus

• Memory Devices

• Peripherals

What is an Embedded System?

• A system composed of HW + SW to perform a dedicated function.

• On average, a human being meets 100s of embedded systems daily

Embedded System Components

Part I: Embedded Systems Structure

• Composition of Embedded Systems

• Processor

• System Bus

• Memory Devices

• Peripherals

The Processor

• The core of a digital system

• AKA CPU

• Performs arithmetic, control, data, and I/O operations

• A small IC that embeds everything a CPU needs is called a microprocessor.

• Nowadays, this IC is called a SOC

The Processor Structure

• Registers

• ALU: Arithmetic Logic Unit

• CU: Control Unit

• Internal Bus

CU

ALU Registers

Internal Bus

• Temporal storage inside the CPU

o Flip-flops + latches

• General purpose register

o Carry out program or data processing

Instruction Decoder

o Between I/O devices, memories, and CPU

o Data bus: transfers data

o Address bus: transfers address information

o Control bus: transfers control signals

MCU, MPU, and SoC

• System on Chip (SoC)

o Several semiconductors integrated into a single chip

o Modern CPUs are in SoC forms

o The whole system is integrated on a single chip

 SW + HW

• MCU, MPU

o Another naming of an SoC

 Depends on vendor

• A list of acceptable processor instructions

• Designed to achieve a specific result

Machine Code and Assembly

Language

• Machine code

o 1’s and 0’s only

o Understood by processor only

o Inconvenient to write a program with

Assembler and Assemble

• Instruction = Op Code + Operand

o Op Code is an action taken by a processor

o Operand is the target the Op Code should take action to

Op Code: ADD Operands: A, B, C Symantec: Add register B and register C and put result in register A

ADD A,B,C

Part I: Embedded Systems Structure

• Composition of Embedded Systems

• Processor

• System Bus

• Memory Devices

• Peripherals

System Bus Architectures

Data Memory

Part I: Embedded Systems Structure

• Composition of Embedded Systems

• Processor

• System Bus

• Memory Devices

• Peripherals

Types of Memories

Program and Data Storage High

Tens of ns NOR

Read and WRITE with block units, High Capacity Data Storage

Low Tens of ns

NAND Flash

Small size data or program storage High

Tens of ns EEPROM

Non-Volatile

Memory

Main memory Low

Tens of ns DRAM

Cache High

Several ns, Fast SRAM

Volatile

Memory

C/CsUse

CostSpeed

Types

Random Access Memories

 Does not need refreshing

o Dynamic RAM (DRAM)

Cache Memory System

System performance is lowered due

to slow bus and memory regardless

of high speed CPU

CPU

400 MHZ

Main Memory

10 MHZ

CPU + Cache

400 MHZ

Main Memory

10 MHZ

Improved performance by accompanying CPU with a high speed memory to store frequently

accessed instructions/data

Read Operation with a Cache

• Cache hit

o A requested instruction or data is in cache

o Cache performance is high when cache hit rate is high

• Cache miss

o A requested instruction or data is not in cache

o Cache performance is low when cache miss is high

Write Operation with a Cache

Memory Management Unit

Physical Address

Part I: Embedded Systems Structure

• Composition of Embedded Systems

• Processor

• System Bus

• Memory Devices

• Peripherals

I/O Device

• Exchanges information with CPU

• Includes digital and non-digital signals

• Only digital signals are exchanged directly with the CPU

CPU Signals

Device Signals

I/O Device Address Allocation

• Allocation is necessary to control each I/O device

• I/O mapped I/O

o Exclusive I/O address space

o Widely used in PC world

• Memory mapped I/O

o Uses unused regions of normal memory addresses

o Widely used in embedded world

Memory Mapped I/O vs I/O

Mapped I/O

Example CPUs ARM, PowerPC, M68K, Intel x86 Intel x86

I/O Device Domain A memory region Exclusive I/O region

Instruction Access both memory and I/O devices

Address distinguishes both. Separate memory and I/O device instructions

Hardware A decoder interprets the address and decides

whether to select a memory or I/O device

CPU has a separate signal that distinguishes memory address and I/O addresses

Remarks I/O region must be set Non-cacheable areaI/O region variables must be declared as

volatile type variable

I/O Resource Management

• Polling

o A program continuously checks the device

o Existence, data requests, operations completion, …

• Interrupt

o If a device needs a transaction, it interrupts the processor

o A processor executes a single instruction at a time

o Multitasking can be supported if interrupts are in use

• Direct Memory Access (DMA)

o Allows I/O device and memory to transfer data between each other without CPU interference

I/O Device

IRQ IRQACK

IRQ IRQACK

Interrupt Generation

• Interrupt request

o An I/O device requests an I/O operation with the CPU

o I/O device generates interrupt, so the CPU performs some operations without the program control

o The CPU performs some operations to decide whether to process the interrupt or not

o The code that processes the interrupt is called Interrupt Service Routine (ISR)

o Interrupt vector is the memory location where the ISR rsides

• Examples

o Data reception complete

Flow Control when Interrupt is Generated

Practice I: Embedded Systems Development

• Please refer to the labs handouts