Đồ án HDL PROJECT REPORT VERILOG HDL SIMULATIONLABS

Đồ án HDL PROJECT REPORT VERILOG HDL SIMULATIONLABS

TRƯỜNG ĐẠI HỌC CẦN THƠ

1/ Nguyễn Bá Quốc Huy MSSV : B1306150

2/ Nguyễn Lê Khanh MSSV : B1306158

3/ Lê Quốc Huy MSSV : B1306149

4/ Dương Văn Đoan MSSV : B1306135

5/ Nguyễn Tấn Tài MSSV : B1306195

6/ Nguyễn Trung Nhân MSSV : B1306179

TABLE OF CONTENT

Verilog HDL Simulation Labs ……… Page 3 Lab 1 : Building Hierarchy ……….Page 4 Lab 2 : Simulation/Verification ……… Page 7 Lab 3 : Memory ………Page 11 Lab 4 : n-bit binary counter ………Page 16 Lab 5 : Comparator ……….Page 22 Lab 6 :Arithmetic Logic Unit (ALU)……… Page 26

Verilog HDL Simulation Labs

Overview

The Verilog simulation labs in this course are designed to maximize your hands on introduction to Verilog coding Therefore, you are asked to create all hardware modules and testbenches from scratch After finishingthese labs, you will gain the level of coding skill, syntax proficiency, and understanding that can only be achieved through meaningful practice and effort

Most of the early lab exercises are standalone tasks that reinforce and illustrate language concepts that are fundamental to all Verilog coding

Objectives

After completing these labs, you will be able to:

• Write RTL descriptions for simple circuits

• Create a structural Verilog description for simple circuits

• Build hierarchy by using Verilog

• Create a Verilog testbench to verify the hierarchical structure created in the

previous steps

• Use the simulation software

• Create basic input stimulus

Lab 1: Building Hierarchy

Request :

In this lab, you will write a complete RTL description for the modules MY_AND2 and MY_OR2 and build the circuit shown below (Figure 1)

in a structural Verilog description of the top-level module AND_OR

This lab comprises three primary steps: You will create a software

project; write RTL descriptions; and check the syntax of your RTL code

Verilog Code:

// This is module AND_OR in Labs 1

// Design name : AND_OR

// File name : AND_OR.v

Synthesis output:

Lab 2: Simulation/Verification

Request :

In this lab, you will write a Verilog testbench for the AND_OR module

completed in the previous exercise As part of the testbench, you will create a simple input stimulus by using both concurrent and sequential statements

Examine the circuit below (Figure 2) In this lab, you will write a

complete Verilog testbench description for the module AND_OR.

This lab comprises four primary steps: You will create a new project and import Verilog source files; create a testbench with the Verilog testbench

wizard in the simulation software; create initial and always input stimulus

statements; and, finally, verify the logic structure and functionality by running a simulation and examining the resulting waveforms.

Simulation Result:

Waveforms:

Lab 3: Memory (ROM)

Request :

In this lab, you will write a complete RTL description for a ROM module

by using a one-dimensional array and a Verilog reg data type and a case

memory array using case statement; create a testbench with the Verilog

testbench wizard in the simulation software; finally, verify the logic structure and functionality by running a simulation and examining the resulting waveforms

Simulation result:

Lab 4 Counter

Request :

In this lab, you will write a complete RTL description for the module

CNTR by using parameter statements to specify the bit width This is an

n-bit binary, up/down, loadable counter, with active-Low asynchronous reset You will then build a Verilog HDL testbench to verify the

functionality of the RTL code as well as the hardware it models.

Examine the circuit below (Figure 3) In this exercise, you will create a fully functional binary counter that can be dynamically scaled to any

length The use of parameter statements is an important tool for module

reuse and source code readability The circuit is an n-bit binary, up/down loadable counter, with active- Low asynchronous reset

This lab comprises three primary steps: You will create a software project; declare

the parameter statements; and, finally, create a testbench to verify the design.

Create the input stimulus:

1 Set the CLOCK input to toggle at a rate of 100 MHz

2 Assert the RESET input at time 15 ns, hold for 25 ns, then de-assert

3 Set the CE input initially High, de-assert (set Low) at time 300, hold for 100 ns,

load_tb = 0; //Load initially Low,

begin //toggle High at time 500ns

Lab 5 Comparator

Request :

In this lab, you will write description for the module COMP

(Synchronous Comparator) using an if/else statement.

Examine the circuit below (Figure 4):

This lab comprises four primary steps: You will create a software project;

create an RTL version of COMP; and, finally, create a testbench to verify

that the behavioral model functions correctly

If the expected result and the data are equal, the result is TRUE;

otherwise, the result is FALSE

Declarations of input and output are shown in the following table:

Waveform

Lab 6 Arithmetic Logic Unit (ALU)

Request :

In this lab, you will write a complete RTL description for the module

ALU The op-codes and functionality of the synchronous ALU is

described below

Use a case statement to describe the functionality for the ALU as shown

in the following table, which shows the SELECTION OPCODE and the

operation/function for each Do not forget the ENABLE input

Verilog Code:

// Module name : alu

// File name : alu.v

4'b0010 : alu_out = a_in + b_in;

4'b0011 : alu_out = a_in + b_in + 1;

4'b0100 : alu_out = a_in + (~b_in);

4'b0101 : alu_out = a_in + (~b_in) + 1;

4'b0110 : alu_out = a_in - 1;

4'b0111 : alu_out = a_in && b_in;

4'b1000 : alu_out = a_in || b_in;

4'b1001 : alu_out = a_in ^ b_in;

Simulation Result: