FPGA BASED DESIGN AND IMPLEMENTATION FOR OPTICAL TRANSPORT NETWORKS

The design of the system based on the Field Programmable Gate Array FPGA and Gigabit optical network is discussed.. Some software tools are used to assist the design process and download

VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITY

UNIVERSITY OF SCIENCE

HA VAN KHA LY

FPGA-BASED DESIGN AND IMPLEMENTATION FOR OPTICAL TRANSPORT NETWORKS

Master Thesis in Electronic Engineering

(Specification in Microelectronics & IC Design)

SUPERVISOR: Dr BUI HUU PHU

HCM CITY, 2010

Thanks to all of my lecturers in HCM University of Science such as Prof Dr Dang Luong Mo, Prof Dr Nguyen Huu Phuong, Prof Dr Dinh Si Hien, Dr Bui Trong Tu and Dr Huynh Huu Thuan for their knowledge of the microelectronic, IC design and their patiences during my master course I have learned a lot from them

I would like to thank to my brother, Dr Ha Hoang Kha, for all his help me through my thesis, especially in providing me the IEEE papers and the related softwares

I acknowledge the kindly supports from Arrive Technologies Viet Nam The thesis might be impossibe without the supports from the company Particularly, I also would like to thank Mr Do Dinh Duc for his kind assistant, suggestion on explaining FPGA implementation, and for providing an excellent atmosphere at Arrive technologies Lab, and guidance especially in using AT FPGA board version 1.0 development board and configuration of the related software

Finally, I sincerely thank to all my friends and all those whoever has helped

me either directly or indirectly in the completion of my final year project and thesis

ABSTRACT

The thesis presents an approach to system design and implementation for optical transport networks The design of the system based on the Field Programmable Gate Array (FPGA) and Gigabit optical network is discussed Gigabit optical network interfaces provide fixed functionality and are optimized for sending and receiving large packets All modules are designed using Verilog Hardware Description Language (HDL) and implemented using AT FPGA board version 1.0 The board is connected to computer and Quartus II Version 8.0 is used

to design, compile and implement for the hardware All processing is executed in

AT FPGA version 1.0 board and only requires the input data to the hardware throughout interfaces To test and analyse results, input and output data are displayed to computer, and the results are compared using HyperTerminal or Telnet command Softwares and tools used in this project include Verilog HDL Design Entry Altera Quartus II 8.0 Some software tools are used to assist the design process and downloading process into Altera FPGA chip Stratix II EP2S180, while

AT FPGA board version 1.0 is used to implement the designed module The experimental results at Gigabit Ethernet receiving interface indicate that the optical interface can receive all packet sizes and store them in SDRAM at Gigabit Ethernet line rate

TABLE OF CONTENTS

ABSTRACT 2

CHAPTER 1 : INTRODUCTION 9

1.1 Introduction 9

1.2 Project objectives 11

1.3 Project scope 11

1.4 Thesis outline 12

CHAPTER 2 : FPGA AND HDL CHIP DESIGN 14

2.1 Introduction 14

2.2 FPGA architecture overview 15

2.3 Stratix II FPGA 17

2.4 Hardware description language 21

2.4.1 Introduction 21

2.4.2 Verilog HDL Structure 22

CHAPTER 3 : PRINCIPLES AND APPLICATIONS OF OPTICAL COMMUNICATIONS 30

3.1 Optical fiber communication technology 30

3.2 System overview, trends and advances 34

3.3 Standard and devices requirements 37

3.3.1 Standard 37

3.3.2 Devices requirements 41

CHAPTER 4 : FPGA-BASED DESIGN AND IMPLEMENTATION 47

4.1 Overview of the design 47

4.2 Software design 51

4.3 Hardware design 52

4.3.1 High speed 8B/10B Encoder and Decoder Design 66

4.3.2 Details of the Encoding Process 67

4.3.3 FIFO Functionality 72

4.4 Download the design into hardware 78

CHAPTER 5 : SIMULATION RESULTS AND EXPERIMENTAL TESTS ON FPGA CHIPS 80

5.1 Introduction 80

5.2 Individual component test 80

5.2.1 8B/10B encoder and decoder implemetation and simulation results 80

5.2.2 FIFO Implemetation and simulation results 86

5.2.3 System compilation 93

5.2.4 Breadboard prototype test 94

5.3 System level testing for transmitter and receiver 97

5.3.1 Optical link test 97

5.3.2 Gigabit Ethernet test 97

CHAPTER 6 : CONCLUSION AND FUTURE WORK 100

6.1 Conclusion 100

6.2 Future work 101

REFERENCES 102

List of Figures

Figure 2.1: Structure of an FPGA 15

Figure 2.2: SRAM-controlled Programmable Switches 16

Figure 2.3 : Actel Antifuse Structure 17

Figure 2.4: Top view Stratix II 18

Figure 2.5: Stratix II Block Diagram 19

Figure 2.6: 1,020-PIN FPGA Package Outline 20

Figure 2.7: Verilog 21

Figure 3.1: Optical transmitter and receiver 31

Figure 3.2: Fiber to the X (FTTX) 33

Figure 3.3: Enterprise LAN Topology 33

Figure 3.4: Today’s networks 34

Figure 3.5: Total Traffic Bandwidth Increases 35

Figure 3.6: Convergence of Ethernet and Optical transports 35

Figure 3.7: Overview of optical transport networks 36

Figure 3.8: Relationship of IEEE 802.3 layering model to OSI reference model 39

Figure 3.9: SPLC-20-4-X-BX 41

Figure 3.10: Diagram of host board connector block pin numbers and names 42

Figure 3.11: Block diagram of SFP 44

Figure 3.12: Single-mode fiber and multimode fiber 45

Figure 3.13: HDMP-1636A/46A/T1636A transceiver 46

Figure 4.1: Design flow using Quartus II 48

Figure 4.2: Design flow 48

Figure 4.3: Full IC Design Flow 51

Figure 4.4: Quartus II Software Basic Design Flow 52

Figure 4.5: Stratix II block diagram 54

Figure 4.6: Top-level block diagram of the system 55

Figure 4.7: FPGA Stratix II 56

Figure 4.8: Block diagram of Gigabit Ethernet 57

Figure 4.9: Block diagram of MAC 57

Figure 4.10: MAC control frame format 58

Figure 4.11: Format of frame preamble 59

Figure 4.12: Shift register generating CRC-8 60

Figure 4.13: Functional block diagram 65

Figure 4.14: The 8B/10B Encoder and decoder in a system stransmission 66

Figure 4.15: The 8B/10B coding scheme 67

Figure 4.17: First-in, first-out functionality gives a FIFO register file a specific directionality

72

Figure 4.18: A typical block diagram of a synchronous FIFO 74

Figure 4.19: The illustrative examples of FIFO occupancy 75

Figure 4.20: A typical block diagram of a asynchronous FIFO 76

Figure 4.21: FIFO state machine transition diagram 77

Figure 4.22: FPGA daughter board 78

Figure 4.23: AT FPGA mother board and daughter board 79

Figure 4.24: The Gigabit Ethernet fibre optical connection 79

Figure 5.1: Encoder Block Diagram 81

Figure 5.2: Decoder Block Diagram 81

Figure 5.3: Schemetic Symbol of an 8B10B Encoder 82

Figure 5.4: Schemetic Symbol of an 8B10B Decoder 83

Figure 5.5: Encoder 8B10B Timing Diagrams 85

Figure 5.6: Decoder 8B10B Timing Diagrams 85

Figure 5.7: Schemetic Symbol of an Asynchronous FIFO 87

Figure 5.8: Initial write operations to an FIFO 91

Figure 5.9: Read and Write Operations to an Almost Full FIFO 92

Figure 5.10: Read and Write Operations to an almost empty FIFO 93

Figure 5.11: Full compilation was successful report 93

Figure 5.12: Linux System login 94

Figure 5.13: Load FPGA and show status 94

Figure 5.14: Data receive after sending messages 95

Figure 5.15: Show data in buffer 95

Figure 5.16: Clear data in buffer 96

Figure 5.17: The connection was tested 96

Figure 5.18: The disconnection was tested 96

Figure 5.19: System connection test with telnet 97

Figure 5.20: Wireshark Preferences 98

Figure 5.21: Wireshark Options 98

Figure 5.22: Command window 99

Figure 5.23: The sent packet and the received packet 99

List of Tables

Table 2.1: Stratix II FPGA EP2S180 features 18

Table 3.1: Ethernet Communication Standards 37

Table 3.2: Common Fiber Optic Attachment options for standard 802.3z 38

Table 3.3: Diagram of Host Board Connector Block Pin Numbers and Names 43

Table 4.1: 3-bit to 4-bit Encoding Values 69

Table 4.2: 5-bit to 6-bit Encoding Values 69

Table 4.3: 8B/10B encoding/decoding mapping table 70

AES Advanced Encryption Standard

APON ATM Passive Optical Network

ALM Adaptive Logic Module

ALU Arithmetic Logic Unit

ASIC Application Specific Integrated Circuit

BPON Broadband Passive Optical Network

CDR Clock Data Recovery

CMOS Complementary Metal-Oxide-Semiconductor

CPLD Complex Programmable Logic Device

DSL Digital Subcriber Line

DTE Data Terminal Equipment

EPON Ethernet based Passive Optical Network

FIR Finite Impulse Response

FPGA Field Programmable Gate Array

FTTH Fiber To The Home

GMII Gigabit Media Independent Interface

G-PON Gigabits Passive Optical Network

I/O Input/Output

IC Integrated Circuit

IEEE Institute Of Electrical And Electronics Engineers

ISI Intersymbol Interference

ITU-T International Telecommunication Union - Telecommunication

LD Laser Diode

LED Light Emitting Diode

LLC Logical Link Control

MBd Megabaud

MMF Multi-Mode Fibers

OSI Open Systems Interconnection

PAL Programmable Array Logic

PCS Physical Coding Sublayer

PHY Gigabit Physical Layer

PIN Positive-Intrinsic-Negative

PLLs Phase-Locked Loops

PMA Physical Medium Attachment

PMD Physical Medium Dependent

PON Passive Optical Network

RS Reconciliation Sublayer

SDRAM Synchronous Dynamic Random Access Memory SERDES Serialize/Deserialize (Serdes)

SFP Small Form Factor Pluggable

SMF Multi-Mode Fibers

STM Synchronous Transport Module

CHAPTER 1: INTRODUCTION

his chapter introduces the motivation and objectives of this thesis about the optical transport implementation based on Field Programmable Gate Array Description on the available hardware for implementation is presented The problem statement of the project will also be carried out in this thesis The outline

of the thesis is provided

1.1 Introduction

Recently, there has been a great demand of the high-speed data transmission due to the emerging applications in digital communications such as high quality audio, video transmission [5], [12] The development of technology which can support the high data rate transmission of various applications is of considerable interest Among the advanced transmission technologies, the optical fiber systems are the suitable choice due to their potential advantages The optical transport networks enable to transmit more information than conventional cable networks In addition, the advances of signal processing techniques allow to implement the hardware for the high-speed data transmission efficiently

There are several methods to implement the system One of the methods to implement the system is using FPGAs (Field Programmable Gate Arrays) FPGAs are the fastest, smallest, and shortest way to implement into hardware This method

is flexibility of design process and the shorter time to market for the chip design [4], [18]

The disadvantages of using this hardware are it needs memory and other peripheral chips to support the operation Besides that, it uses the most power usage and memory space, and would be the slowest in terms of time to produce the output compared to other hardwares

T

FPGA is an example of VLSI circuit which consists of a “sea of NAND gates” whereby the function are customer provided in a “wire list” This hardware is programmable and the designer has full control over the actual design implementation without the need and delay for any physical IC fabrication facility

An FPGA combines the speed, power, and density attributes of an ASIC with the programmability of a general purpose processor will give advantages to the optical transport system

An FPGA could be reprogrammed for new functions by a base station to meet future needs particularly when new design is going to fabricate into chip This will

be the best choice for optical transport implementation since it gives flexibility to the program design besides the low cost hardware component compared to others

As the performance of optical networks increases, optical network interface will have a significant impact on a system performance Interfaces are optimized for sending and receiving large packets Recent studies have shown that the controller

in the optical network interface must be able to buffer larger number of incoming smaller packets If the controller does not provide adequate resources, the result will

be lost packets and reduced performance The other reason for this problem is that current devices do not provide enough processing power to implement basic packet processing tasks efficiently as the frame rate increases for small packet traffic New network services like FTTH (Fiber to the home) may be significantly more complex than existing services [12] To address these issues, an intelligent, configurable network interface is an effective solution A reconfigurable optical network gigabit Ethernet interface allows rapid prototyping of new system architectures for network interfaces An FPGA with an embedded processor is a natural fit with this requirement

1.2 Project objectives

The objective of this thesis is the design and implementation of the hardware platform for the FPGA-based optical network transport with the Gigabit Ethernet interface This system is designed as an open research platform, with a range of configuration options and possibilities for extension in both software and hardware dimensions

The aim for this project is to design an optical transport network, mapping 8bits–10 bits encoder/decoder to serial to parallel and parallel to serial converter and FIFO buffers to MAC core, using Verilog HDL These designs were developed using Verilog HDL programming language in the design entry software The design

is then implemented in the Stratix II EP2S180F1020C5 FPGA chip, and AT FPGA version 1.0 development board

Several tools involved in the process of completing the design in real hardware which can be divided into two categories, software tools and hardware tools The softwares which include in this project are using CAD tools software, Verilog HDL module generator Altera Quartus II 8.0 and Modelsim, while the hardware use is Altera Stratix II board of ATVN FPGA version 1.0

1.3 Project scope

The work of the project will be focused on the design of the processing block One example is 8 bits-10 bits encoder decoder and FIFO buffers This project will concentrate on using the Gigabit Ethernet MAC Controller that supports data transfer speeds 1Gbps in the fiber optical transport networks and implement it on FPGA The Gigabit Ethernet MAC controller is an open core which was designed

by using Verilog HDL code

To ensure that the program can be implemented, the number of gates used in the design must be small or at least less than the hardware can support All design

need to be verified to ensure that no error in Verilog HDL programming before being downloading to hardware

The second scope is to implement the design into FPGA hardware development board This process is implemented if all designs are correctly verified and simulated using particular software Implementation includes hardware programming on FPGA or downloading hardware design into FPGA and software programming

Besides that, the design does not include Power-PC processor and control signal which control the data processing in SERDES module The control signal is use to select the process executed for each computation process during Verilog HDL design As a result, the design is applicable for hardware implementation in the FPGA development board

Finally, System testing performed also include in the scope of the project Testing is intended as the input interface for user as well as to control data processing performed by the hardware Appropriate software is used to compare the computation performed by the FPGA hardware with the software These computation values should be verified and tested to ensure the correctness of the developed module Testing required in understanding the operation of the networking process

1.4 Thesis outline

The thesis is organized into six chapters, namely introduction, FPGA and HDL chip design, principles and applications of optical communications, design and implementation, results and analysis, conclusion and future works

 Chapter 1 discusses the general idea of the project which covers the introduction, project objective, and scope of the project

 Chapter 2 presents the background information for this research and related literature review shows The overview of the FPGA architecture, and FPGA devices, basic concepts about design and hardware description language

 Chapter 3 describes the principles and applications of optical communications, optical fiber communication technology, system overview, trends and advances, fiber-optic transmission-systems design, device requirements and standard

 Chapter 4 explains regarding the hardware design and software design process involved in the project This part basically discussed on the works involved to download the modules into FPGA board

 Chapter 5 Analysis for individual components is provided and shows the results obtained from the FPGA hardware The results obtained are captured and shown in the figures Testing for system level will be carried out in this chapter

 Chapter 6 Conclusions are drawn and future work is suggested in

CHAPTER 2: FPGA AND HDL CHIP DESIGN

he development of types of sophisticated field-programmable devices has made the designing digital hardware industry change dramatically over the past few years This chapter introduces the overview of field-programmable devices I will present the relevant terminology and introduce the architectures of the most important commercially available chips Then, I will provide a brief introduction about the hardware description languages

2.1 Introduction

Field Programmable Gate Arrays (FPGAs) have played an important role in the development of the electronics industry FPGAs can be applied in different aspects of computing problems thanks to rapidly improving semiconductor manufacturing technology which is ranged from sub-micron to deep sub-micron processes and equally innovative CAD tools Thus, FPGAs provide the facility to implement systems with a set of primitive computational elements interconnected through flexible interconnects As compared to build a device with exact computational units and hardwired dataflow to solve a single problem, to build a FPGA solution offers more advantages of supporting a wide range of tasks [18]

Field Programmable Gate Arrays are called this because rather than having a structure similar to a PAL (Programmable Array Logic) or other programmable device, they are structured very much like a gate array ASIC (Application Specific Integrated Circuit) This makes FPGAs very nice for use in prototyping ASICs, or

in places where and ASIC will eventually be used For example, an FPGA may be used in a design that needs to get to market quickly regardless of cost Later an ASIC can be used in place of the FPGA when the production volume increases, in order to reduce cost [4], [17]

T

2.2 FPGA architecture overview

Each FPGA vendor has its own FPGA architecture, but in general terms they are all a variation of that shown in Figure 2.1 The architecture consists of configurable logic blocks, configurable I/O blocks, and programmable interconnect Also, there will be clock circuitry for driving the clock signals to each logic block, and additional logic resources such as ALUs, memory, and decoders may be available The two basic types of programmable elements for an FPGA are Static RAM and anti-fuses

The FPGA architecture is composed of basic functional blocks, which are connected together by a structure of programmable interconnections and have I/O capabilities to distribute signal [4], [17]

Figure 2.1: Structure of an FPGA

There are two basic categories of FPGAs on the market today: SRAM-based FPGAs and anti-fuse based FPGAs In the first category, Xilinx and Altera are the leading manufacturers in terms of number of users, with the major competitor being AT&T For antifuse-based products, Actel, Quicklogic and Cypress, and Xilinx offer competing products

An example of usage of SRAM-controlled switches is illustrated in Figure 2.2, showing two applications of SRAM cells: to control the gate nodes of pass-transistor switches and to control the select lines of multiplexers that drive logic block inputs The figure gives an example of the connection of one logic block (represented by the AND-gate in the upper left corner) to another through two pass-transistor switches, and then a multiplexer, all controlled by SRAM cells Whether

an FPGA uses pass-transistors or multiplexers or both depends on the particular product

Figure 2.2: SRAM-controlled Programmable Switches

The other type of programmable switch used in FPGAs is the antifuse Antifuses are originally open-circuits and take on low resistance only when programmed Antifuses are suitable for FPGAs because they can be built using modified CMOS technology As an example, Actel’s antifuse structure, known as PLICE is depicted in Figure 2.3 The figure shows that an antifuse is positioned between two interconnect wires and physically consists of three sandwiched layers: the top and bottom layers are conductors, and the middle layer is an insulator When unprogrammed, the insulator isolates the top and bottom layers, but when programmed the insulator changes to become a low-resistance link PLICE uses Poly-Si and n+ diffusion as conductors

Figure 2.3 : Actel Antifuse Structure

2.3 Stratix II FPGA

The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs) Stratix II devices offer up to 9 Mbits of on-chip, TriMatrix™ memory for demanding, memory intensive applications and have up to 96 DSP blocks with up

to 384 (18-bit × 18-bit) multipliers for efficient implementation of high performance filters and other DSP functions Various high-speed external memory interfaces are supported, including double data rate (DDR) SDRAM and DDR2 SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data rate (SDR) SDRAM Stratix II devices support various I/O standards along with support for 1-gigabit per second (Gbps) source synchronous signaling Stratix II devices offer a

complete clock management solution with internal clock frequency of up to 550

MHz and up to 12 phase-locked loops (PLLs) Stratix II devices which have a top

view in Figure 2.4 are also the industry’s first FPGAs with the ability to decrypt a

configuration bitstream using the Advanced Encryption Standard (AES) algorithm

to protect designs

Figure 2.4: Top view Stratix II

Table 2.1: Stratix II FPGA EP2S180 features

1.2-V internal, 3.3-V I/O

Figure 2.5: Stratix II Block Diagram

The Stratix II EP2S180 features are listed in Table 2.1 More specially, the Stratix II family offers the following features:

- 15,600 to 179,400 equivalent LEs

- New and innovative adaptive logic module (ALM), the basic building block

of the Stratix II architecture, maximizes performance and resource usage efficiency

- Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources

- TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers

- High-speed DSP blocks provide dedicated implementation of multipliers (at

up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters

- Up to 16 global clocks with 24 clocking resources per device region

- Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode

- Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting

Figure 2.6: 1,020-PIN FPGA Package Outline

2.4 Hardware description language

2.4.1 Introduction

In electronics, a hardware description language (HDL) is referred to as a class of computer languages which can be used to describe of electronic circuits It can support to describe circuit's operation, its design, and tests to verify its operation by simulations To design integrated circuits, one can use the Verilog HDL or VHDL which is one of the two most common Hardware Description Languages (HDL) In the design cycle, with the help of HDL the design can be simulated to investigate and correct errors or to check the experimental architectures The most advantages of using HDL are that designs are usually more readable and they are technology-independent, easy to check performance results [11]

Verilog can be used to describe designs at four levels of abstraction:

- Algorithmic level (much like C code with if, case and loop statements)

- Register transfer level (RTL uses registers connected by Boolean equations)

- Gate level (interconnected AND, NOR etc.)

- Switch level (the switches are MOS transistors inside gates)

Figure 2.7: Verilog

2.4.2 Verilog HDL Structure

In Verilog, circuit components are designed inside a module [11] Modules can contain both structural and behavioral statements Structural statements represent circuit components like logic gates, counters, and microprocessors Behavioral level statements are programming statements that have no direct mapping to circuit components like loops, if-then statements, and stimulus vectors which are used to exercise a circuit A design is described in Verilog using the concept of a module A module starts with the keyword module followed by an optional module name and an optional port list The key word endmodule ends a module A module can be conceptualised as consisting of two parts, the port

declarations and the module body The port declarations represent the external

interface to the module The module body represents the internal description of the module - its behaviour, its structure, or a mixture of both

Example

`timescale 1ns / 1ps module some_logic_component (c, a, b);

// declare port signals

// declare internal wire

//instantiate structural logic gates

endmodule

The language also defines constructs that can be used to control the input and output

of simulation More recently Verilog is used as an input for synthesis programswhich will generate a gate-level description (a netlist) for the circuit Some Verilog constructs are not synthesizable

Comments can be specified in two ways:

(//) All text between these characters and the end of the line will be ignored

by the Verilog compiler

/* and */ Using comments on more than one line

Data Types

Value Set Verilog consists of only four basic values

0 (logic zero, or false condition)

1 (logic one, or true condition)

x (unknown logic value)

Wire A wire represents a physical wire in a circuit and is used to connect gates or

modules The value of a wire can be read, but not assigned to, in a function or block A wire does not store its value but must be driven by a continuous assignment statement or by connecting it to the output of a gate or module

wire [9:0] A; // a cable (vector) of 10 wires

Reg A reg (register) is a data object that holds its value from one procedural

assignment to the next It is used only in functions and procedural blocks

Syntax reg [msb:lsb] reg_variable_list;

Example

reg a; // single 1-bit register variable reg [7:0] tom; // an 8-bit vector; a bank of 8 registers

Input, Output, Inout: These keywords declare input, output and bidirectional ports

of a module or task Input and inout ports are of type wire An output port can be configured to be of type wire, reg, wand, wor or tri The default is wire

module sample(b, e, c, a);

input a; // An input which defaults to wire

output b, e; // Two outputs which default to wire output [1:0] c; /* A two-it output One must declare its type in

a separate statement */

reg [1:0] c; // The above c port is declared as reg

Parameter: A parameter defines a constant that can be set when you instantiate a

module This allows customization of a module during instantiation

(cond) ? (result if cond true):

(result if cond false)

Continuous Assignment is used to assign a value onto a wire in a module It is the

normal assignment outside of always or initial blocks

Syntax

wire wire_variable = value;

assign wire_variable = expression;

Blocking Assignments

Procedural (blocking) assignments (=) are done sequentially in the order the statements are written A second assignment is not started until the preceding one is complete

Example For simulation

initial

begin

a=1; b=2; c=3;

#5 a = b + c; // wait for 5 units, and execute a= b + c =5

d = a; // Time continues from last line, d=5 = b+c at t=5

end Nonblocking (RTL) Assignments RTL (nonblocking) assignments (<=), which

follow each other in the code, are done in parallel The right hand side of

blocking assignment or if none, the start of the procedure The transfer to the left hand side is made according to the delays A delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking

#3 b <= a; // grab a at t=0 Deliver b at t=3

#6 x <= b + c; // grab b+c at t=0, wait and assign x at t=6

// x is unaffected by b’s change

begin end: are used to group several statements for use where one statement is

syntactically allowed Such places include functions, always and initial blocks, if, case and for statements Blocks can optionally be named and can include register, integer and parameter declarations

if else if else: The if else if else statements execute a statement or block of

statements depending on the result of the expression following the if If the conditional expressions in all the if’s evaluate to false, then the statements in the else block, if present, are executed There can be as many else if statements as required, but only one if block and one else block If there is one statement in a block, then the begin end statements may be omitted

Syntax

if (expression) begin

statements

end else if (expression) begin

statements

end

more else if blocks

else begin

statements

end end

case

The case statement allows a multipath branch based on comparing the expression with a list of case choices Statements in the default block execute when none of the case choice comparisons are true (similar to the else block in the if else if else)

If no comparisons, including delault, are true, synthesizers will generate unwanted latches

Event Control, @

This causes a statement or begin-end block to be executed only after specified

events occur An event is a change in a variable and the change may be: a positive edge, a negative edge, or either (a level change), and is specified by the keyword

posedge, negedge, or no keyword respectively Several events can be combined

with the or keyword Event specification begins with the character @and is usually

used in always statements

Syntax

@ (posedge variable or negedge variable) statement;

@ (variable or variable ) statement;

always

@ (posedge clk or negedge rst)

if (rst) Q=0; else Q=D; // Definition for a D flip-flop

@(a or b or e); // re-evaluate if a or b or e changes

sum = a + b + e; // Will synthesize to a combinational adder

Always Block The always block is the primary construct in RTL modeling Like

the continuous assignment, it is a concurrent statement that is continuously executed during simulation This also means that all always blocks in a module execute simultaneously

Syntax 1 always @(event_1 or event_2 or )

begin

statements

end Syntax 2 always @(event_1 or event_2 or )

begin: name_for_block

statements

end

Example always @(a or b) // level-triggered; if a or b changes levels

always @(posedge clk); // edge-triggered: on +ve edge of clk Initial Block is like the always block except that it is executed only once at the

beginning of the simulation It is typically used to initialize variables and specifies signal waveforms during simulation Initial blocks are not supported for synthesis

This parallel data is latched into the input register of the transmitter section on the rising edge of the reference clock (used as the transmit byte clock) A 1062.5 MHz reference clock is used in Fibre Channel operation, whereas a 125 MHz reference clock is used in Gigabit Ethernet operation

The transmitter section’s PLL locks to the user supplied reference byte clock This clock is then multiplied by 10 to generate the high speed serial clock used to generate the high speed output The high speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission

The receiver section accepts a serial electrical data stream at 1062.5 MBd or

1250 MBd and recovers the original 10-bit wide parallel data The receiver PLL locks onto the incoming serial signal and recovers the high speed serial clock and data The serial data is converted back into 10-bit parallel data, recognizing the 8B/10B comma character to establish byte alignment

CHAPTER 4: FPGA-BASED DESIGN AND

IMPLEMENTATION

his chapter presents the important steps in the design of the device based

on the hardware description language and FPGA The function block diagrams of the Gigabit Ethernet are introduced

4.1 Overview of the design

This section examines the design flow for any device, whether it is an ASIC,

an FPGA, or a CPLD This is the entire process for designing a device that guarantees the design engineers will not overlook any steps and that the design engineers will have the best chance of getting back a working prototype that functions correctly in the system The design flow consists of the steps in Figure

T

Figure 4.1: Design flow using Quartus II

Figure 4.2: Design flow Design Entry

The design engineers must decide at this point which design entry method they prefer For smaller chips, schematic entry is often the method of choice, especially

Simulation Design Entry

Contraints

if the design engineer is already familiar with the tools For larger designs, however,

a hardware description language (HDL) such as Verilog or VHDL is used because

of its portability, flexibility, and readability When using a high level language, synthesis software will be required to “synthesize” the design This means that the software creates low level gates from the high level description

Simulating - design review

Simulation is an ongoing process while the design is being done Small sections of the design should be simulated separately before hooking them up to larger sections There will be many interations of design and simulation in order to get the correct functionality Once design and simulation are finished, another design review must take place so that the design can be checked

Synthesize

The design engineers must decide at this point which synthesis software they will be using if they plan to design the FPGA with an HDL If the design was entered using an HDL, the next step is to synthesize the chip This involves using synthesis softwares to optimally translate your register transfer level (RTL) design into a gate level design which can be mapped to logic blocks in the FPGA This may involve specifying switches and optimization criteria in the HDL code, or playing with parameters of the synthesis software in order to insure good timing and utilization

Place and Route

The next step is to lay out the chip, resulting in a real layout for a real chip This involves using the vendor’s software tools to optimize the programming of the chip to implement the design Then the design is programmed into the chip

Resimulating - final review

After layout, the chip must be resimulated with the new timing numbers produced by the actual layout If everything has gone well up to this point, the new

possible paths to go in the design flow If the problems encountered here are significant, sections of the FPGA may need to be redesigned If there are simply some marginal timing paths or the design is slightly larger than the FPGA, it may be necessary to perform another synthesis with better constraints or simply another place and route with better constraints At this point, a final review is necessary to confirm that nothing has been overlooked

Testing

For a programmable device, the design engineers simply program the device and immediately have their prototypes The design engineers then have the responsibility to place these prototypes in the system and determine that the entire system actually works correctly If the design engineers have followed the procedure up to this point, chances are very good that their system will perform correctly with only minor problems These problems can often be worked around by modifying the system or changing the system software These problems need to be tested and documented so that they can be fixed on the next revision of the chip System integration and system testing is necessary at this point to insure that all parts of the system work correctly together

When the chips are put into production, it is necessary to have some sort of burn-in test of the system that continually tests the system over some long amount

of time If a chip has been designed correctly, it will only fail because of electrical

or mechanical problems that will usually show up with this kind of stress testing

Figure 4.3: Full IC Design Flow

4.2 Software design

The software design of the system mainly includes two parts: the test system application software, and the FPGA software The application software mainly finishes sending disposing and controlling information; The FPGA software is principal part of the system software, and responsible for finishing the realization of all test functions Software in FPGA is the key to achieve the ideal function It is the most difficult to design This part is achieved in Altera’s Quartus II software development environment

Figure 4.4: Quartus II Software Basic Design Flow

The Quartus II software provides a wizard to help you create new projects The New Project Wizard generates the qpf file and qsf file for your project The Quartus II software supports the following design entry methods:

Top-level design files can

be schematic, HDL or 3 rd Party Netlist File

.edf edif

.v vhd

.tdf bsf

.bdf

.gdf

Level File

Top-the FPGA is shown in Figure 4.5 There are two separate custom boards, named main-board and daughter-board The reason for having two separate boards is to provide more flexibility in the board layout implementation The Stratix-II FPGA is the focal point in the board design and is used to implement a programmable network processor, a Gigabit Ethernet MAC controller, memory controllers, 8B/10B encoding with a symbol data rate of 1.25 Gbit/s and FIFOs buffers

The SRAM with a speed grade of 133 MHz has access latency of 5 cycles and has a 32-bit data bus width interface with Stratix II FPGA, which provides low latency access for the processor The SDRAM, 128 Mbytes is integrated as a large capacity, high bandwidth memory to store data and is used for adding future services like network interface data caching

The Gigabit Ethernet transceiver PHY chip, coverts the input signals into a SERDES and 8B10B coded signal with 1.25 Gbit/s Gigabit Ethernet transceiver implements the physical layer defined in the Open System Interconnect reference module and is responsible for processing signals received from the MAC (which is implemented in the Stratix-II) to the medium, and for processing signals received from the medium for sending to the MAC It requires a 3.3V, 1.5A power supply to all VCC balls for operation A 125 MHz oscillator is required for the reference clock The maximum power consumption of the PHY is 6Watts

Figure 4.5: Stratix II block diagram

Clock Distribution Management: Various interfaces with different speed clock domains are implemented in the board These clock domains are shown

high-in Figure 4.5 The Gigabit Ethernet PHY requires 125 MHz as the reference clock SDRAM and SRAM require a programmable clock ranging from 50 MHz to 133 MHz Excessive use of multiple oscillators or clock multiplier ICs to generate the required clock for each interface is not recommended, since it adds more hardware and noise to the board In addition, special consideration must be given to clock distribution to prevent the clock skew in the systems Clock skew and clock delay can have a substantial impact on designs running at higher than 100 MHz Thus to address these issues, a proper clocking management is required to generate a zero-delay and de-skewed clock for designs in the both FPGAs and the on-board component

The biggest challenge in designing a functional Gigabit Ethernet network interface controller in the FPGA is to meet the performance objective for each interface in the FPGA There are multiple fast clock domains in the FPGA for this design, including PowerPC processor interface operating at 100MHz, Gigabit Ethernet interface operating at 125MHz, SDRAM and SRAM memory interfaces operating at frequencies of 100 or 125 MHz

Figure 4.6: Top-level block diagram of the system

Flash SDRAM

CPU

POWER SUPPLY

FPGA- Stratix II-EP2S180

GMII

Tx MAC

8B/10B

8B/10B

Rx MAC

Rx FIFO

Power-PC

Figure 4.7: FPGA Stratix II POWER-PC

The PowerPC is a hard core processor built into the AT FPGA board Within the FPGA there are two buses for interfacing the PowerPC to the peripherals: the Processor Local Bus (PLB) and the On-chip Peripheral Bus (OPB) The PLB is a high-performance bus that directly connects the PowerPC to memory and high-performance peripherals The OPB is used to connect slower peripherals The PLB and OPB connect through a bridge

The top-level block diagram shows the board has one hardcore of PowerPC processor The PowerPC processor is a 32-bit implementation of the AMD processor Each processor runs at 300 MHz and, a high-bandwidth bus provides separate 32-bit address and 64-bit data buses for the instruction and runs at 100 to

133 MHz The CoreConnect architecture is implemented as a soft IP The PowerPC core accesses high speed and high performance system resources through the local bus

An open-source Linux 2.4.2 kernel was supported to run on the PowerPC system The soft Linux TCP/IP stack (including UDP transfers) drives the Ethernet communications with the PC farm Some device drivers including the Gigabit Ethernet, and memory technology devices have already been included in the kernel’s package as options Others like the feature extraction processors are to be customized for accessing them in the Linux operating system Ethernet data transferring and slow control tasks are implemented as application programs which might be written in C/C++ or high level scripts