Simulation, modelling and fabrication of novel devices with steep subthreshold slope

vii 5.4 The Silicon I-FinFET Technology 77 5.4.2 Breakdown Characteristics 81 5.4.3 Gate Transfer Characteristics 83 5.5 In situ Doping and Strain Engineering Technology 85 5.5.2 Device

SIMULATION AND FABRICATION OF NOVEL DEVICES

WITH STEEP SUBTHRESHOLD SLOPE

TOH ENG HUAT

(B.Eng (Hons.), NUS)

A THESIS SUBMITTED FOR THE DEGREE OF Ph.D (ENGINEERING) DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE

2008

i

ABSTRACT

CMOS device scaling faces several fundamental limits as it scaled beyond the sub-30

nm regime Non-scalability of the subthreshsold swing and adverse short channel effects like drain-induced barrier lowering, and band-to-band tunneling have led to high off-state leakage current Thus, the impact-ionization MOS (I-MOS) transistor and tunneling field-effect transistor (TFET) have been explored as an alternative switching device for sub-60 mV/decade subthreshold swing Both are essentially gated p-i-n diode The former employs an impact-ionization region (I-region) for avalanche of carriers to occur, while the latter creates a region near the source-channel junction for band-to-band tunneling of carriers to occur This work is devoted to addressing the issue of the non-scalability of the subthreshold swing, and evaluating and advancing the I-MOS and TFET technologies

For the I-MOS technology, process and device design innovations like the spacer I-MOS were applied to achieve excellent device performance with good short channel effects The employment of SiGe in SiGe complementary I-MOS (C-I-MOS) further reduces the power supply voltage requirement, while boosting the device performance in terms of off-state and on-state current For compactness and better scalability, an I-MOS transistor with an elevated I-region or the L-shaped I-MOS transistor had been proposed as a promising candidate among various I-MOS structures for enhanced performance through strain and materials engineering The elevated I- region allows for the incorporation of novel materials for introduction of strain and

double-ii

reduction inthe bandgap to increase impact-ionization activity Both I-MOS with an elevated Si1-yCy RSD and I-MOS with an elevated Si1-xGex RSD had been realized and proved to be viable not only in reducing the breakdown voltage, but also to enhance the performance further An impact-ionization nanowire multiple-gate field-effect transistor (I-FinFET) was also proposed and fabricated, leading to a significant reduction in the

source bias needed to sustain impact-ionization In situ doping, strain and material

engineering technology were employed for enhanced device performance In addition, a simulation study on the Ge LI-MOS technology revealed promising potential

The TFET technology had been studied by extensive device simulation A gate Si TFET with SiGe source was proposed and explored Less than 60 mV/decade subthreshold swing with extremely low off-state leakage current is achieved by optimizing the device parameters and Ge content in the source Power supply voltage scaling is projected to be possible with the introduction of much narrower bandgap material like Ge or InAs Thus, low supply voltage coupled with bandgap engineering helps to pave the way for transistor downscaling while maintaining low power consumption

double-In summary, novel devices with steep subthreshold slope were proposed and studied They reveal promising potential for augmenting the performance of conventional CMOS transistors

iii

ACKNOWNLEDGEMENTS

I would like to express my sincere gratitude to my advisor, Dr Yeo Yee-Chia for his generous help throughout my four years of post graduate study at National University of Singapore (NUS) Dr Yeo Yee-Chia is an admirable academic professional and a great role model He taught me not only his precious knowledge, but also his exceptional professionalism I typically enjoyed those inspiring discussions we had I especially thank him for his prompt reading and careful critique of my thesis Throughout my life, I will benefit from the experience and knowledge I gained working with Dr Yeo Yee-Chia

I am also indebted to my co-advisor, Prof Ganesh Samudra for his valuable guidance and insightful suggestions to my research work Since my undergraduate study, he had been providing me with lots of guidance in research for the past five years He impressed

me very much by his responsibility and strict attitude in training students to be independent He always provided timely and warm encouragement and support in difficult times As a respected elder, he introduced me to the various opportunities in research

I am also grateful to my mentor, Dr Lap Chan from Chartered Semiconductor Manufacturing Ltd (CHRT) who had been very supportive of my work His willingness

to share both his work and life experience really widened my perspectives I would also like to thank Dr Francis Benistant (CHRT) for his guidance in carrying out TCAD simulation A lot of precious knowledge was learned from him

iv

Special thanks to Dr Patrick Lo for facilitating my fabrication work at the Institute of Microelectronics (IME) I also thank the research staffs and engineer assistants at IME for their support

I would also like to take this opportunity to thank my working partner, Miss Grace Wang Huiqi, who introduced me to semiconductor processing equipments and shared her expertise in materials analysis; my colleagues at the Silicon Nano Device Laboratory (SNDL), Dr Zhu Ming, Mr Shen Chen, Mr Ang Kah Wee, Mr Chui King Jien, Mr Tan Kian Meng, Mr Jason Liow, Mr Rinus Lee, and Mr Andy Lim for their help and discussions; and the Special Project Group students (CHRT) for providing a wonderful research atmosphere to work in

Finally, I owe more than words can describe to my family and friends This work is dedicated to them

3.4.2 SiGe-on-Insulator (SGOI) Substrate Formation 39 3.4.3 Device Structure and Fabrication 42 3.4.4 Impact of Impact-ionization Threshold Energy Engineering 44 3.4.5 Device Performance of SiGe I-MOS Transistor 47 3.4.6 Summary of SiGe I-MOS Transistor 48

CHAPTER 4

THE L-SHAPED IMPACT-IONIZATION MOS (LI-MOS) TRANSISTOR 53

4.3 LI-MOS Device Structure and Design 55 4.4 CMOS-Compatible Process Flow of LI-MOS 59 4.5 Strain Engineering of LI-MOS 61 4.6 Material Engineering of LI-MOS 68

CHAPTER 5

5.2 New Device Structure: From LI-MOS to I-FinFET 75

vii

5.4 The Silicon I-FinFET Technology 77

5.4.2 Breakdown Characteristics 81 5.4.3 Gate Transfer Characteristics 83 5.5 In situ Doping and Strain Engineering Technology 85

5.5.2 Device Physics and Structures 86 5.5.3 Process Flow of I-FinFETs with In Situ Doping and Strain Technology 87 5.5.4 Device Performance of I-FinFETs with in situ doping and strain 89 5.5.5 Summary of I-FinFETs with in situ doped Source 93 5.6 Impact-ionization Threshold Energy Engineering Technology 93

ix

CHAPTER 10

10.2 Future Work for I-MOS Transistor 168

x

LISTS OF FIGURES

Chapter 1

Figure 1.1 Gate transfer characteristics of (a) original device (black line) with fixed

subthreshold swing S showing decreasing on-state current I on due to a reduction of

power supply voltage V DD, and (b) original device (black line) and scaled device

(blue line) with fixed S showing increasing off-state leakage current I on when

threshold voltage V T is reduced .2 Figure 1.2 Schematic of (a) a conventional CMOS transistor, and (b) its on-state energy band

diagram extracted from the source to drain direction Electrons in the source are injected into the channel by the lowering of the barrier through the control of the gate influence .4 Figure 1.3 Schematic of an n-channel impact-ionization MOS (I-MOS) transistor The I-MOS

transistor has an asymmetric structure with an additional region for ionization to occur This region is known as the impact-ionization region or I-region For an n-channel I-MOS, the drain is doped n+ while the source is doped p+ 5 Figure 1.4 (a) Energy band digram of the n-channel I-MOS transistor operating in the on-state

impact-(b) Simulated gate transfer characteristics for conventional MOSFET and I-MOS

Excellent subthreshold swing of sub-5 mV/decade is achieved with high I on /I off ratio for the I-MOS transistor, whereas the subthreshold swing of the conventional MOSFET is greater than 60 mV/decade .6 Figure 1.5 (a) Schematic showing the structure of an n-channel Si TFET with a p+ source and

n+ drain Tunneling occurs at the source-channel junction The energy band diagram

of the TFET operating in the on-state is shown in (b) Electrons tunnel from the

source to the channel when the tunneling barrier width ω T is adequately small at a specific gate bias .7 Figure 1.6 Simulated gate transfer characteristics for conventional MOSFET and TFET

Excellent subthreshold swing of sub-25 mV/decade is achieved with high I on /I off ratio

for TFET The extremely low I off of TFET make such a device attractive for low power applications 8

xi

Chapter 2

Figure 2.1 Schematic showing the interaction of a carrier (electron) and an atom to produce

additional electron-hole pair 13 Figure 2.2 Schematic showing the avalanche multiplication events being initiated by an

injecting electron from the left into the sample The hole created moves to the left, and the electron moves to the right 17 Figure 2.3 Schematic illustrating the various components of electron and hole current densities

caused by impact-ionization .18 Figure 2.4 Energy band diagram of p-i-n diode showing the phenomenon of band-to-band

tunneling, whereby a valence band electron tunnel through the forbidden energy gap

to the conduction band .20 Figure 2.5 A two band structure of (a) direct bandgap material (GaAs, InSb), and (b) in-direct

bandgap material (Si, Ge) for a p-i-n diode, illustrating direct tunneling and phono assisted tunneling, respectively .21

Figure 2.6 Band-to-band tunneling rate G BTBT as a function of electric field for different type of

materials Higher G BTBT is observed for material with smaller bandgap and smaller relative effective masses 24

Chapter 3

Figure 3.1 Schematic showing the structure of (a) an n-channel Si I-MOS with a p+ source and

n+ drain, and (b) a p-channel Si I-MOS with a n+ source and p+ drain 27 Figure 3.2 Energy Band Diagram of an n-channel I-MOS along the source to the I-region to the

drain for device operating in the (a) Off-state, and (b) On-state The n+ drain is grounded while p+ source is at a negative bias 27 Figure 3.3 Schematic of (a) a basic lateral I-MOS or single-spacer (SS) I-MOS, and (b) a

double-spacer (DS) I-MOS Drain extension is lightly doped to reduce drain biasing effect on the breakdown voltage and threshold voltage The second spacer is formed

so that a shallow source implant could be employed to reduce the breakdown voltage .31

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Figure 3.4 Summary of important fabrication process steps for the formation of the DS I-MOS

transistor The first spacer is used to define the length of the I-region L I, and photoresist is used to block the drain/source region when implantation is carried out

on the source/drain region .32 Figure 3.5 (a) SEM view of fabricated I-MOS showing the source being covered by photoresist

during drain extension implantation (b) TEM picture of the DS I-MOS transistor showing the double-spacer Cleaning steps have caused part of the liner oxide to be washed away 32

Figure 3.6 Plot of measured I D -V S for DS I-MOS at various gate lengths Higher reverse-biased

leakage current and lower breakdown voltage are observed at shorter gate length .34

Figure 3.7 Plot of breakdown voltages V BD at various gate lengths L G for SS MOS and DS

I-MOS V BD decreases as L G decreases This is a direct result of the reduction of

channel resistance (inset) with decreasing L G Lower V BD is achieved with shallow source extension implant .34

Figure 3.8 Impact of drain bias on V BD Employing a lightly-doped drain reduces the influence

of drain bias, and hence reduced drain-induced breakdown voltage lowering (DIBVL) A DIBVL reduction of up to 0.17 V/V is achieved 36

Figure 3.9 Measured I D -V S for DS I-MOS (a) at different drain biases, and (b) at different gate

biases Increasing the drain bias reduces the breakdown voltage and increases the band-to-band tunneling current from channel to drain, while increasing the gate bias increases the voltage drop across the I-region, and hence lowers the breakdown voltage .36 Figure 3.10 Gate transfer characteristics for a 60 nm gate length DS I-MOS transistor at different

drain biases Excellent subthreshold swing of 5.88 mV/decade is achieved An

on-state current I on of 200 µA/µm at V G -V T = 1.0V is achieved with an off-state leakage

current of 7.3 nA/µm at V G -V T = -0.2 V .37 Figure 3.11 Schematic of Ge condensation process to fabricate SiGe-on-insulator (SGOI)

substrate for SiGe channel I-MOS device fabrication 40

Figure 3.12 Plot showing the required epi thickness T epi of Si0.75Ge0.15 needed to achieve a certain

Ge content of SGOI substrate with final thickness, T SGOI 41

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Figure 3.13 Schematic of (a) a Si MOS transistor, and (b) a SiGe MOS transistor The

I-region is located under the spacer next to the source For an n-channel device, the drain is doped n+ while the source is doped p+ For a p-channel device, the drain is doped p+ while the source is doped n+ 43 Figure 3.14 Summary of important fabrication process steps for the formation of the lateral I-

MOS transistor SOI, and SGOI substrates of different Ge content are used to

fabricate the devices The spacer is used to define the length of the I-region L I, and photoresist is used to block the drain/source region when implantation is carried out

on the source/drain region .43 Figure 3.15 (a) SEM view of the device after gate formation and rotated anti-clockwise by 45°

(left) Photoresist is used as a mask to block out the source from ion implants during the drain extension formation (right) The TEM picture of the fabricated SiGe I-MOS device is as shown in (b) The spacer liner oxide was partially removed during cleaning steps .44 Figure 3.16 Variation of impact-ionization threshold energies for electrons and holes as a

function of Ge content is shown [48] Increasing the Ge content favors ionization by decreasing the threshold energies for both electrons and holes This

impact-will lead to impact-ionization occurring at a lower breakdown voltages V BD 46 Figure 3.17 Measurement of breakdown voltages as a function of Ge content Impact-ionization

occurring at a lower breakdown voltages V BD (experimentally measured) for both n- and p-channel SiGe I-MOS devices .46

Figure 3.18 Plot of (a) drain current I D and (b) transconductance G m , as a function of gate

overdrive (V G –V T) for Si, Si0.75Ge0.25 and Si0.40Ge0.40 n-channel I-MOS devices All

devices have a L G of 50 nm and L I of 40 nm with an EOT of 30 Å Higher I D is achieved at higher Ge content due to lower threshold energies A four-fold enhancement in peak transconductance is achieved with Si0.40Ge0.40 n-channel I-MOS device 49

Figure 3.19 (a) Measured drain current I D as a function of gate overdrive (V G –V T) for Si,

Si0.75Ge0.25 and Si0.40Ge0.40 p-channel I-MOS devices I on is enhanced by 3.5 times at

40% Ge due to higher impact-ionization rates (b) Plot of transconductance G m as a

function of gate overdrive (V G –V T) for Si, Si0.75Ge0.25 and Si0.40Ge0.40 p-channel MOS devices An enhancement of 4 times in peak transconductance is achieved with

I-Si0.40Ge0.40 p-channel I-MOS device 49

xiv

Figure 3.20 (a) Off-state current I off measured at (V G –V T ) = -0.2 V plotted as a function of V T for

n-channel I-MOS devices revealing that for matched V T , the I off of Si I-MOS device

is much higher than that of SiGe I-MOS device (b) Measured I off - I on plot for the

n-channel devices I on is measured at (V G –V T ) = 1.0 V An I on enhancement of ~2-3 times is observed for Si060Ge0.40 devices at matched V T or the same I off 50

Figure 3.21 (a) Plot of off-state current I off measured at (V G –V T ) = 0.2 V as a function of V T for

p-channel I-MOS devices The I off of Si I-MOS device is much higher than that of

SiGe I-MOS device at the same V T (b) Plot of I off as a function of I on showing that at

matched V T or the same I off , significant I on enhancement measured at (V G –V T) = -1.0

V is achieved with Si0.60Ge0.40 I-MOS devices .50

Chapter 4

Figure 4.1 Schematics of various I-MOS transistor structures, compared against each other for

their merits and demerits The studied I-MOS structures are (a) the Lateral I-MOS [26], (b) the I-MOS with an elevated Drain [27], and (c) the L-shaped I-MOS [28] The impact-ionization region (I-region) is enclosed by the dotted box and the junctions are indicated by dashed lines .57

Figure 4.2 Schematic of an n-channel Impact-ionization MOS (I-MOS) Transistor with (a) an

Elevated Si Impact-ionization region (I-region), (b) an Elevated Si1-yCy I-region, and (c) an Elevated Si1-xGex I-region The L-shaped I-region (enclosed dotted box)

comprises a horizontal I-region under the spacer (L S ) and an elevated I-region (T I) in the raised source region 58 Figure 4.3 (a) Energy band diagram of the LI-MOS in the on-state The narrower bandgap in

the vertical I-region enhances impact-ionization (b) Simulation results showing the distribution of the band-to-band generation rate (cm-3 s-1) at the source-end of the LI-MOS transistor .58 Figure 4.4 Process sequence for the fabrication of LI-MOS transistors, showing compatibility

with a conventional CMOS process After gate stack and spacer formation, selective epitaxial growth (SEG) of raised S/D regions was performed This was followed by implantation to form the n+ drain and the p+ source, dopant activation, contact formation, and metallization 60

xv

Figure 4.5 Simulated (a) Bandgap E g , and (b) Changes in Breakdown voltage V BD as a function

of stress obtained using Synopsys TCAD tools Biaxial tensile stess and uniaxial compressive stress are effective in narrowing the bandgap of Si Inset of Fig 5(b) shows the stress resulting from growing Si0.99C0.01 on Si Depending on the device structure and processing conditions, the stresses of Si0.99C0.01 could vary from uniaxial tensile stress to biaxial tensile stress 63 Figure 4.6 (a) SEM picture of strained I-MOS showing the good surface morphology of SEG

Si0.99C0.01 (b) TEM picture of strained I-MOS with elevated Si0.99C0.01 S/D 63

Figure 4.7 Simulated contour plot of lateral stress S xx (in MPa) for strained I-MOS using

Synopsys-ISE TCAD tools The SEG of Si1-yCy on Si results in uniaxial tensile strain

to be induced in the lateral I-region The effect of strain has further implication on the changes in bandgap 65

Figure 4.8 Plot of measured I D -V S for control and strained I-MOS showing the breakdown

voltages V BD of their p-i-n diode structures Lower breakdown voltage is observed for strained I-MOS .65

Figure 4.9 Measured Breakdown voltage V BD changes as a function of gate length L G The

advantage of using strain to reduce the breakdown voltage is clearly shown As L G

decreases, the strain effect is more prominent, and thus the changes in V BD are larger 66 Figure 4.10 SIMS profile of Boron in the source region in control and strained I-MOS devices

The integration of Si0.99C0.01 contributes to a steeper Boron profile and hence a lower

V BD .66

Figure 4.11 (a) Plot of drain current I D as a function of gate overdrive (V G –V T) for I-MOS with

Si RSD, and Si0.99C0.01 RSD Both devices have a L G of 60 nm and L I of 60 nm with

an EOT of 30 Å The elevated I-region (T I) for both Si RSD and Si0.99C0.01 RSD is 30

nm Excellent subthreshold swing S of 4.46 mV/decade and 3.56 mV/decade is achieved, respectively (b) Plot of transconductance G m as a function of gate

overdrive (V G –V T) for I-MOS with Si RSD, and Si0.99C0.01 RSD A two-fold enhancement in on-state current and peak transconductance is achieved with

Si0.99C0.01 RSD .67

xvi

Figure 4.12 Simulated (a) Bandgap, and (b) Breakdown voltage changes as a function of Ge

content The unstrained bandgap of Si1-xGex is modeled using a piecewise linear approximation [42] Due to the lattice mismatch between Si and Si1-xGex, biaxial strain is present in the fully-strained Si1-xGex This results in more bandgap narrowing and thus greater reduction in breakdown voltage .70

Figure 4.13 Plot of measured breakdown voltage V BD as a function of gate length L G for control

and bandgap engineered I-MOS transistors, showing the advantage of using narrower bandgap material to reduce the breakdown voltage .70

Figure 4.14 (a) Plot of drain current I D as a function of gate overdrive (V G –V T) for I-MOS with

Si RSD, and Si0.75Ge0.25 RSD Both devices have a L G of 60 nm and L I of 60 nm with

and EOT of 30 Å The elevated I-region (T I) for both Si RSD and Si0.75Ge0.25 RSD is

30 nm Excellent subthreshold swing S of 4.46 mV/decade and 3.28 mV/decade is achieved, respectively (b) Plot of transconductance G m as a function of gate

overdrive (V G –V T) for I-MOS with Si RSD, and Si0.75Ge0.25 RSD A three-fold enhancement in peak transconductance is achieved with Si0.75Ge0.25 RSD .71 Figure 4.15 Summary plot of the important electrical parameters of the various types of LI-MOS

transistors Strain and material engineering enhances the performance of control MOS .72

LI-Chapter 5

Figure 5.1 (a) 3-Dimensional Schematic of the impact-ionization nanowire multiple-gates

FinFET or I-FinFET and SEM view (inset) The spacer next to the raised source defines the lateral I-region and the elevated structure beside the spacer defines the elevated I-region, raised source, and drain Thus, the L-shaped I-region comprises the lateral and elevated I-region (b) The cross-section schematics of Si I-FinFET are extracted along the line X-X’ of (a) Shown here are n-channel devices The dotted L-shaped box outlines the impact-ionization region (I-region) 78 Figure 5.2 This plot shows the simulated electric potential extracted along the gate-to-gate

direction (Y-direction) of an I-FinFET and gate-to-substrate direction of a Gate I-MOS, respectively Gate-to-gate coupling effect raises the potential in the centre of the nanowire or fin .79

Single-xvii

Figure 5.3 Extracted impact-ionization rate (simulated) in the I-region along the y-direction

perpendicular to the source-drain (x-direction) in the I-region Due to stronger

gate-to-channel coupling effect for the multiple-gate structure, impact-ionization is enhanced at the centre of the Si nanowire This will contribute to enhanced device performance at lower breakdown voltage .79 Figure 5.4 Important process sequence for the realization of the I-FinFET .80

Figure 5.5 Breakdown voltage |V BD | as a function of gate length L G for n- and p-channel

devices Decreasing channel resistance with decreasing L G increases the voltage drop

across the I-region and reduces |V BD| for both n- and p-channel devices N-channel

devices have a lower |V BD| than p-channel devices due to the lower impact-ionization threshold energy for electrons .82

Figure 5.6 Plot of measured change in breakdown voltage |∆V BD| as a function of the applied

drain bias |V D | Increasing the drain bias |V D| increases the voltage drop across the

I-region and reduces the breakdown |V BD| This is termed as drain-induced breakdown voltage lowering (DIBVL), and is similar to the drain-induced barrier lowering (DIBL) in conventional MOSFETs .82 Figure 5.7 Gate transfer characteristics for a 50 nm gate length n-channel I-FinFET at different

source biases Excellent subthreshold swing of sub-3 mV/decade is achieved As V S

is increased from -5.0 V to -5.5 V, the on-state current I on of 257 µA/µm at V G -V T = 1.0V is increased by ~1.42 times to 365 µA/µm 84 Figure 5.8 Gate transfer characteristics for a 50 nm gate length p-channel I-FinFET at different

source biases Excellent subthreshold swing of sub-3 mV/decade is achieved As V S

is increased from 5.0 V to 5.5 V, V T drops from -0.8 V to -0.23 V The on-state

current I on defined at V G -V T = -1.0V is increased by ~1.82 times 84 Figure 5.9 (a) 3-Dimensional Schematic of the impact-ionization nanowire multiple-gates

FinFET or I-FinFET with a raised source structure The cross-section schematics of p-channel I-FinFET with an elevated (a) Si I-region and source, and (b) SiC I-region and source are extracted along the line X-X’ of (a) .88

Figure 5.10 (a) Summary of process flow to form the I-FinFET with an elevated I-region and in

situ doped source There is no high thermal step after the in situ doped SEG of the

source region (b) shows the SEM view of the I-FinFET after spacer formation As shown in (c), the reciprocal space map of (004), and (224) show perfect alignment between the SiC and Si peaks, indicating pseudomorphic epitaxial growth .88

xviii

Figure 5.11 Breakdown voltage V BD as a function of gate length L G Decreasing channel

resistance with decreasing L G reduces V BD for p-channel devices 90

Figure 5.12 Plot of threshold voltage V T versus source voltage V S for the 3 types of devices with

a gate length L G of 50 nm Increasing V S reduces V T 90

Figure 5.13 (a) Gate transfer characteristics of p-channel I-FinFETs with a gate length L G of 50

nm, an I-region length L I of 45 nm, and an EOT~ 30 Å By employing in situ doping and strained SiC I-region, significant I on and G m enhancement are achieved (b) Off-

state current I off measured at (V G –V T ) = 0.2 V plotted as a function of V T for

p-channel I-FinFETs revealing that at matched V T , the I off of I-FinFET with in situ

doped SiC source is the lowest 92

Figure 5.14 (a) On-state current I on measured at (V G –V T ) = -1.0 V plotted as a function of V S for

p-channel I-FinFET At matched V S , the I on of I-FinFET with in situ doped SiC source is the highest among the three devices (b) Plot of I off versus I on for the p-

channel devices with various V S I on is measured at (V G –V T) = -1.0 V Significant

I on enhancement is observed for I-FinFET with in situ doped SiC source at the same

I off 92 Figure 5.15 (a) 3-Dimensional Schematic of the impact-ionization nanowire multiple-gates

FinFET or I-FinFET and SEM view (inset) The spacer next to the raised source defines the lateral I-region and the elevated structure beside the spacer defines the elevated I-region, raised source, and drain Thus, the L-shaped I-region comprises the lateral and elevated I-region The cross-section schematics of (b) Si I-FinFET, and (c) SiGe I-FinFET are extracted along the line X-X’ of (a) Shown here are n-channel devices The dotted L-shaped box outlines the impact-ionization region (I-region) .95 Figure 5.16 (a) Overview of the I-FinFET process flow The fabrication of I-FinFET is CMOS

process-compatible, and could be integrated with conventional CMOS planar and FinFET devices SEM view of (b) I-FinFET after gate formation, and (c) I-FinFET rotated by 135º, showing the source being masked by photo-resist (d) TEM view of

the fabricated SiGe-SD/SiGe I-FinFET with a gate length L G of 50 nm and a total

I-Region length L I of 40 nm .96

xix

Figure 5.17 Plot of measured I D -V S for n-channel control Si I-FinFET and SiGe I-FinFET

showing the breakdown voltages V BD of their p-i-n diode structures Lower breakdown voltage is observed for SiGe I-FinFET 98

Figure 5.18 Plot of measured I D -V S for p-channel control Si I-FinFET and SiGe I-FinFET

showing the breakdown voltages V BD of their p-i-n diode structures Lower breakdown voltage is observed for SiGe I-FinFET 98

Figure 5.19 (a) Measured I D -V G and (b) G m -(V G -V T ) for n-channel I-FinFET devices with 50nm

gate length, and 40nm I-region The threshold voltages V T are 1.28 V and 0.46 V,

respectively SiGe I-Region results in lower V T and higher I off at a fixed V S and V D of -4.75 V and 1.0 V, respectively 99 Figure 5.20 Gate transfer characteristics for p-channel I-FinFET devices with 50nm gate length,

and 40nm I-region The threshold voltages V T are -1.22 V and -0.56 V, respectively

SiGe I-Region results in lower V T and higher I off at a fixed V S and V D of 4.75 V and 1.0 V, respectively 99

-Figure 5.21 (a) Off-state current I off measured at (V G –V T ) = -0.2 V plotted as a function of V T for

n-channel I-FinFET revealing that at matched V T , the I off of Si I-FinFET is much

higher than that of SiGe I-FinFET (b) Measured I off - I on plot for the n-channel

devices with varying |V S | I on is measured at (V G –V T ) = 1.0 V Significant I on

enhancement is observed for SiGe I-FinFET at matched V T or the same I off 101

Figure 5.22 (a) Off-state current I off measured at (V G –V T ) = -0.2 V plotted as a function of V T for

p-channel I-FinFET At matched V T , the I off of Si I-FinFET is much higher than that

of SiGe I-FinFET (b) Plot of I off versus I on for the p-channel devices with various

|V S | I on is measured at (V G –V T ) = 1.0 V Significant I on enhancement is observed for

SiGe I-FinFET at matched V T or the same I off .101

xx

Chapter 6

Figure 6.1 Schematic of an n-channel L-shaped Impact-ionization MOS (LI-MOS) Transistor,

or an I-MOS Transistor with an Elevated Impact-ionization region (I-region), showing the equivalent resistances and dimensions in the I-region The total length

of I-region comprises a vertical I-region of length T I and a horizontal I-region of

length L S , with resistances of R V and R H, respectively For an n-channel device, the source is doped p+ while the drain is doped n+ 105

Figure 6.2 Variation of impact-ionization coefficient α n and α p as a function of the inverse of

electric field for Si and Ge, respectively A higher impact-ionization coefficient is favorable for LI-MOS device operation The impact-ionization coefficient of Ge is

at least 1-2 orders of magnitude higher than that of Si 107

Figure 6.3 Simulated I D -V G plot of Si and Ge n-channel LI-MOS transistors with source bias V S

of -5.25V and -1.8V respectively The drain is grounded Excellent subthreshold swing of sub-5 mV/decade is achieved for both devices Ge LI-MOS has a much

superior I on /I off ratio than Si LI-MOS due to the lower bandgap of Ge .108

Figure 6.4 Simulated I D -V G plot of Ge n-channel LI-MOS transistors with two different

substrate doping concentrations N B, showing a 1 mV/decade transition between the off- and on- states The voltage applied to the p+ source, V S is -1 V Increasing N B

causes V T to drop .109

Figure 6.5 Plot of threshold voltage V T versus substrate doping concentration N B for various

length L S , keeping T I fixed at 15 nm The L-shaped I-region has a total length L I =

T I + L S A longer L S causes V T to drop faster as N B increases .110

Figure 6.6 Plot of I off and I on /I off ratio as a function of substrate doping concentrations N B I off

decreases as N B increases This also causes the I on /I off ratio to increase .111

Figure 6.7 Threshold voltage V T generally increases with increasing T I L S and T I are two

adjustable parameters that allows for the flexibility of V T tuning .112

Figure 6.8 Plot of I off and I on /I off ratio as a function of I-region length L I I off increases rapidly as

L I becomes comparable to L G This also causes the I on /I off ratio to decrease .112

xxi

Figure 6.9 Comparison of V T as a function of device gate length for High-Performance (HP)

logic [2], I-MOS Low Static Power LSP), and I-MOS Low Dynamic Power

(I-LDP) technologies V DD values are the same for the HP and I-LSP technologies, and

are indicated above the open squares The corresponding V DD values for the I-LDP

technologies are indicated below each open triangle The low V DD achievable in LDP I-MOS devices translates to a much reduced dynamic power as compared to CMOS 114

Figure 6.10 Ge I-MOS technologies shows superior I off and I on characteristics as compared with

projected I off and I on targets for High-Performance (HP) CMOS technology [2] A

Low Static Power LI-MOS (denoted by I-LSP) employs the same V DD and transistor

structure parameters, e.g L G, as the corresponding HP logic technology For

example, I-LSP32 employs V DD = 0.9 V and L G = 18 nm The Low Dynamic Power LI-MOS (denoted by I-LDP) employs the same device structure parameters but a

lower V DD than that of the corresponding HP logic technology .115

Chapter 7

Figure 7.1 Schematic of (a) a Single-Gate (SG) TFET device, and (b) a Double-Gate (DG)

TFET Device Shown here is an n-channel device with a p+ source, and a n+ drain 118 Figure 7.2 Extracted Energy Band Diagram along the source to channel direction at the surface,

illustrating the modulation of the tunneling barrier width ω T from the off-state to the on-state .119 Figure 7.3 Comparison of the gate characteristics between SG TFET and DG TFET devices,

clearly showing the advantage of employing a double-gate structure Excellent subthreshold swing is achieved with ~2.25× on-state current enhancement for the

DG TFET device .122

Figure 7.4 Plot of on-state drain current I on and average current density J ave as a function of

silicon film thickness T Si The device operation spans from the regime of volume limitation to that of single-gate control limitation 122

xxii

Figure 7.5 (a) Electric potential extracted along the Y-direction near the band-to-band tunneling

region of the source-channel interface The tunneling barrier width ω T extracted near

the surface (Y ~3Å) and the center of the film (Y = T Si/2) for various silicon thicknesses is shown in (b) 123 Figure 7.6 (a) Schematic of a Double-Gate (DG) TFET Device with silicon-germanium (SiGe)

source (b) A zoomed-in view of the source end of the DG TFET, showing the

SiGe/Si hetero-junction The edge of the top gate is the origin for the x-y axes (c)

Simulated gate transfer characteristics of the DG TFET with SiGe source at various

L H The Ge content is 20% Lower threshold voltage V T with higher on-state current

I on is observed as L H increases from -2 nm to 2 nm 127 Figure 7.7 Extracted Energy Band Diagram along the source to channel direction near the

surface for (a) V GS = V DS = 0 V, (b) V GS = 0 V and V DS = 1.2 V, and (c) V GS = 1.2 V

and V DS = 1.2 V The application of the drain and gate bias modulates the tunneling

barrier width ω T from the off-state to the on-state With L H of 2 nm, ω T is reduced This will enhance the band-to-band tunneling (BTBT) rate, and hence on-state

current I on 127

Figure 7.8 (a) Plot of (a) off-state current I off , and (b) on-state current I on , as a function of L H

Generally, both I off and I on increase as the overlap of the hetero-junction with the

gate (L H) increases Both minimum and maximum points occur at certain value of

L H This could be explained by the variation in electric field and tunneling barrier

width as L H changes 129 Figure 7.9 (a) Extracted maximum electric field along the source to channel direction near the

surface for V gs = V ds = 0 V, V gs = 0 V and V ds = 1.2 V, and V gs = 1.2 V and V ds = 1.2

V The maximum electric field at various biases decreases as L H increases (b) Extracted maximum BTBT tunneling rate along the source to channel direction near

the surface for V gs = 1.2 V and V ds = 1.2 V 130 Figure 7.10 Gate transfer characteristics of DG CTFET with Si0.8Ge0.2 source region Excellent

subthreshold swing is achieved with high I on /I off ratio Compared to conventional

CMOS transistors, CTFET excel in terms of low I off and high I on .132

Figure 7.11 With increasing Ge content, the bandgap E g of SiGe decreases This results in a

corresponding decrease in the tunneling width ω T Hence, band-to-band tunneling is enhanced in a material with narrower bandgap .132

xxiii

Figure 7.12 Energy band diagram of DG TFET with Si1-xGex source where x = 0 (dashed lines),

and x = 0.4 (solid lines) Higher Ge content reduces the tunneling width ω T

substantially This leads to a higher band-to-band tunneling (BTBT) rate and a higher on-state current 133

Figure 7.13 Plot of simulated I D -V G for DG TFET with SiGe source Increasing Ge content

enhances the drive current and improves the subthreshold swing, as can be expected due to the reduction in tunneling barrier width .133 Figure 7.14 The subthreshold swing, which determinates how abruptly the transistor could be

switched with respect to gate voltage variation, improves as the Ge content is

increased S ave is the average subthreshold swing obtained from the segment of the

I D -V G curve where the drain current from I D ≈ 10-15 to 10-7 A/µm S min is the

minimum subthreshold swing in the same range of I D, which typically occurs in the

low I D regime 134

Figure 7.15 Plot of threshold voltage V T as a function of Ge content for two different power

supply voltages V DD HP and LSTP devices employed a V DD of 1.2 V while low

power device employs a V DD of 0.9 V V T reduces with increasing Ge content .135

Figure 7.16 I on is enhanced with the incorporation of higher Ge content Due to increased

band-to-band tunneling rate The higher V DD used in HP or LSTP technologies also induces higher tunneling rate than that in LOP technology .135

Figure 7.17 The ω T is reduced as the Ge content increases, hence giving rise to an exponentially

increasing I off Higher V DD also results in higher I off (reducing ω T) .136

Figure 7.18 Higher Ge content is required at shorter L G, to meet performance requrements For

LOP and HP logic devices, much higher Ge content is needed as compared to LSTP

logic or LSTP (low V DD) logic devices due to more stringent performance requirements .137 Figure 7.19 HP and LOP logic devices using DG TFET perform very well when benchmarked

against ITRS projections .137

Figure 7.20 LSTP devices using DG TFET with two different power supply voltage V DD perform

much better in terms of I off and I on than that specified by ITRS projections Using a

lower V DD for LSTP (low V DD) devices helps to reduce dynamic power and allows

for possible integration with HP logic using a common V DD .138

xxiv

Chapter 8

Figure 8.1 (a) Schematic showing the structure of a n-channel Si or Ge TFET with a p+ source

and n+ drain The n+ drain doping concentration N D and p+ source doping

concentration N S are varied in this study The profile of n- and p- type dopants from the p+ source to the n+ drain for a TFET device with N D = 1×1019 cm-3 and N S = 1×1020 cm-3 is plotted in (b) 143 Figure 8.2 Simulated and extracted energy band diagrams along the source to channel direction

near the surface for Si and Ge TFETs in the on-state The drain and gate biases

modulate the tunneling barrier width ω T In the on-state (V GS = 1.2 V and V DS = 1.2 V), tunneling occurs at the source-side As Ge has a smaller bandgap than Si, the

Ge TFET has a smaller ω T of 3.6 nm compared to that of the Si TFET (ω T ~ 5.1 nm) The enhanced band-to-band tunneling (BTBT) rate in Ge TFET gives a higher on-

state current I on than the Si TFET 145 Figure 8.3 Simulation and extracted energy band diagrams along the source-to-channel

direction at 0.3 nm below the surface for Si and Ge TFETs in the off-state In the

off-state (V GS = 0 V and V DS = 1.2 V), tunneling may occur at the channel-drain junction The drain-side tunneling distance for the Ge TFET in the off-state is much

smaller than that of the Si TFET, resulting in significantly higher I off .146

Figure 8.4 Gate transfer characteristics for Si and Ge TFET with N D of 1019 cm-3 Due to the

narrower bandgap of Ge compared to Si, the on-state current of Ge TFET is significantly higher than that of Si TFET However, the off-state leakage current for the Ge TFET is also significantly higher 147 Figure 8.5 Gate transfer characteristics for Ge TFET with various drain doping concentration

N D In order to reduce the channel to drain tunneling leakage current for Ge TFET

in the off-state, the drain doping concentration should be reduced so that the electric field near the drain is reduced and the tunneling distance is increased .148

Figure 8.6 Plot of off-state leakage current I off as a function of drain doping concentration N D

With lower N D , I off is reduced substantially, meeting the specifications for various types of logic devices .149

xxv

Figure 8.7 Energy band diagram along the source-to-channel direction near the surface for Ge

TFET with various drain doping concentration operating in the off-state at V GS = 0 V

and V DS = 1.2 V, as obtained from numerical simulation At higher N D , ω T is smaller

at the channel-drain junction, which results in high tunneling leakage current in the off-state 150 Figure 8.8 Energy band diagram along the source-to-channel direction near the surface for Ge

TFET with various drain doping concentration operating in the on-state at V GS = 1.2

V and V DS = 1.2 V In the on-state, ω T at the source side is not affected by the varied

N D .150 Figure 8.9 Gate transfer characteristics for Ge TFET with various source doping concentration

N S N D is kept low at 1018 cm-3 to reduce I off In order to increase I on , N S needs to be kept as high as possible In addition, the subthreshold swing also improves with

increasing N S 151

Figure 8.10 Plot of on-state current I on as a function of source doping concentration N S In order

to achieve higher I on , there is a need to increase N S substantially .152

Figure 8.11 Tunneling barrier width ω T as a function of source doping concentration N S The

higher I on at higher N S is a result of the narrower tunneling width The narrower tunneling width is contributed by larger band offset and bandgap narrowing effect due to heavy doping .153

Figure 8.12 Impact on subthreshold swing S (left axis) and threshold voltage V T (right axis) by

varying source doping concentration N S Lower V T and steeper S are achieved at higher N S 153

Figure 8.13 Variation of on-state current as a function of gate-source overlap Sufficient L ov is

required for adequate I on .154 Figure 8.14 (a) Gate transfer characteristics of Ge TFET as a function of gate work function (b)

Variation of threshold voltage as a function of work function 155

Figure 8.15 Gate transfer characteristics for Ge TFET with various oxide thickness T ox GIDL

has increases with thinner T ox However, in order to increase I on and improve S, T ox

needs to be kept as thin as possible .156

xxvi

Figure 8.16 Energy band diagram along the source-to-channel direction near the surface for Ge

TFET with various gate oxide thickness operating in the off-state at V GS = 0 V and

V DS = 1.2 V, as obtained from numerical simulation At thinner T ox , ω T is smaller or electric field is higher at the channel-drain junction, which results in high tunneling leakage current in the off-state .157

Figure 8.17 Impact of T ox on the (a) subthreshold swing S, and (b) threshold voltage V T of Si and

Ge TFET In general, better S and lower V T are achieved with thinner T ox Ge TFET has better scalability and higher performance .157 Figure 8.18 Gate transfer characteristics for Ge TFET as a function of power supply voltages

V DD GIDL current and I on have decreased with lower V DD .159

Figure 8.19 Extracted tunneling barrier width ω T near the surface as a function of power supply

voltages V DD ω T is a strong function of T ox and V DD 159

Figure 8.20 Impact of V DD on on-state current I on for various oxide thickness T ox Ge TFET

outperforms Si TFET in terms of I on even at much lower V DD .160 Figure 8.21 Gate transfer characteristics for Si, Ge, and InAs TFETs Narrower bandgap

materials result in a significantly higher I on However, the I off is also significantly higher 162

Figure 8.22 V DD scaling scenario for Si, Ge, and InAs TFETs Narrower bandgap materials are

required to maintain sufficient I on as V DD scales down 162

Chapter 3

Table 3.1 Summary of the process modifications carried out in this work and the impact on

device characteristics 31

ξ crit,n Critical electric field needed for avalanche multiplication for electron

ξ crit,p Critical electric field needed for avalanche multiplication for hole

ξ n Effective driving field for electron

ξ p Effective driving field for hole

ε XX Lateral strain

ε ZZ Vertical strain

λ n Optical-phonon mean free path

λ n Optical-phonon mean free path for electron

λ p Optical-phonon mean free path for hole

E Fn Fermi-level for electron

E Fp Fermi-level for hole

E g Band-gap

E o Energy

E OP Optical-phonon energy

E th Impact-ionization threshold energy

E th,e Impact-ionization threshold energy for electron

E th,h Impact-ionization threshold energy for hole

E V Valence band

J n Electron current density

J p Hole current density

L S Horizontal I-region/Spacer Width

l o Mean free path

M Multiplication factor

M n Electron multiplication factor

M p Hole multiplication factor

m e

*

Effective mass for electron

m h Effective mass for hole

m O Free electron effective mass

m r Relative effective mass

T epi Epi Thickness of SiGe

T final Final Thickness of SGOI

T initial Initial Thickness of SOI

T I Thickness of Vertical I-region

C-I-MOS Complementary Impact-ionization Metal-Oxide-Semiconductor

CMOS Complementary Metal-Oxide-Semiconductor

DG Double-Gate

xxxi

DIBL Drain Induced Barrier Lowering

DIBVL Drain Induced Breakdown Voltage Lowering

DS Double-Spacer

EOT Equivalent Oxide Thickness

FFT Fast Fourier Transform

GIBVL Gate Induced Breakdown Voltage Lowering

GOI Ge-On-Insulator

HRXRD High Resolution X-Ray Diffraction

I-CMOS Impact-ionization and Complementary Metal-Oxide-Semiconductor

I-FinFET Impact-ionization FinFET/nanowire

I-MOS Impact-ionization Metal-Oxide-Semiconductor

I-MuGFET Impact-ionization nanowire Multiple-Gate Field-Effect Transistor

I-region Impact-ionization Region

ITRS International Technology Roadmap for Semiconductor

LI-MOS L-shaped Impact-ionization Metal Oxide Semiconductor

LOCOS Local Oxidation of Silicon

MOS Metal-Oxide-Semiconductor

PR Photo-resist

RMS Root Mean Square

RSD Raised Source/Drain

RTA Rapid Thermal Anneal

RTO Rapid Thermal Oxidation

SCE Short Channel Effects

S/D Source/Drain

SEG Selective Epitaxial Growth

SEM Scanning Electron Microscopy

SIMS Secondary Ion Mass Spectroscopy

SG Single-Gate

SGOI SiGe-On-Insulator

SOI Silicon-On-Insulator

TCAD Technology of Computer Aided Design

TEM Transmission Electron Microscopy

TFET Tunneling Field-Effect Transistor

XRD X-Ray Diffraction

metric for assessing the circuit performance is the time delay τ d, which is given by

on

DD d

I

CV

=

where C is the parasitic capacitance, V DD is the power supply voltage and I on is the

transistor on-state current As such, reduction of both C and V DD , and increment of I on are the keys to improve the circuitry speed performance In addition, other metrics like the

dynamic power P dynamic and standby power P standby are desired to be kept as low as possible They are given by

P dynamic = C V DD 2 f (1.2)

P standby = W I off V DD (1.3)

where f is the driving frequency related to τ d , W is the device width, and I off is the off-state

current Hence, reduction of C, V DD , W and I off have been part of the technology

progression On the other hand, f or I on needs to be high for speed performance

Chapter 1 Introduction 2

However, Complementary Metal-Oxide-Semiconductor (CMOS) transistor faces fundamental physical and functional limits as we continue to scale beyond the sub-30nm regime It suffers from poor electrostatic control and short channel effects (SCE), giving rise to severe drain induced barrier lowering (DIBL) and band-to-band tunneling (BTBT)

which lead to high off-state leakage current I off Recently, technology innovations such as strained Si channels [3]-[5] and metal gate/high-k dielectric stacks [5]-[6] have been introduced to sustain the Moore’s Law Nevertheless, CMOS technology still faces several fundamental scaling challenges [7],[8] as performance improvement does not necessarily commensurate with technology scaling

In particular, power supply voltage V DD scaling becomes increasingly difficult Figure

1.1 illustrates the scaling scenario The V DD is reduced to curb the excessive power consumption, but this inevitably compromises speed performance for a given threshold

Figure 1.1 Gate transfer characteristics of (a) original device (black line) with fixed subthreshold swing S showing decreasing on-state current I on due to a reduction of power supply voltage V DD, and (b) original

device (black line) and scaled device (blue line) with fixed S showing increasing off-state leakage current

I on when threshold voltage V T is reduced

Gate Overdrive of Scaled Device

V T ’

I on

Chapter 1 Introduction 3

voltage V T as a result of the reduced gate overdrive [Figure 1.1 (a)] In order to maintain

or increase the gate overdrive or the on-state current I on , V T needs to be reduced This

reduction in V T in turn results in an exponential increase in I off, and hence increased static power consumption [Figure 1.1 (b)] The crux of the power consumption issue lies in one

of the fundamental limitations faced, i.e the non-scalability of the subthreshold swing S The equation that governs the relationship between I off and S is given by

) / (

)(

)0

D off

T

e V V I V

I

where I off is defined as I D at V G = 0 at V D = V DD Hence, reducing S would result in exponential decreased in power consumption The subthreshold swing S is an indication

of the sensitivity of the transistor current to a change in the gate voltage in the

subthreshold regime, and is limited by kT/q, where k is the Boltzmann’s constant, T is the absolute temperature, and q is the electronic charge For conventional CMOS transistor,

S is at its best 60 mV/decade at room temperature Moreover, aggressive scaling-down of

CMOS transistors has resulted in an increase of channel doping and aggravate the

degradation of the subthreshold swing [8] As such, the I on /I off ratio decreases tremendously

In this thesis, innovations to circumvent the above mentioned barriers are discussed

Various ways to achieve high I on /I off ratio by reducing S beyond that of conventional

transistor are explored This is achieved by utilizing new device structures and device physics, which will be discussed in details in the later sections Hence, the main motivation of this thesis is to explore new devices with steep subthreshold swing

Chapter 1 Introduction 4

1.2 Background

For a conventional CMOS transistor as depicted in Figure 1.2 (a), it operates through the injection of carriers from the source into the channel when the transistor is in its on-state [Figure 1.2 (b)] The fact that the energy distribution of carriers in the source follows a Fermi-Dirac distribution results in a subthreshold swing that is at least 60 mV/decade at room temperature This fundamental limitation on the minimum subthreshold swing is non-scalable even as device dimensions and supply voltage are reduced For the current state-of-art technology, it is in the range of 70-90mV/decade and

is expected to worsen as device scales further Multiple gate devices [9] could help alleviate this issue Unfortunately, the fundamental issue lies in the conduction mechanism of the conventional CMOS transistor which places a thermodynamic limit of kT/q on the subthreshold swing Thus, for a device to achieve a subthreshold swing of less than 60 mV/decade, it will have to depend on entirely new device physics As such, novel device structures are needed

Figure 1.2 Schematic of (a) a conventional CMOS transistor, and (b) its on-state energy band diagram

extracted from the source to drain direction Electrons in the source are injected into the channel by the lowering of the barrier through the control of the gate influence

(b)

Chapter 1 Introduction 5

One such option is to make use of the abrupt electric field dependence of impact

ionization To realize S of less than 60 mV/decade at room temperature, an

Impact-ionization Metal-Oxide-Semiconductor (I-MOS) device [10] that modulates the breakdown voltage of a gated p-i-n structure to switch between off and on states was proposed The n-channel I-MOS transistor is illustrated in Figure 1.3, featuring the gate stack with an adjacent n+ doped drain, an impact-ionization region or I-region where impact-ionization occurs, and a p+ doped source For a p-channel I-MOS transistor, the source is doped n-type, while the drain is doped p-type

The I-MOS transistor also exhibits better control of short channel effects than the conventional CMOS transistor due to the longer effective gate length in the off-state In a CMOS transistor, the off-state leakage current is a diffusion current of the majority carriers from the source, but in an I-MOS transistor, the off-state leakage current is the electrical drift of the minority carriers from the source to the drain In addition, the

Figure 1.3 Schematic of an n-channel impact-ionization MOS (I-MOS) transistor The I-MOS transistor has an asymmetric structure with an additional region for impact-ionization to occur This region is known as the impact-ionization region or I-region For an n-channel I-MOS, the drain is doped n+ while the source is doped p+

n + Drain

p + Source

Gat G

I-region

BOX

Chapter 1 Introduction 6

reverse-biased p-i-n diode helps to suppress band-to-band tunneling and leads to a much lower off-state leakage current in I-MOS This alleviates the problem of high power consumption faced by nanoscale CMOS technology

Figure 1.4 (a) shows the energy band diagram of the n-channel I-MOS transistor operating in the on-state The p-i-n diode is reverse-biased and current conduction in the I-MOS transistor has an abrupt dependence on the electric field in the I-region The application of gate bias lowers the conduction band in the channel and creates a high electric field in the I-region Above a critical electric field, impact-ionization occurs It is the avalanche breakdown effect that realizes a sub-5 mV/decade swing and excellent

I on /I off ratio as depicted in Figure 1.4 (b) This is compared to conventional MOS transistor which is limited by the 60 mV/decade swing Hence, the I-MOS technology is

an attraction option to realize devices with steep subthreshold swing

Figure 1.4 (a) Energy band digram of the n-channel I-MOS transistor operating in the on-state (b) Simulated gate transfer characteristics for conventional MOSFET and I-MOS Excellent subthreshold

swing of sub-5 mV/decade is achieved with high I on /I off ratio for the I-MOS transistor, whereas the subthreshold swing of the conventional MOSFET is greater than 60 mV/decade

Chapter 1 Introduction 7

Beside impact-ionization, the abrupt electric field dependence of band-to-band

tunneling (BTBT) is another option that could be utilized to achieve reduced S As such,

a new device known as the tunneling field-effect transistors (TFET) [10] has been proposed as an alternative switching device The TFET device is a gated p-i-n diode which exploits the gate-controlled band-to-band tunneling mechanism to overcome the

fundamental kT/q thermodynamic limit placed on the abruptness of the subthreshold swing S in conventional MOSFETs In addition, excellent short channel effects (SCE) and extremely low off-state leakage I off are achieved in TFET by virtue of its reverse-biased p-i-n diode configuration

Figure 1.5 (a) shows the n-channel TFET with the source and drain that are asymmetrically doped with p-type and n-type dopants, respectively p-channel TFET has dopants of the opposite polarity The structure of TFET is similar to that of I-MOS except that it does not have an impact-ionization region The energy band diagram of n-channel

Figure 1.5 (a) Schematic showing the structure of an n-channel Si TFET with a p+ source and n+ drain Tunneling occurs at the source-channel junction The energy band diagram of the TFET operating in the on-state is shown in (b) Electrons tunnel from the source to the channel when the tunneling barrier width

ω T is adequately small at a specific gate bias

Figure 1.6 Simulated gate transfer characteristics for conventional MOSFET and TFET Excellent

subthreshold swing of sub-25 mV/decade is achieved with high I on /I off ratio for TFET The extremely low

I off of TFET make such a device attractive for low power applications

TFET operating in the on-state is depicted in Figure 1.5 (b) The p-i-n diode is reversed biased Tunneling of electrons starts to occur near the source from the valence band to the

conduction band (towards the channel) when the gate bias V G is positive The tunneling

barrier width ω T at various V G determines the amount of electrons that could tunnel

across from the source to the channel With a narrower ω T, more electrons could tunnel through the barrier

The gate transfer characteristics of TFET and MOSFET are illustrated in Figure 1.6 TFET exhibits a subthreshold swing of 25 mV/decade, well below the 60 mV/decade

limit In addition, excellent I on /I off ratio is achieved with extremely low I off As such, TFET is attractive for ultra-low power applications