High k MOSFETS with high mobility channels

27 1.5.1 High-к gate dielectrics with substrate strain channel materials.... Application of high mobility channel materials and high permittivity high-к gate dielectrics in metal-oxide-s

HIGH-К MOSFETS WITH HIGH MOBILITY CHANNELS

HUANG JIDONG

(B Sc., Jilin Univ., CHINA and M.Sc., NUS, SINGAPORE)

A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF MECHANICAL ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE

2007

I would like to express my heartfelt gratitude and sincere appreciation to my supervisors, Dr Chunxiang Zhu (Department of Electrical and Computer Engineering), and Professor Andrew A O Tay (Department of Mechanical Engineering), who have led

me into this exciting area of microelectronics, and have offered me continuous encouragement, advice and support throughout this research project

I would like to thank Dr Celine Wong and Dr Vaidyanathan Kripesh from the Institute of Microelectronics, and Dr Yongwei Zhang (Department of Material Science) for their helpful advice and guidance during the first year of my PhD study My gratitude also goes to Dr Minghui Hong, Guoxin Chen, Dr Wendong Song from the Laser Microprocessing Lab for their great help on laser annealing; and Dr Zhi-Yuan Cheng from the AmberWave System Corp (U.S.A.), Dr Mingbin Yu from the Institute of Microelectronics (Singapore) for their warm cooperation on substrate preparation

I gratefully acknowledge my lab fellows for their valuable discussion and help on research, learning, and many other aspects in life during the past four years: Nan Wu, Qingchun Zhang, Xiongfei Yu, Chi Ren, Rui Li, Sung Jin Whang, Moon Sig Joo, Jinghao Chen, Sung Jung Kim, Yingqian Wang, Chen Shen, Xinpeng Wang, Jingde Chen, Fei Gao,Yan Song, Rinus Tek-Po Lee, Kian Ming Tan, Wan Sik Hwang, Andy Eu-Jin Lim, Zerlinda Tan, Chia Ching Yeo, Debora Poon, Samanta Santanu Kumar, Eric Yeow-Hwee Teo, Jia Fu, Wei He, Gang Zhang, Yi Tong, Jing Pu, Hoon-Jung Oh, Yu Fu Yong, Patrick Tang, Wai Linn O-Yan, Boon Tech Lau and many others from the Silicon Nano Device Lab; and Audrey Chng, Chun Deng, Aiping Tan, Ebin Liao, Manyi Pan, Bing

Wei Sun, Kim Shyong Siow, Arthur Kin Mun Kwok etc in the Nano/Micro Systems

Integration Lab In particular, I wish to express my sincere thanks to Nan Wu, Qingchun Zhang and Xiongfei Yu, for their innumerable helpful discussion and constructive suggestions on device fabrications, characterizations as well as data analyses in this project

The financial support from the National University of Singapore Nanoscience and Nanotechnology Initiative (NUSNNI) is also gratefully acknowledged

Finally, I want to thank my parents for their love, constant support and encouragement in all of my life

ACKNOWLEDGMENTS I CONTENTS III SUMMARY V List of Figures and Tables VII List of Symbols and Abbreviations XI

Chapter I Introduction 1

1.1 Improvement of MOSFET performance 3

1.2 Scaling limit for traditional gate dielectric SiO 2 6

1.3 Alternative high-к gate dielectrics 10

1.4 Channel carrier mobility enhancement 14

1.4.1 Strain-induced mobility enhancement 14

1.4.1.1 The piezoresistance effect 15

1.4.1.2 Strain-induced energy-band structure modification 16

1.4.1.3 Effect of strain type and stress direction on carrier mobility enhancement 19

1.4.1.4 Approaches to introduce strain in the carrier channel 20

1.4.2 Channel materials with high intrinsic carrier mobility 25

1.5 Literature review and objective of this study 27

1.5.1 High-к gate dielectrics with substrate strain channel materials 27

1.5.2 High-к gate dielectrics with germanium substrate 29

1.5.3 Scope of this study 30

References 32

Chapter II Device fabrication and characterization 38

2.1 Fabrication process of MOSFET 38

2.1.1 A typical fabrication process of MOSFET 38

2.1.2 Substrate structures 45

2.1.3 Thin film techniques for high-к dielectrics and metal gate deposition 47

2.1.4 Source and drain activation 50

2.2 Characterizations of MOSFET 52

2.2.1 Physical properties 52

2.2.2 Electrical properties 55

References 58

Chapter III Strained Si 0.5 Ge 0.5 MOS capacitors with MOCVD HfO 2 as gate dielectric 59

3.1 Introduction 59

3.2 Experiment details 60

References 68

Chapter IV Strained Si 0.5 Ge 0.5 MOS capacitors with MOCVD HfAlO as gate dielectric 70

4.1 Introduction 70

4.2 Experiment details 71

4.3 Results and discussion 72

4.4 Summary 79

References 80

Chapter V Strained Si 0.6 Ge 0.4 pMOSFETs with ALD HfO 2 as gate dielectric 82

5.1 Introduction 82

5.2 Experiment details 83

5.3 Results and discussion 84

5.4 Summary 96

References 97

Chapter VI Germanium nMOSFETs with n + /p junctions activated by laser annealing 99

6.1 Introduction 99

6.2 Experiment details 100

6.3 Results and discussion 101

6.3.1 Ge n + /p junction 101

6.3.2 Ge nMOSFET 108

6.4 Summary 112

References 114

Chapter VII Conclusions 117

7.1 Conclusions 117

7.2 Recommendations for future study 119

Appendix I: List of Publications i

Application of high mobility channel materials and high permittivity (high-к) gate dielectrics in metal-oxide-semiconductor field effect transistor (MOSFET) are of great interest to the modern semiconductor industry for further improvement of the performance of integrated circuits This dissertation consists of two parts: i) integration

of high-к gate dielectrics, HfO2 or HfAlO, on high hole mobility compressive SiGe (ε-SiGe) surface channel for pMOSFET; and ii) demonstration of high electron mobility pure germanium channel nMOSFET with HfO2 as gate dielectric and source/drain (S/D) dopants activated by laser annealing (LA)

strained-Following the first introductory chapter, a detailed description of typical MOSFET fabrication process and a brief introduction of techniques for characterization of physical and electrical properties of the devices in this study are presented in chapter II

Chapters III, IV and V deal with the first part of this dissertation The interfacial and electrical properties of metal organic chemical vapor deposition (MOCVD) HfO2 and HfAlO on compressively ε-Si0.5Ge0.5 substrate without or with surface rapid thermal nitridation (RTN) treatment were investigated Both TaN/HfO2/ε-Si0.5Ge0.5 and TaN/HfAlO/ε-Si0.5Ge0.5 capacitors with RTN showed superior capacitance-voltage (C-V) and current-voltage (I-V) characteristics compared to the capacitors without RTN However, RTN treatment resulted in hole mobility degradation for TaN/HfO2/ε-Si0.6Ge0.4

pMOSFET with atomic layer chemical vapor deposition (ALD) HfO2 as gate dielectric The effective hole mobility of the devices without or with RTN was showed to be

region

In the second part of this dissertation, formation of germanium n+/p junction by phosphorous implantation and subsequent LA is demonstrated as shown in chapter VI After being irradiated at a laser energy fluence of 0.16 J /cm2 with two successive pulses, the germanium n+/p junction exhibits a sheet resistance of ~50 Ohm/sq for the n+ region,

a comparable I-V characteristic, and much less phosphorus dopant diffusion in comparison with those formed by rapid thermal process (RTP) annealing Moreover, a gate-first self-aligned Al/TaN/HfO2/Ge nMOSFET with S/D activated by LA at a fluence

of 0.22 J /cm2 with one pulse was showed to give small S/D resistance and good stack integrity simultaneously It also has a larger drive current, a lower threshold voltage and a higher electron mobility at high effective field than those of the device with RTP annealing

gate-Finally, the conclusions drawn from this PhD research are summarized A few of recommendations for future study are also suggested

Figure 1.1 Schematic illustration of a submicron channel length complimentary MOSFET

(CMOSFET)

2

Figure 1.2 A typical chip cross-section illustrating hierarchical scaling methodology (after the

1999 Semiconductor Industry Association (SIA) roadmap) 2Figure 1.3 Sketch of a typical MOSFET structure on a bulk (B) substrate, in which L and W

represent the channel length and width, respectively When the carrier channel is in inverted state with a voltage applied on the gate (G), carriers can flow from the source (S) to drain (D) forming the drive current of transistor

4

Figure 1.4 The gate leakage current density limit (J g limit ) versus the expected value of the gate

leakage current density from the simulations (J g, simulated ) for high-performance logic (after IRTS 2005 [1.1]) EOT curves of planar bulk, fully depleted silicon-on- insulator (FDSOI) and dual-gate (DG) MOSFETs are also plotted for reference

11

Figure 1.7 Predicted band offsets for various high-к dielectric materials (after [1.3]) 12

Figure 1.8 Biaxial tensile strain-induced Si conduction band splitting in k-space (adapted from

[1.7][1.8])

17

Figure 1.9 Biaxial compressive strain-induced Si 1-x Ge x valence bands splitting in k-space (after

[1.9]) HH, LH and SO represent the heavy-hole band, light-hole band and spin-off band, respectively

18

Figure 1.10 The effect of various stress on electron and hole mobility in <110> channel on (001)

silicon wafer (adapted from [1.11] [1.12]) 19Figure 1.11 Schematic diagrams of a) uniaxial package strain produced by four-point bending

method (adapted from [1.13]), and b) biaxial package strain by displacement of the center of wafer (adapted from [1.14])

20

Figure 1.12 Schematic features of the various process strain (adapted from [1.8]): (a) silicon

nitride capping layer to create a tensile channel, (b) STI to create a compressive channel, (c) silicide strain and (d) embedded SiGe S/D process strain to created a compressive strain

21

Figure 1.13 A schematic diagram of lattice arrangement of Si Ge 1 x− x/Si Ge 1 y− y(withx y> ) 24

SiGe layer and the corresponding band alignment (after [1.8] [1.19])

Figure 2.1 A sketch of single mask ring-shaped MOSFETs with channel length of 20µm and

width of 100µm, where G, S and D presenting gate, source and drain regions, respectively

39 Figure 2.2 A typical fabrication process flow of MOSFET in this project 45 Figure 2.3 Schematics diagram of two kinds of ε-SiGe substrate structures in this project with

corresponding energy band alignment

46 Figure 2.4 A schematic sketch of the laser annealing experimental setup 52 Figure 2.5 A schematic sketch of spectroscopic ellipsometer 53 Figure 2.6 A schematic sketch of X-ray photoelectron spectroscopy 54 Figure 2.7 Sample of irregular sharp with four contacts at arbitrary places along the

circumference

55

Figure 2.8 Comparison of effective electron mobility among universal curve, Si control and

tensile strained Si channel nMOSFET with SiO 2 as gate dielectric 57Figure 3.1 XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for a DHF-cleaned ε-Si 0.5 Ge 0.5

substrate [curves (i)] and a DHF-cleaned ε-Si 0.5 Ge 0.5 substrate with subsequent deposition of a layer of ~10Å HfO 2 film by MOCVD without [curves (ii)] or with [curves (iii)] PDA at 600 ºC for 30 seconds

62

Figure 3.2 XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for a DHF-cleaned ε-Si 0.5 Ge 0.5

substrate [curve (i)], a DHF-cleaned ε-Si 0.5 Ge 0.5 substrate with surface RTN treatment [curve (iv)], and a DHF-cleaned ε-Si 0.5 Ge 0.5 substrate with RTN and subsequent deposition of a layer of ~10 Å HfO 2 film by MOCVD without [curve (v)] or with [curve (vi)] PDA at 600 ºC for 30 seconds The inset shows N 1s spectrum of the substrate with surface nitridation and a thin layer of HfO 2 film [curves (v)]

64

Figure 3.3 C-V characteristics (100-kHz) of the TaN/HfO 2 /ε-Si 0.5 Ge 0.5 MOS capacitor without

(solid line with open square) and with (solid line with open circle) surface nitridation treatment prior to HfO 2 deposition The physical thickness of HfO 2 measured by an ellipsometer is ~82Å

65

Figure 3.4 I-V characteristics of the TaN/HfO 2 /ε-Si 0.5 Ge 0.5 MOS capacitor without (solid line

with open square) and with (solid line with open circle) RTN prior to HfO 2

deposition

66

Figure 4.1 XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for DHF-cleaned ε-Si 0.5 Ge 0.5

substrate [curve (i)] and DHF-cleaned ε-Si 0.5 Ge 0.5 substrate with subsequent deposition of a layer of ~15Å HfAlO film without [curve (ii)] or with [curve (iii)] PDA at 600 ºC for 30 seconds The inset shows Al 2p3/2 spectrum of the substrate with a thin layer of HfAlO film without PDA [curve (ii)]

73

Figure 4.2 XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for DHF-cleaned ε-Si 0.5 Ge 0.5

substrate [curve (i)], DHF-cleaned ε-Si 0.5 Ge 0.5 substrate with surface nitridation treatment [curve (iv)], and DHF-cleaned ε-Si 0.5 Ge 0.5 substrate with surface nitridation

74

without PDA [curve (v)]

Figure 4.3 XPS data of (a) Al 2p3/2 and (b) Hf 4f spectra for DHF-cleaned ε-Si 0.5 Ge 0.5 substrate

with subsequent deposition of a layer of ~15Å HfAlO film without [curve (i)] or with [curve (ii)] PDA at 600 ºC for 30 seconds, and DHF-cleaned ε-Si 0.5 Ge 0.5 substrate with surface nitridation treatment and subsequent deposition of a layer of ~15 Å HfAlO film without [curve (iii)] or with [curve (iv)] PDA at 600 ºC for 30 seconds

75

Figure 4.4 C-V characteristics (100-kHz) of the TaN/HfAlO/ε-Si 0.5 Ge 0.5 MOS capacitor without

(solid line with open square) and with (solid line with open circle) RTN prior to HfAlO deposition

76

Figure 4.5 EOT dependence of gate leakage currents at Vg = V FB -1V for the

TaN/HfAlO/ε-Si 0.5 Ge 0.5 MOS capacitor without (solid triangles) or with (solid squares) RTN prior to HfAlO deposition The inset shows dependence of EOT on HfAlO physical thickness for both samples

78

Figure 5.1 5.1 XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for a DHF-cleaned ε-Si 0.6 Ge 0.4

substrate [curve (i)] and a DHF-cleaned ε-Si 0.6 Ge 0.4 substrate with subsequent deposition of a layer of ~10Å HfO 2 film by ALD without [curve (ii)] or with [curve (iii)] PDA at 600 ºC for 30 seconds

85

Figure 5.2 5.2 XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for a DHF-cleaned ε-Si 0.6 Ge 0.4

substrate [curve (i)], a DHF-cleaned ε-Si 0.6 Ge 0.4 substrate with surface RTN treatment [curve (iv)], and a DHF-cleaned ε-Si 0.6 Ge 0.4 substrate with RTN and subsequent deposition of a layer of ~10 Å HfO 2 film by ALD without [curve (v)] or with [curve (vi)] PDA at 600 ºC for 30 seconds

86

Figure 5.3 5.3 EOT and gate leakage current as a function of the PMA condition The

ε-Si 0.6 Ge 0.4 samples with RTN show better thermal stability than that without RTN 87Figure 5.4 5.4 I-V characteristics of Boron implanted p + /n junctions of ε-Si 0.6 Ge 0.4 samples with

PMA at 650 ºC 50 seconds or 850 ºC 15 seconds The later condition gives about one order magnitude lower of I off for all samples

89

Figure 5.5 5.5 Split C-V characteristics of TaN/HfO 2 /ε-Si 0.6 Ge 0.4 pMOSFETs without or with

RTN, with PMA at 850 ºC for 15 seconds 90Figure 5.6 5.6 (A) output and (B) transfer characteristics of TaN/HfO 2 /ε-Si 0.6 Ge 0.4 pMOSFETs

without or with RTN, with PMA at 850 ºC for 15 seconds

91

Figure 5.7 5.7 Charge pumping current for Si control, and ε-Si 60 Ge 40 pMOSFET without or with

RTN, with PMA at 850 ºC 15 s as function of base level of gate pulse 93Figure 5.8 5.8 XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for a DHF-cleaned ε-Si 0.6 Ge 0.4

substrate [curve (i)] and a DHF-cleaned ε-Si 0.6 Ge 0.4 substrate with subsequent deposition of a layer of ~10Å HfO 2 film by MOCVD without [curve (vii)] or with [curve (viii)] PDA at 600 ºC for 30 seconds

93

Figure 5.9 5.9 Comparison of effective hole mobility among Si control, and ε-Si 60 Ge 40

pMOSFET without or with RTN, with PMA at 850 ºC 15 seconds

95

Figure 6.2 Phosphorus SIMS profile of phosphorous-implanted Ge substrates after laser

irradiation at (a) various energy fluence with two successive pulses; (b) 0.16 J/cm 2

with different successive pulses The inset of (b) shows the SIMS dose measured on the substrate annealed by LA at fluence of 0.16 J/cm 2 with different successive pulses.

Figure 6.6 The effects of laser energy fluence with single pulse on sheet resistance of

phosphorous-implanted Ge substrates Also shown are the minimum sheet resistances achieved by RTA

109

Figure 6.7 (a) Output and (b) transfer characteristics of a Ge nMOSFET with S/D activated by

LA The output curve of device activated by RTA was also included in (a) as a reference

111

Figure 6.8 Extracted electron mobility as a function of the effective electrical field for Ge

nMOSFETs with S/D activated by LA or RTA

E Intrinsic Fermi level of semiconductor

EOT Equivalent oxide thickness

E

∆ Valence band offset between semiconductor and dielectric

FGA Forming gas annealing

J MOSFET gate leakage current density from the simulations

κ Relative permittivity (dielectric constant) of dielectric

χ Electron affinity of semiconductor

LA Laser annealing

L Length of transistor channel

LH Light hole

m∗ Electron effective mass

MOCVD Metal-organic chemical vapor deposition

PDA Post deposition anneal

PMA Post metallization anneal

PR Photo-resist

PVD Physical vapor deposition

κλ

π Piezoresistance tensor

QMCV Quantum-Mechanical CV simulator

s

R Sheet resistance,

RTA Rapid thermal annealing

RTP Rapid thermal process

RTN Rapid thermal nitridation

SIMS Secondary ion mass spectrometry

τ Average switching response time of the IC

VASE Variable angle spectroscopic ellipsometer

W Width of the transistor channel

XPS X-ray photoelectron spectroscopy

Chapter I Introduction

Since the advent of integrated circuit (IC) technology in the 1950’s, transistor dimensions have been continuously shrunk to improve circuit performance, enhance packing density and reduce manufacturing costs Following the trend known as Moore’s law, i.e the number of transistors per unit area on IC doubles approximately every 18 months, the shrinking of the transistor feature size has resulted in the traditional silicon-based IC technology approaching its fundamental limits today

The fundamental active devices in most of modern circuits, semiconductor field effect transistors (MOSFETs) (see Fig 1.1), are nowadays scaled down to submicron size with the gate length below 100nm and the gate insulator SiO2

metal-oxide-thickness below 2nm [1.1] The SiO2 with such a thin physical thickness may not have the insulating properties required, and the gate threshold voltage will be significantly reduced with a decrease of channel length to under one micron (short channel effect) Emergence of other manufacturing and reliability issues are predictable if shrinking of transistor dimensions continues Novel solutions are therefore increasingly being sought

to improve IC performance continuously Extensive research work has been carried out

on development and incorporation of new materials, from the interconnect level (copper, low-permittivity materials, etc) to the gate stack (high-permittivity dielectrics, metal gate electrodes, etc) and even to the substrate (strained carrier channels, germanium channel and silicon-on-insulator, etc) in circuit Figure 1.2 shows a typical chip cross-section illustrating hierarchical scaling methodology

FIG 1.1 Schematic illustration of a submicron channel length complementary MOSFET (CMOSFET)

Wire Via

FIG 1.2 A typical chip cross-section illustrating hierarchical scaling methodology (from the 1999 Semiconductor Industry Association (SIA) roadmap)

Copper Conductor with Barrier/Nucleation Layer

Dielectric Capping Layer Etch Stop Layer

Dielectric (low-k) Passivation

In the thesis, it is proposed to integrate high permittivity/dielectric-constant (high-к) gate dielectrics on Ge-rich compressively-strained SiGe channels with high hole mobility and pure germanium channels with both high electron and hole motilities, seeking to attain their advantages to improve MOSFET performance

In this introductory chapter, the relationship between performance of MOSFETs and device physical parameters will be briefly introduced, followed by discussions on limitations of traditional gate dielectric SiO2 and demand of high-к replacement Then the material structures of high mobility channels and their applications in enhancement of carrier mobilities will be described Finally, a brief review of relevant research work in literature and scope of this thesis will be given

1.1 Improvement of MOSFET performance

From a complementary metal-oxide-semiconductor (CMOS) circuit performance point of view, the performance merit of an IC considers the dynamic response (i.e charging and discharging) of the n- and p-MOSFTETs, associated with a specific circuit element and the supply voltage provided to the element at a representative (clock) frequency Considering a common element such as a CMOS inverter, the average switching response time (τ_ ) of an IC, is [1.2]

I are the drive current of n- and p-MOSFETs, respectively We can then

characterize the performance of an IC through this switching time It is easily seen that an

increase in the driven current I of MOSFET results in a decrease in the (higher d

switching speed) and an increase in the “figure of merit” of a circuit (better performance) Therefore, an improvement of MOSFET performance can be achieved by the enhancement of drive current

_

τ

d

I associated with the transistor

Figure 1.3 shows a sketch of a typical MOSFET structure on a bulk substrate When the carrier channel is in an inverted state with a voltage applied on the gate, carriers can flow from the source to drain forming the drive current of the transistor

Using gradual channel approximation, (i.e the variation of the electric field along the carrier channel is much less than the corresponding variation perpendicular to the channel) the driven current I initially increases linearly with d (the voltages applied to the drain of transistor), and then eventually saturates to a maximum value when

W: the width of the transistor channel

L : the length of transistor channel

µ: the channel carrier mobility

inv

C : the capacitance density associated with the gate dielectric when the

underlying channel is in the inverted state

g

V : the voltage applied to the transistor gate

th

V : the threshold voltage of transistor

For a given power supply voltage, increase of the term (V g −V th) is limited in range due

to reliability and room temperature operation constraints Increasing of the channel widthW is contrary to the down scaling of device dimension, while the reduction of the channel length L is approaching its fundamental limits today Thus the remaining

approaches to enhance the drive current I d sat, and eventually improve MOSFET

performance are increases of either the gate dielectric capacitance density or the channel carrier mobility

inv

C

µ, or both

1.2 Scaling limit for traditional gate dielectric SiO2

The MOS gate structure in a transistor (see Fig 1.3) can be simplified as a parallel plate capacitor from which theC invis given by

0

inv inv

t : the capacitive equivalent oxide thickness (CET) of the gate dielectric

Therefore, a thinner dielectric layer with a higher κ value will give a higher which is desirable Traditionally, consists of three CET components if poly-Si gate is used,

t : the main part of attributes to the gate dielectric, also known as

equivalent oxide thickness (EOT)

( ) 3.9 ox ox

T

t EOT

κ

Hence, reduction of any components especially t oxwill help to increase C inv

Table 1.1 Near-term high-performance logic technology requirements in ITRS 2005 [1.1]

Manufacturable solutions exist, and are being optimized

Manufacturable solutions are known

Manufacturable solutions are NOT known

However, is attributed to intrinsic mechanism that is unable to be eliminated can be released by using a metal gate This has triggered studies on metal gate technology in the past few years, which is not within the scope of this study However, one of the most widely studied metallic materials, Tantalum Nitride (TaN), was used as a metal gate in this study The reduction of , as the main part of , is the most practical approach in traditional technology, i.e thinning of the gate dielectric SiO

The gate insulator SiO2 is nowadays scaled down to sub-20Å as shown in Table 1.1 which summarizes the near-term gate stack related technology requirements for high-performance logic applications from the International Technology Roadmap for Semiconductors (ITRS) 2005 edition [1.1] With such a small physical thickness, SiO2

may not have the insulating properties required Also, due to quantum mechanical effects, electrons can tunnel directly through the gate insulator when it is reduced to just a few atomic layers

Figure 1.4 depicts the gate leakage current density limit ( J g limit, ) versus the expected value of the gate leakage current density from the simulations (J g simulated, ) for high-performance logic with silicon oxy-nitride (SiON) as gate dielectric It is obvious that for 2008 and beyond, the leakage current limit cannot be met even utilizing SiON (κ ≈6) because of direct tunneling Furthermore, for both curves the J g simulated, curve separates rapidly from the curve after 2008, indicating that gate leakage would rapidly become completely out of specification if SiON were to continue to be used for the gate

dielectric after that time Hence, continued device scaling requires the replacement of the conventional gate insulator with high-к dielectrics, very likely by 2008, in order to increase the physical thickness of the gate insulator and prevent tunneling currents while retaining the electronic properties of an ultrathin SiO2 film to enhance the gate dielectric capacitance densityC inv

FIG 1.4 The gate leakage current density limit (Jg limit) versus the expected value of the gate leakage current density from the simulations (Jg, simulated) for high-performance logic (after IRTS 2005 [1.1]) EOT curves of planar bulk, fully depleted silicon-on-insulator (FDSOI) and dual-gate (DG) MOSFETs are also plotted for reference

1.3 Alternative high-к gate dielectrics

A high-к dielectric must meet various requirements to act as a satisfactory alternative gate insulator First of all, it is clearly essential that the value of permittivity should be high enough to justify the cost of change Figure 1.5 shows dielectric constants

of some high-к materials versus their band gap values The к values of some materials, such as Y2O3 and Al2O3, are not really high enough as potential candidates

FIG 1.5 Variation of dielectric constant with band gap of high-к materials (after [1.3])

Secondly, the band offset of a dielectric at both conduction and valence band must

be high enough (>1eV) to ensure a low tunneling current [1.3] Figure 1.6 shows the energy-band diagram of an ideal metal-insulator-semiconductor (MIS) structure with n-

type semiconductor The barrier for electrons traveling from the substrate to the gate, and for electrons traveling inversely is the conduction band offset ∆E C ≈q[χ φ( M φB)]and the

2

die die

where C is a constant, is the physical thickness of the dielectric, is the voltage

drop across the dielectric, and m is the electron effective mass in the dielectric

Obviously, the leakage current increases exponentially with decreasing barrier height and the dielectric thickness Therefore, dielectric with larger

1eV as shown in Fig 1.7 This condition tends to restrict the dielectrics to those with band gaps higher than 5eV

FIG 1.7 Predicted band offsets for various high-к dielectric materials (after [1.3])

Hence, there has to be a trade-off between permittivity and barrier height A figure

of merit given as( has been developed by Yeo et al [1.4] to classify the

dielectrics in terms of their effectiveness as a tunnel barrier, where is the electron tunneling effective mass A value of ~4, ~10 and ~20 was obtained [1.4] for SiO

it is undesirable if an unstable reactive interfacial layer is formed between high-к dielectrics and the substrate However, most of the high-к metal oxide systems were reported [1.2] to react with silicon substrate during the dielectric deposition and post

deposition processes such as post deposition anneal (PDA) The interfacial layer thus formed is usually of relatively low permittivity that severely compromises the capacitance gain from any high-к layers in the gate stack It may also bring in other issues related to dielectric quality and device reliability such as high density of electrical defects On the other hand, there could be a material phase changing in the high-к dielectric itself during different thermal processes, normally from amorphous state, to polycrystalline, even to single crystalline A persistent amorphous state with high-к dielectric is preferred since crystallization of gate dielectric may increase the gate leakage by current penetration through the grain boundaries of dielectric and undesirable anisotropic material properties Therefore a dielectric with better thermal stability including higher crystallization temperature is desired

There are some other aspects which need to be considered for selection of high-к gate dielectrics, such as: A) high-к dielectrics without low-lying ‘soft’ polar modes have advantages since device mobility degradation related to remote scattering of carrier by low frequency phonon modes in high-к dielectrics could be eliminated; B) defects in dielectric may cause serious mobility degradation and gate threshold voltage shifting therefore a less defective dielectric is favorite; C) the deposition process for high-к dielectric should be compatible with current or expected CMOS processing, cost and throughput

Although a material which satisfies all of considerations has yet to be determined, several promising candidates have been identified, such as La2O3, HfO2, and Hf-based pseudo-binary alloys (HfSiO, HfSiON, HfTaO, and HfLaO) In this study, HfO2 was

selected as principal gate dielectric for its relatively simple chemical composition and formation techniques as well as its good material properties

1.4 Channel carrier mobility enhancement

Theoretically, the carrier mobilityµ (cm2/V•s) of a material is an intrinsic material property, defined as the proportionality of carrier drift velocity (V d) to electric field (ξ) applied on the material when ξis low enough, and

in the channel to gain strain-induced mobility enhancement, or using new channel materials with higher intrinsic carrier mobility, or both

1.4.1 Strain-induced mobility enhancement

Strain-induced carrier mobility enhancement can be examined in two ways: the piezoresistance effect and energy-band structure Depending on the type of strain and the direction of stress applied relevant to the direction of current flow in MOSFET, strain has various effects on carrier mobility enhancement

1.4.1.1 The piezoresistance effect

The effect of mechanical stress on electrical resistance of a material, namely piezoresistance effect, had been extensively studied almost one century ago Normally, the piezoresistance, i.e the fractional change in resistivity (ρ) with small stress (T ) less than yield stress, is given by

λ

6 1

T

κ

κλ λ λ

4

5 44

5

6 44 6

These piezoresistance tensors can be evaluated experimentally For instance, the ,

and of silicon were experimentally estimated [1.6] to be -102.1, 53.4, and 136 (Ω•cm/10

11

π π12 44

π

-11 Pa) for electrons respectively, and 6.6, -1.4, and 138 (Ω•cm/10-11 Pa) for holes respectively

The altering of net resistance (thereby conductivity) of channel material with stress eventually results in increase or decrease of the driven current I of MOSFET at same d

electrical conditions, which is equivalent to enhancement or reduction of the carrier mobilityµof channel material (see Eq 1.2)

1.4.1.2 Strain-induced energy-band structure modification

Fundamentally, strain-induced carrier mobility changes can also be understood by studying the influence of strain on conduction and valence-band structures Strain has two main effects on the band structure of a semiconductor [1.7]: 1) hydrostatic strain shifts the energetic position of a band, and 2) uniaxial or biaxial strain splits degenerate bands The population of carriers and hence the resistivity of a semiconductor therefore change

I Electron mobility enhancement

The electron mobility enhancement can be explained by the conduction band structure modification induced by strain For instance, in a layer of silicon under biaxial tension strain, such as Si/ relaxed system (see 1.4.1.4 for more discussions), the tensile strain will lift the six-fold degeneracy in Si conduction band and lowers the two perpendicular valleys ( ) with respect to the four in-plane valleys ( ) in k-space as shown in Fig 1.8 The splitting energy is given by 0.67x eV where x is the Ge content of the substrate Electrons occupy preferentially the lower-energy valleys, which has the lower effective in-plane transport mass of electron The carrier mobility

is therefore increased (see Eq 1.7) The energy splitting also suppresses inter-valley

phonon-carrier scattering, increasing the electron low-field mobility

II Hole mobility enhancement

The hole mobility enhancement can be explained by the valence band structure modification induced by strain For instance, for epitaxially grown on silicon by which it is under biaxial compressive strain (more discussion will be given below), its valence bands become nondegenerate at k = ~ 0, and the heavy hole (HH) band moves upwards while the light hole (LH) band moves downwards as shown in Fig 1.9 It can be seen that the energy split associated with the LH band is less pronounced than the corresponding shift in the HH band, implying a larger proportion of the hole concentration in the HH band [1.9] Moreover, it has been shown [1.10] that the effective

1 x

Si Ge− x

FIG 1.8 Biaxial tensile strain-induced Si conduction band splitting in k-space (adapted from [1.7][1.8])

in-plane transport mass of hole is systematically decreased as Ge composition (i.e the

h

m∗

x value) increases (a larger curvature of HH band at region of k = ~0), which also results in increase of the strain in the The carrier mobility is therefore increased (see Eq 1.7)

HH

k

HH

LH LH

Degenerate

FIG 1.9 Biaxial compressive strain-induced Si1-xGex valence bands splitting in k-space (after [1.9]) HH, LH and SO represent the heavy-hole band, light-hole band and spin-off band, respectively

1.4.1.3 Effect of strain type and stress direction on carrier mobility enhancement

From the piezoresistance effect discussed previously, it is obviously that different types of strain (tensile or compressive) and the direction of stress will result in various effects on carrier mobility enhancement for MOSFETs

Considering the technologically important (001) silicon wafer with wafer notch on the [110] axis (see Fig 1.10) as an example, the direction of current flow for transistors with 0º and 90º orientation is along the [110] axis Based on piezoresistance coefficients simply taken from silicon bulk values, the effects of strain type and stress direction enhance or degrade the electron (for NMOS) or hole (for PMOS) mobility have been

obtained by Ge et.al from TSMC [1.11] and Scott et.al from Intel [1.12] as summarized

in Fig 1.10 As can be seen, for the <110> channel direction the most effective stresses

to implement are longitudinal compressive stress for pMOSFETs, and longitudinal tensile and out-of plane compressive stress for nMOSFETs

+++

++

TensionTension

Transverse

+

++++

TensionCompression

Out-of-plane

++++

+++

CompressionTension

Longitudinal

PMOS NMOS

Direction

FIG 1.10 The effect of various stress on electron and hole mobility in <110> channel

on (001) silicon wafer (adapted from [1.11][1.12])

1.4.1.4 Approaches to introduce strain in the carrier channel

Since carrier mobility in a strained channel can be significantly enhanced, extensive studies on implementation of strain into carrier channels have been carried out There are several approaches currently used to introduce strain in the carrier channel in MOSFETs which could be categorized into: i) package strain, ii) process-induced (local) strain, and iii) substrate (global) strain

I Package strain

Strain in the carrier channel can be induced by bending a substrate directly or by bending a package substrate with semiconductor chips glued firmly on its surface The package strain can be applied uniaxially by one-end-bending method, or four-point-bending method as sketched in Fig 1.11 (a), or biaxially by producing displacement of the center of a wafer as sketched in Fig 1.11 (b) Package strain can be applied to both short and long-channel devices and improve the NMOS and PMOS devices performance after the fabrication of integrated circuits

FIG 1.11 Schematic diagrams of a) uniaxial package strain produced by four-point bending method (adapted from [1.13]), and b) biaxial package strain by displacement of the center of wafer (adapted from [1.14])

II Process strain

Strain in the carrier channel can also be induced intentionally during device processing This process strain technology can improve the performance of NMOS and PMOS devices due to the appropriate local strain Several approaches such as a) silicon nitride capping layer, b) shallow-trench isolation (STI), c) silicidation processes, and d) embedded SiGe S/D have been utilized individually or in combination to realize the local strain [1.15]-[1.17]

(d) (c)

FIG 1.12 Schematic features of the various process strain (adapted from [1.8]): (a) silicon nitride capping layer to create a tensile channel, (b) STI to create a compressive channel, (c) silicide strain and (d) embedded SiGe S/D process strain to created a compressive strain

Basically, each of the approaches employs at least a stressor, i.e stress-inducing structure, in the vicinity of the carrier channel region The silicon nitride (SiN) film is known to produce either a tensile or compressive strain depending on its deposition conditions: thermal chemical vapor deposition for tensile film and plasma-enhanced chemical vapor deposition for compressive film The tensile or compressive SiN films induce tensile or compressive strain in the channel region of NMOS or PMOS, thereby improving their performance Similarly, STI that is frequently used for lateral isolation in deep sub-micrometer technology, induces a compressive strain in the channel region and improves the drive current of PMOS The silicide-induced strains in the channel is due to the difference in the coefficient of thermal expansion (CTE) between the silicide and silicon, which normally yield compressive Si underneath since the common silicides (TiSi2, CoSi2, and NiSi) have larger CTE than Si, and may provide beneficial strain-improving NMOS performance As for embedded SiGe S/D, the lattice constant of SiGe alloy is larger compared to bulk Si, which creates a compressive stress in the carrier channel thereby resulting in hole mobility improvement for PMOS

The process strain is effective for the ~100nm node and beyond Its enhancement effect diminishes for large channel devices

III Substrate strain

Substrate strain allow for the fabrication of wafer-scale strained layers that can confine holes or electrons for both short channel and long channel devices The strain of

a channel layer (strained Si or Si Ge1−y y) is induced by a buffer layer (strained Si Ge 1 x− x or

Si) that is deposited as a stressor underneath the channel layer, leading to appreciable carrier mobility and drive current enhancement

It is known that silicon and germanium, both crystallize in the diamond lattice, are completely miscible for a full range of composition which form solid solutions

(

1 x

Si Ge− x

x is atomic fraction of Ge, ranging from 0 to 1) The lattice parameter of ,

experimentally follows a parabolic relation [1.18] as a function of

where =5.431Å and =5.646Å Therefore the lattice mismatch for SiGe alloys can

be up to ~4% which is helpful for strain generation

Si

For instance, when a thin film with a larger lattice constant, e.g., is

epitaxially grown on another thin film with smaller lattice constant, e.g., ( )

on relaxed cubic Si substrate as shown in Fig 1.12, the two films retain the in-plane lattice constant of the substrate and are under a biaxially compressive strain if their thicknesses are smaller than critical values Also shown in the figure is the corresponding band alignment The band offset between such SiGe alloys and Si is mainly on valence bands (with negligible conduction band offset), and hole mobility in such a channel structure can be improved due to the valence band modification and alloy-induced intrinsic hole mobility enhancement discussed previously

1 x

Si Ge−

Si Ge− x y>

HH Δ4

HH & LH Δ6

Ec Ev

FIG 1.13 A schematic diagram of lattice arrangement of Si Ge 1 x− x/Si Ge 1 y− y(withx> ) y

epitaxially grown on Si, and the corresponding band alignment (after [1.8] [1.19])

On the contrary, when a thin film with a smaller lattice constant, e.g Si is epitaxially grown on another layer with larger lattice constant, e.g., relaxed SiGe layer as shown in Fig 1.13, the film retains the in-plane lattice constant of the substrate layer and

is under a biaxial tensile strain if it is thinner than the critical thickness Both conduction and valence bands of the Si film are therefore modified as shown in the figure, which enhances carrier mobility especially the electron mobility significantly in such a channel structure

Substrate strain has been shown to improve both electron and hole mobilities but it suffers some issues related to the substrate such as the limitation of thermal budget and generation of threading defects (~1 × 105 cm-2) due to the existence of SiGe alloys, and a relative high production cost

As we continue to scale MOSFETs, it is unclear what the optimal approach(es) will

be and how to integrate them into the IC process flow according the ITRS 2005 Edition [1.1] In this project, we focus on adaptation of strain channel induced by the substrate strain approach

1.4.2 Channel materials with high intrinsic carrier mobility

The strain-induced carrier mobility enhancement is quite limited In order to further boost drive current of MOSFET, there have been increasingly interested in building the device on alternative channel materials with higher intrinsic carrier mobility other than silicon

The most promising alternative channel materials include pure germanium, silicon germanium alloy and some III-V semiconductors such as gallium arsenide (GaAs) Table

1.2 shows some basic intrinsic material properties of semiconductors Si, Ge and GaAs at

300 K As can be seen, both electron and hole mobilities of germanium surpass those of silicon by ~2 and ~ 3 times, respectively The mobilities of ideal silicon germanium alloy are also intrinsically improved compared to silicon since the alloy effect on the mobilities normally could be estimated by linear interpolation of relevant parameters from silicon and germanium [1.7] [1.19] The electron mobility of GaAs is ~ 6 time higher than that of silicon which makes it an attractive candidate for n-channel MOSFET in future

However, MOSFETs with those compound semiconductors as well as germanium

as channel materials have been elusive for decades, mainly due to the lack of stable and high quality native oxides on them in contrast to the counterpart silicon oxide on silicon However, the development of high-к dielectric technology during the past decade have provided some potential technology solutions for those MOSFETs with new channel materials, since those high-к dielectrics rather than the native oxides of channel materials can be used as the gate insulator In this project, germanium MOSFET with high-к gate dielectric will be studied