CRITICAL DIMENSION AND TEMPERATURE CONTROL IN MULTI ZONE THERMAL PROCESSING 2

This thesis investigates the application of advanced process control for thermalprocessing in the lithography step to improve lithography performance as the finalCritical Dimension CD un

I would like to express my deepest gratitude to my supervisor, Professor Ho WengKhuen, for his excellent guidance and consistent support throughout my grad-uate research at the National University of Singapore I have indeed benefitedenormously from the insightful advice and instruction that he offered in our dis-cussions Without his dedicated help, this thesis would have been impossible Iwould also like to express my appreciation to Professor Ling Keck Voon for hishelp rendered to my research in Multiplexed Model Predictive Control.

I would also like to acknowledge the National University of Singapore for thegenerous scholarship and research facilities I am also extremely thankful to myfriends and colleagues: Dr Fu Jun, Dr Chen Ming, Dr Yan Han, Dr WangYuheng, Dr Shao Lichun, Mr Nie Maowen, Mr Chua Teck Wee, Mr Ngo YitSung, and many others working in the Advanced Control Technology Laboratory

I have enjoyed the excellent cooperation during the experiment implementationand entertaining time spent on the badminton court with them We have allcontributed to the conducive and congenial working environment

Finally and most importantly, my heartfelt thanks to my parents and friend for their love and support Their love is my impetus to overcome difficultiesfaced not only in research but also in my daily life I would have never reached

girl-so far without their constant encouragement and support

1.2 Contributions 5

1.2.1 Improvement of CD Uniformity by Real-Time Temperature Control 6

1.2.2 Experimental Evaluation of MMPC Computation Load 7

1.2.3 Derivation and Experimental Verification of MMPC ISE formula for PEB process 8

1.3 Organization 9

2 CD and Real-Time Temperature Control for Warped Wafers 10 2.1 Introduction 11

2.2 Thermal Modeling of the Baking Process 15

2.3 Experiment 19

2.3.1 Setup 19

2.3.2 Runs 20

2.3.3 Real-Time Control 25

2.4 Conclusion 31

3.3 Multi-Zone Bake Plate Thermal Modeling 41

3.4 Experimental Results 43

3.5 Conclusion 48

4 Integral Square Error Performance of Multiplexed MPC 54 4.1 Introduction 54

4.2 ISE Formula for Multiplexed MPC 56

4.3 Experiment 63

4.4 Conclusion 67

5 Conclusion 71 5.1 Summary 71

5.2 Future Work 74

Bibliography 76

This thesis investigates the application of advanced process control for thermalprocessing in the lithography step to improve lithography performance as the finalCritical Dimension (CD) uniformity is sensitive to temperature during thermalprocessing.

Wafer warpage affects the thermal processing in lithography and can result in

CD nonuniformity Real-time temperature control is proposed and demonstrated

in the thesis that real-time control of the post-exposure bake temperature to give

a non-uniform temperature distribution across a warped wafer can reduce CDnon-uniformity across the wafer

Multiplexed Model Predictive Control (MMPC) has recently been proposed

as a strategy to reduce computational complexity It is experimentally strated in the thermal processing step that MMPC has computational advantageover the Standard MPC (SMPC), for large horizon and when constraints arepresent The reduction in computational load can be used gainfully to increase

demon-sampling rate and improve thermal processing performance.

To provide a framework for systematic analysis of the MMPC, a formula

to compute the Integral Square Error (ISE) performance for load disturbance isderived and validated on a multi-zone semiconductor manufacturing thermal pro-cess Experimental results validate the formula and show that shorter samplingtime can result in faster recovery of bake-plate temperature when a cold wafer isplaced on the bake-plate

List of Figures

2.1 Baking of Flat Wafer 1 Solid-line: center, Dashed-line: edge 13

2.2 Baking of Warped Wafer 4, Solid-line: center, Dashed-line: edge 14

2.3 The bake-plate used in the experiment 15

2.4 Baking of Wafer 16

2.5 Critical dimension measurements Circle: center; Square: edge;Wafer 1–3: flat wafer with conventional baking; Wafer 4–6: warpedwafer with conventional baking; Wafer 7–9: flat wafer with opti-mized baking; Wafer 10–12: warped wafer with real-time on-lineadjustment of bake-plate temperature setpoints 21

2.6 Temperature measurement on a warped wafer with no photoresistnor pattern Solid-line: center, Dashed-line: edge 24

2.7 Bake-plate setpoint adjusted to give uniform CD for Flat Wafer 7.Solid-line: center, Dashed-line: edge 26

tected to give uniform CD for Warped Wafer 10 Solid-line: center,Dashed-line: edge 30

3.1 Patterns of input moves for Standard MPC (left), and for the tiplexed MPC (right) 35

Mul-3.2 Experimental Temperature Responses (Solid) and TemperatureResponse of the Model (Dashed) 44

3.3 Experimental temperature disturbance (’x’) and Step Response ofthe Disturbance Transfer Function (Solid) 46

3.4 Performance and computation time of MMPC and Standard MPC

3.7 Maximum Computation Time in the experiment 53

4.1 Temperature Responses of MMPC with sampling interval 0.4s (Solid)and 1.0s (Dashed-dot) superimposed with simulation (Dashed) 69

4.2 Comparison of Experimental (’x’) and Theoretical (’o’) ISE 70

Lithography has been one of the fundamental technologies in semiconductor ufacturing In modern microelectronics manufacturing, lithography alone com-prises about 30% of the entire chip manufacturing cost [1] and accounts for 40%

man-to 50% of the man-total production cycle time [2] Lithography is also seen as the keydriver in scaling down device size, and historically, advances of lithography havesignificantly reduced wafer fabrication cost and improved circuit performance [3]

The Critical Dimension (CD) or the linewidth of the photoresist pattern isthe key output in lithography The shrinkage of CD has the most impact onchip speed and performance [1] For instance, both propagation delay and drain

current are proportional to the inverse of the channel length which is determined

by CD It is assessed that 1nm variation in gate CD results in 1MHz variation inchip speed [4]

Thermal processing is integrated as part of lithography, including variousbaking steps such as the post-apply bake, post-exposure bake and post-developbake [5] Thermal processing has been identified as one major source of CDvariation [6] The most temperature sensitive thermal process in lithography isthe post-exposure bake (PEB) process [7] The PEB step stimulate the chemicalamplification process for most of chemically amplified resists (CARs) For 193nmCARs, a representative PEB latitude for CD variation is about 7-10nm/◦C [8].Temperature sensitivity of KrF resists is on the order of 2-16nm/◦C [9]–[10] Forcommercially available deep ultraviolet (DUV) resists, a representative sensitivity

of 8 nm/◦C was reported in [11]–[12] The resists quoted are used in the DUVprocess and the nominal CD is 200 nm

The high sensitivity of CD variation to temperature implies that CD can becontrolled by the temperature control in thermal processing, especially in PEB.Zhang et al [13] showed that the implementation of an advanced thermal pro-cessing system in PEB could reduce CD variation by 40% Zhang et al [14] andLee et al [15] also showed that CD variation could be reduced by adjusting PEBtemperature through a multi-zone bake plate Specifically, temperature unifor-mity among the thermal processing system of PEB is critical to CD uniformity

tolerances of the temperature [20] A state-of-the-art 49-zone bake-plate with aLinear Quadratic Gaussian (LQG) controller has been proposed in [21].

The implementation of advanced process control (APC) has shown mance improvement in lithography process [20, 22] However, as the photolithog-raphy industry moves to bigger substrate and smaller CD, the stringent require-ments for lithography thermal processing still persists [23] Stresses from siliconwafer processing may cause wafer warpage [24], which will affect the resist pro-cessing at the various baking steps and eventually affect the CD in lithography.Another challenge is that a computationally amenable algorithm is required toapply real-time APC methodology in multi-zone bake plate temperature control

perfor-to meet the more and more stringent requirements

1.1.1 Warpage Effects in Lithography

Warpage is one challenge for PEB processing of wafers [24] [25] One factor thatcontributed to warpage was stress [24] [26] studied the influences of Warpage on

baking temperature, and gave quantitative results as 1◦C change for a warpage

level of 50 µm through simulation studies Such variation will cause substantial

CD nonuniformity

Since warpage is usually different from wafer-to-wafer, measurement of warpage

is essential for CD nonuniformity compensation The warpage can be measured

by various methods [27] The shadow and projection Moire techniques are widelyused warpage measurement methods [28] Warpage can also be measured throughcapacitive probes [29] and through the pneumatic-electromechanical effects [30].All these methods have the advantage that they can give the precise profile ofthe warped wafer However, one disadvantage is that they are off-line and needextra processing time to obtain the warpage information Further, the delay be-tween the exposure and the PEB steps needs to be reduced due to post-exposuredelay effect of chemically amplified resists [31] This would eliminate any timeconsuming measurement between these two steps One objective of this thesis

is to adopt an in-situ warpage detection method for proper PEB processing ofwarped wafers to obtain CD uniformity

been proposed As the number of bake plate zone is up to 49, computational loadwill be a concern in real time control of bake plate using standard MPC.

A variant of Model Predictive Control, called Multiplexed MPC, or MMPC,has been proposed recently [33] and stability results for MMPC have also been es-tablished [34] The motivation for MMPC was to reduce real-time computationalload on multivariable systems It has been applied on a multi-zone bake-plate andhas been demonstrated experimentally that MMPC has the potential to respondand recover faster than standard MPC when disturbance takes place [35] Asthe close-loop performance is affected by many factors, for example the samplingrate, the MMPC design for the thermal process needs to be further investigated

In this thesis, the application of real time process control of warped wafer andMMPC control algorithm to meet some stringent requirements in lithography

is investigated This thesis will address three areas: 1) Improvement of CDuniformity by real-time temperature control for warped wafers during PEB, 2)Derivation and validation of a formula to compute the Integral Square Error (ISE)performance of a MMPC controlled thermal system, 3) Experimental evaluation

of MMPC computational load carried out on a multi-zone thermal system

1.2.1 Improvement of CD Uniformity by Real-Time

Tem-perature Control

A real-time temperature control method will be proposed to improve CD mity for warped wafers It is noted that bake plate temperature will drop to amaximum value before recovering to the set point It is also noted that flat waferand warped wafer give different maximum temperature drop Thus wafer warpagecan be detected from the maximum temperature drop Once the warpage is de-tected, the bake plate temperature can be adjusted in real-time accordingly toreduce wafer temperature variations The wafer-to-wafer CD variation compen-sation will be demonstrated experimentally

unifor-There are also temperature and CD nonuniformity across the wafer due tothe different air-gap at different location To realize within-wafer CD uniformity,

a multizone bake plate is used, with the capability to bake different zones todifferent temperature independently When the maximum temperature drops of

1.2.2 Experimental Evaluation of MMPC Computation

Load

Multiplexed MPC, by distributing the control moves over a complete updatingcycle, reduces computational load otherwise incurred by Standard MPC We pro-vide one of the first experimental verification of the computational load reduction

property of Multiplexed MPC This is especially so when N u is large and whenconstraints are present

It is shown that MMPC has computational advantage over the StandardMPC, for large horizon and when constraints are present Thus, the MMPCalgorithm can be applied to multi-zone bake-plate system and its property ofreduced online computational time has the potential to make MPC scalable tomore sophisticated (more zones) bake-plate system

1.2.3 Derivation and Experimental Verification of MMPC

ISE formula for PEB process

Temperature non-uniformity will affect critical dimension of the wafer MMPChas the comparable response with that of standard MPC when disturbance takesplace However, it should be noted that there are many factors affecting closed-loop performance, such as sampling rate, controller tuning, etc

Therefore, it is worthwhile to develop a formula for computing the Square-Error (ISE) of MMPC for PEB process The formula will be useful inevaluating the effect of MMPC tuning parameters and its updating patterns,which will finally affect the CD uniformity

Integral-Multiplexed MPC with different sampling intervals have been demonstratedexperimentally on a multi-zone bake-plate application Shorter sampling time canresult in faster recovery of bake plate temperature when a cold wafer is placed

on the bake plate This result is important for the MMPC design Experimentalresults and theoretical results were matched and hence before hardware imple-mentation, design can be performed with the aid of theory The ISE formulaenables one to select a suitable sampling interval, or other design choices for the

MMPC, such as MPC control horizon N u , MPC controller tuning parameters Q,

R.

evaluation of MMPC computational load carried out on a multi-zone thermalsystem The derivation and Verification of MMPC ISE formula for PEB processare presented in Chapter 4 Chapter 5 summarizes the research works and givesrecommendations for future works.

con-of the current wafer or batch, the approach here is real-time and make use con-of rent information for control of the CD of the current wafer In this Chapter it

cur-is demonstrated that real-time control of the post-exposure bake temperature togive nonuniform temperature distribution across the warped wafer can reduce CDnonuniformity across the wafer

the photolithography sequence Temperature uniformity control is an importantissue with stringent specifications and has a significant impact on the CD [37]–[39].The most temperature sensitive step in the photolithography sequence is the post-exposure bake step As the photolithography industry moves to bigger substrateand smaller CD, the stringent requirements for post-exposure bake processing stillpersists [23] For commercially available deep ultraviolet resist, a representativepost-exposure bake latitude for CD variation is 8 nm/◦C [11]–[12] A number ofrecent investigations also showed the importance of proper bake-plate operation

on CD control [19, 39, 40]

Thermal processing of semiconductor wafers is commonly performed by ing the substrate on a heated bake-plate for a given period of time The heatedbake-plate is usually held at a constant temperature by a feedback controller thatadjusted the heater power in response to a temperature sensor embedded in thebake-plate near the surface The wafers are usually placed on proximity pins of

plac-the order of 100 µm to create an air-gap to minimize contamination.

When a flat wafer at room temperature is placed on the bake-plate, the

temperature of the bake-plate drops at first but recovers gradually because ofclosed-loop control as shown in Figure 2.1(a) One challenge for thermal process-ing of wafers in photolithography is the warpage [41] Figure 2.2(a) shows the

bake-plate temperature when a wafer warped 140µm center-to-edge was placed

on the bake-plate By comparing Figures 2.1(a) and 2.2(a), it can be seen that

a flat and warped wafer gave rise to different magnitudes of bake-plate ature drops due to different air-gap sizes and hence different thermal resistancesbetween the substrates and bake-plate Figure 2.4 shows a flat and warped wafer

temper-on the bake-plate Compared with the flat wafer, because the air-gap betweenthe warped wafer and bake-plate are bigger (smaller), the maximum temperaturedrop at the bake-plate are smaller (bigger) Furthermore, we expect the warpedwafer to be heated to a lower (higher) temperature than the flat wafer Finally,because of nonuniform processing condition, CD across the warped wafer is notexpected to be uniform

It was demonstrated in [42]–[43] that the air-gap size can be estimated fromthe maximum drop in bake-plate temperature through their inverse relationship

It was further demonstrated in [43] that using the heat transfer model of thebaking system and the estimated air-gap, we can calculate the bake-plate tem-perature to give uniform temperatures across the warped wafer In this chapter weextend the results by demonstrating that real-time control of the post-exposurebake temperature to give nonuniform temperature distribution across the warped

Figure 2.3: The bake-plate used in the experiment.

wafer can reduce CD nonuniformity The proposed solution is to adjust the plate temperature setpoints on-line and in real-time once warpage is detected.Warpage can differ from wafer to wafer and hence not expected to be repeatable

bake-If warpage was repeatable then we could have fixed the bake-plate setpoints

The distributed thermal processing system used in this work is shown in ure 2.3 It consisted of two heating zones, center and edge as shown in Figure2.4 Embedded within each of the heating zones were resistive heating elementsand temperature sensors The zones were separated by a small air-gap of approx-imately 1 mm for thermal insulation

Fig-Spatial distributions of temperature and other quantities in a silicon wafer

in shape with the same diameter as the wafer Energy balances on the wafer andbake-plate can be carried out to obtain a two dimensional model as follows.

where subscripts p, w, a, 1 and 2 denote bake-plate, wafer, air-gap, center zone

and edge zone respectively Temperature above ambient, thermal capacitance

and resistance are given by T , C and R respectively Thermophysical properties

of silicon and air can be obtained from handbooks [44] as tabulated in Table 2.1

Table 2.2: Thermal Capacitances and Resistances.

A control software system was developed using the National InstrumentsLabView programming environment [45] Two proportional-integral controllers

of the following form were used to control the two zones of the bake-plate.

where u1(t), u2(t) are the control powers and T p1 (∞), T p2 (∞) are the

bake-plate temperature setpoints The proportional-integral controller parameters for

the center and edge zones were manually tuned as K c1 = 5.15, T I1 = 150 and

T p1 (∞) = R a1

µ1

The thermal modelling is based on energy balance and when there is noinput power the steady state bake plate temperature is the ambient temperature,instead of zero.

2.3.1 Setup

In all our experiments, commercial chemical amplified resist, Shipley UV3 wasspin-coated at 6000 revolutions per minute on a 4-inch wafer After a post-applybake, the wafer went through an exposure tool with a patterned mask of regularlyspaced lines The exposed photoresist was then baked, developed and the finaloutput was the linewidth of the photoresist pattern or CD Except for the real-time on-line adjustment of the post-exposure bake temperature, all other inputs

to the photolithography processes such as spin speed, baking time, exposure dose,develop time etc were kept constant No anti-reflection coating was used Thepost-exposure bake-time was fixed at 90s

The experimental setup for the post-exposure bake of a warped wafer is shown

in Figure 2.4 We ensured a fixed warpage during the baking experiment by

mechanically pressing the edges of the wafer against the proximity pins of 70µm.

The center-to-edge warpage was given by the difference between the height ofproximity pin and thermal tape thickness

2.3.2 Runs

Twelve Experiment (Wafer) Runs were performed On each wafer we monitored

CD at 2 points, 1.5 inches apart, one near the center, the other near the edge ofthe wafer At each point, three samples of linewidths were measured by scanningelectron microscope to give the average CD Results are shown in Figure 2.5 Theresults for Runs 1, 4, 7, 10 are tabulated in Table 2.3 for further discussion Theother runs were repeat experiments Wafers 1–3 and 7–9 were flat while 4–6 and

10–12 were warped 140µm center-to-edge.

Because photoresist was coated on the patterned wafer, it was not convenient

to attach temperature sensors on the wafer to measure wafer temperature To

do so, another set of experiments with the same wafer warpage and bake-platesetpoints were conducted There was no pattern or photoresist on these wafersand their sole purpose was for us to obtain the wafer temperatures ResistanceTemperature Detectors (RTD) were attached to the wafers [21, 46] for tempera-ture measurements Thermal grease was applied to the RTD sensors for better

1 2 3 4 5 6 7 8 9 10 11 12 350

heat transfer The measured wafer temperatures are included in the last row ofTable 2.3 and in the column that corresponded to the warpage and bake-platesetpoints Figure 2.6 shows the measured wafer temperature for a warped wafer.

The wafer was baked for 90s starting from t = 10s.

The bake-plate temperature curve for Flat Wafer 1 is shown in Figure 2.1.Notice in Table 2.3 that for Flat Wafer 1 even though the wafer temperature at

center (128.1 ◦ C) and edge (128.0 ◦C) were approximately equal CD mity was 23nm This can be expected as properties at center and edge may not bethe same e.g the thickness of the coat of photoresist across the wafer is known to

nonunifor-be nonuniform [47]–[48] Nonuniform photoresist thickness can cause nonuniform

CD through a swing curve effect [49]–[51] In [43] the bake-plate temperatureswere controlled to give uniform temperatures on the wafer We demonstratedhere that this is not good enough to give uniform CD Nonuniform temperaturedistribution across the wafer may be required to obtain uniform CD at centerand edge

The bake-plate temperature curve for Warped Wafer 4 is shown in Figure 2.2

Table 2.3 shows that the wafer center temperature (125.4 ◦C) was lower than edge

(126.9 ◦C) and the CD nonuniformity doubled to 46 nm

There are different sources of CD variations, such as non-uniform photoresistthickness The temperature of bake-plate will affect photoresist thickness andeventually affect the output of CD With the assumption that CD results is

a certain degree of repeatability of the CD profile and hence the two-zone plate should start baking at different temperatures for different zones Once anew set of bake-plate setpoints (130.3◦C and 128.5◦C) was implemented as shown

bake-in Figure 2.7, the CD non-uniformity on the Flat Wafer 7 was reduced to 1 nm asshown in Table 2.3 Notice that for CD uniformity, wafer temperature at center(128.2◦C) was higher than edge (126.6◦C)

temperature drops in T p1 and T p2 for 20µm ≤ l a1 ≤ 300µm and 20µm ≤ l a2 ≤

300µm and the results are plotted in Figures 2.8 and 2.9 for l a1 and l a2respectively

could have fixed but different bake-plate setpoints for center and edge.

For processing of Warp Wafer 10, the maximum temperature drop of 1.54◦Cand 1.70◦C center and edge respectively were first measured A search through

Figures 2.8 and 2.9 gave l a1 = 184µm and l a2 = 110µm Substitute into R a1,

R a2 and with the desired wafer temperatures of T w1 (∞) + T a = 128.2 ◦C and

T w2 (∞) + T a = 126.6 ◦ C, (2.7) to (2.8) gave the new setpoints of T p1 (∞) + T a =

133.6 ◦ C and T p2 (∞) + T a = 129.6 ◦C Notice in Figure 2.10 the bake-plate points were changed from 130◦C to 133.6◦C and 128.5◦C to 129.6◦ C at t = 24s,

set-immediately after the maximum bake-plate temperature drops had occurred CDnon-uniformity of 1 nm and wafer temperatures of 128.2◦C (center) and 126.6◦C

(edge) were obtained, just like Flat Wafer 7 Note that l a1 −l a2 = 74µm 6= 140µm the center-to-edge warpage of Wafer 10 because l a1 and l a2 were not the air-gaps

at the wafer center and extreme edge but the average over the center-zone andedge-zone

3 2.5

2 1.5

1 3

2 1

center zone maximum drop (Deg C)

edge zone maximum drop (Deg C)

Figure 2.8: Center-zone average air-gap versus bake-plate maximum temperaturedrops