Integrated metrology and real time CD control

As CD is very sensitive to wafer temperature during thermal processing steps in lithography, it is important to control the wafer spatial temperature uniformityfor enhancing CD uniformit

REAL-TIME CD UNIFORMITY CONTROL

NGO YIT SUNG

(B.Eng.(Hons.),UTM)

A THESIS SUBMITTEDFOR THE DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND COMPUTER

ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE

2012

I would also like to express my deepest gratitude to Professor Ng Tuck Wahfor his insightful advices and instructions in the optical sensor development I

am also extremely thankful to my examiners, Professor Prahlad Vadakkepat andProfessor Tan Kay Chen for their advices and guidance during my QualifyingExams Dr Andi S Putra has put in tremendous effort to set up the clean room

in our laboratory and contributed in the development phase of the optical sensor.Our laboratory technologist, Mainavathi has provided unconditional support inour research to make it a success

In my daily work I have been blessed with a friendly and cheerful group offellow students and colleagues: Dr Wang Yuheng, Dr Zhao Shao, Dr KiewChoon Meng, Dr Teh Siew Hong, Mr Ang Kar Tien, Mr Yang Geng, Dr Yan

and many others working in the Advanced Control Technology (ACT) Laboratory.Thank you for your friendship and encouragement along the way Many thanks

to all whom I have unintentionally left out, but contributed in making this thesis

a successful and memorable journey

I thank my parents and sisters for supporting my decision to pursue my passion

in research And last but not least, thanks to my wife, Chiew Mei for her company,love and patience It is her consistent motivation which expedited the completion

of this thesis

Ngo Yit SungJanuary, 2012

ii

1.1 Motivation 1

1.1.1 Process Control 7

1.1.2 Equipment Design 10

1.1.3 Integrated Metrology 14

1.2 Contributions 16

1.2.1 Design and Implementation of Programmable Integrated Bake-Chill System 17

1.2.2 Design and Implementation of Scatterometry in CD Moni-toring 18

1.2.3 Real-time CD Monitoring and Control 20

1.3 Organisation of the Thesis 20

Chapter 2 Programmable Integrated Bake-Chill System 22

2.1 Introduction 22

2.2 Proposed Integrated Bake-Chill System 25

2.3 Thermal Modeling of the System 27

2.3.1 Heat Transfer in Wafer 28

2.3.2 Thermoelectric Devices Modeling 29

2.3.3 Heat Sink Design 32

2.3.4 Open Loop Model Validation 34

2.4 Model-Based Controller 39

2.5 Experimental Results 42

2.6 Conclusion 45

Chapter 3 Metrology for Patterned Thin Film 46 3.1 Introduction 46

3.2 Proposed Rotating Polarizer Spectroscopic Ellipsometer 48

3.3 Principles in Ellipsometry 50

3.4 Instrument Parameter Characterization 53

3.4.1 Determination of Polarizer and Analyzer Axes 53

3.4.2 Residual-Function and Phase-Function Calibration 55

3.4.3 The Effect of Azimuth Angle 57

3.4.4 Tilt and Translation Adjustment 61

3.5 Conclusion 65

Chapter 4 Real Time Photoresist Monitoring and Control 66 4.1 Introduction 66

4.2 Basic Mechanism of Positive CAR 68

4.2.1 Exposure Reaction 69

4.2.2 Amplification Reaction 70

4.2.3 De-protection Induced Thickness Loss and Transmittance Change 72

4.3 DUV Chemically Amplified Resist Characterization 74

4.3.1 Experimental Setup 74

4.3.2 Sample Preparation 77

4.3.3 DUV Chemically Amplified Resist Characterization 77

4.4 PEB Control Scheme 87

4.5 Results and Discussions 90

4.6 Conclusion 97

Chapter 5 Conclusion 98 5.1 Summary 98

5.2 Future Work 101

Lithography is the key technology driver in semiconductor manufacturing Inoptical lithography, the most important variable to be controlled is critical dimen-sion (CD) uniformity As feature size miniaturization goes beyond the sub-microntechnology node, the prevalence of optical lithography is only possible with state-

of-the-art process equipment, in-situ metrology and efficient process control This

thesis presents a framework for lithography process monitoring and control whichencompasses the development of an actuator, sensor and control methodology forpost-exposure bake (PEB) in deep ultraviolet (DUV) lithography

As CD is very sensitive to wafer temperature during thermal processing steps

in lithography, it is important to control the wafer spatial temperature uniformityfor enhancing CD uniformity A new programmable integrated bake-chill thermalprocessing module is designed and implemented to overcome limitations posed

by conventional thermal processing module By employing a set of thermoelectricdevices (TEDs), resistance temperature detectors (RTDs) and model-based controlmethod, the spatial wafer temperature non-uniformity can be well-controlled to

within ±0.4 ◦ C and ±0.1 ◦C during the transient and steady-state period of thermal

cycle respectively.

Metrology wise, a fixed angle scatterometer based on specular spectroscopic

scatterometry is developed as an in-situ metrology system for patterned resist film

monitoring during PEB The rotating-polarizer configuration is adopted so thatthe detector does not need to be insensitive to polarization and parasitic light issuppressed Calibration for sources of systematic errors is proposed The effective

spectral range recognized by the system ranged between 350nm to 850nm and

measurement time during spectroscopic mode is 5 times faster than commercialellipsometers which is critical for real-time monitoring and control

The scatterometer is integrated with a multi-zone bake-plate to form the vanced process control (APC) framework for PEB Characterization on targetedDUV resist is performed to determine the temporal range for control during PEB

ad-A control scheme based on merit function to match the measured and referencespectrums is proposed for real-time monitoring and control Result shows CD

non-uniformity can be significantly reduced to less than 10nm With this system,

real-time monitoring and control for CD uniformity is achieved, control resolution

is further reduced from run-to-run control to across-wafer control

List of Figures

1.1 Intel’s Pentium processor evolution 31.2 A typical sequence of lithographic processing steps, illustrated for

a positive resist 41.3 Thermal processing steps in lithography 112.1 The conventional approach for lithography baking and chilling pro-cess involves substrate transfer between large thermal mass, fixedtemperature plates 232.2 Schematic diagram of the integrated bake/chill design (A) schematicdrawing of the system, (B) plan view of the heat sink (Note: Fig-ures are not drawn to scale) 262.3 Experimental setup 272.4 Schematic of a thermoelectric device (TED).(Note: Figures are notdrawn to scale) 302.5 Arrangement of TEDs in pseudo-circular pattern and location ofRTD sensors for open loop experiment.(Note: Figures are not drawn

to scale) 36

2.6 Comparison of experimental and simulated TED temperatures in aheating and cooling cycle (A) Experimental and simulated TEDtemperature response (B)TED temperature difference between ex-periment and simulation result (C)Input currents during the heat-ing and cooling phase 372.7 Comparison of experimental and simulated wafer at different inputsignals (A) Experimental and simulated wafer temperature re-sponse (B)Wafer temperature difference between experiment andsimulation result (C)Input currents during the process 382.8 Comparison of experimental and simulated wafer temperatures over

10 consecutive cycles (A) Experimental and simulated TED perature response (B)Experimental and simulated heat sink tem-perature over 10 cycles (C)Input currents during the process 392.9 Block diagram of the proposed model based control scheme 402.10 Location of temperature sensors for the integrated bake-chill exper-iment R1 and R5 are used as feedback variables 432.11 Experimental wafer temperature along the wafer radius with thetemperatures of sensors R1 and R5 being treated as feedback vari-ables using model based control method (A) wafer temperatureresponse at the five points during the whole thermal cycle, (B) tem-perature difference between the two feedback points on the wafer

tem-in the process, (C) mean removed wafer temperature of the fivepoints, (D) control current inputs of TEDs during the thermal cycle 44

3.1 Schematic of proposed rotating polarizer spectroscopic ellipsometer 48

3.2 (a) Linearly polarized light (b)Elliptically polarized light 50

3.3 Light intensity recorded for fixed polarizer axis at 0◦ and presumed analyzer axis at 0◦, 30◦, 60◦, 90◦, 120◦, and 150◦ 55

3.4 Residual-function and phase-function calibration to determine A s and P s at 840nm 57

3.5 Incident light with same angle of incidence and symmetric azimuth angle: (a)φ; (b)-φ 58

3.6 Grating specifications 58

3.7 log(tan Ψ) and cos ∆ profiles for grating 600gr/mm for 360o 59

3.8 log(tan Ψ) and cos ∆ at 600nm for different azimuth angle 60

3.9 GOF versus azimuth angle 61

3.10 Sample positioning adjustments for an ellipsometer 62

3.11 log(tan Ψ) and cos ∆ profiles with tilting and translation error 63

3.12 log(tan Ψ) and cos ∆ profiles after tilting and translation adjustment 64 4.1 Integrated wafer thermal processing system 74

4.2 (a)Top view and (b)Schematic of the distributed multi-zone thermal processing system with cartridge heater 76

4.3 log(tan Ψ) and cos ∆ profiles for fully exposed resist film 79

4.4 log(tan Ψ) and cos ∆ profiles for unexposed resist film 80

4.5 log(tan Ψ) and cos ∆ profiles for patterned resist film 81

4.6 Patterned resist surface after PEB 82

4.7 Comparison of log(tan Ψ) and cos ∆ profiles for patterned resist filmafter PEB (200nm line grating vs 500nm line grating) 834.8 log(tan Ψ) and cos ∆ profiles at 130◦ C for 630s (40 consecutive mea-

surements) The signature plot gradually shifts from right to leftthroughout the baking process as indicated by the arrow 844.9 Optical property changes detected by the ellipsometer at differentincident wavelengths across time 854.10 log(tan Ψ) and cos ∆ profiles measured from 50◦C to 200◦C Thesignature plot gradually shifts from right to left throughout thebaking process as indicated by the arrow 864.11 Optical property changes detected by the ellipsometer at differentincident wavelengths across temperature 874.12 Resist thickness variation after PEB 884.13 Advanced process control (APC) architecture of the integrated real-time CD monitoring and control system 894.14 Comparison between controlled response with respect to referencefor log(tan Ψ) and cos ∆ spectrums 914.15 Comparison between controlled and uncontrolled response for log(tan Ψ)and cos ∆ spectrums 934.16 SEM results for (a)reference wafer, (b)controlled wafer and (c)uncontrolledwafer 944.17 Repeatability analysis for log(tan Ψ) and cos ∆ spectrums 965.1 Schematic of the proposed dual-zone scatterometry system 103

List of Tables

1.1 Lithography technology requirements 122.1 Physical parameters of integrated bake-chill thermal models 352.2 Sum of squared errors for Figure 2.6 and 2.7 between the experi-mental and simulation results 39

4.1 Changes in MSE log(tanΨ) , MSE cos∆ , e and T new during one PEB

cycle (K = 2000) 92

4.2 Average CDs of the samples 95

increasing circuit density means adding more features on a given chip area Thelatter involves shrinkage of the transistor’s dimension in terms of transistor gatelength, width and the oxide thickness [3] When these parameters are scaled with

a factor of 0.7 per node, the gate capacitance is reduced by a factor of 0.7 while thetransistor channel resistance remains unchanged and thus, the resistive-capacitive(RC) delay of the transistor is scaled down by the same factor [4]

Today, semiconductor manufacturing or IC fabrications begins with the waferand involves more than a thousand steps of fabrication processes to produce pack-aged and integrated electric components [5] The fundamental to the complexfabrication process is lithography The word ”lithography” originated from the

Greek lithos, which means stones, and graphia, which means to write Literally,

lithography means to write on stones In the case of semiconductor ing, lithography is the formation of three-dimensional (3D) relief images on thesubstrate for subsequent transfer of the pattern into the substrate where the siliconwafer is the stone while the patterns are written with a light-sensitive chemicalcompound called photoresist Since the birth of semiconductor manufacturing,optical lithography has been the preferred technique for mass fabrication of inte-grated circuits Despite inevitably being obsolete once the physical limits of the

manufactur-micron are crossed, it is still the mainstay for mass production for 32nm due to

its ability to meet requirements such as resolution and high productivity

The prominence of lithography can be appreciated in two ways [6]: First, due

to the large number of lithography steps needed in IC manufacturing, phy typically accounts for about 30% of the cost of manufacturing a chip Let’stake a look at Intel’s Pentium processor evolution as an example as shown in

lithogra-Figure 1.1 [7].

Figure 1.1: Intel’s Pentium processor evolution

With the downscaling of technology node in semiconductor manufacturing,the number of transistors per chip increased exponentially, which is in line withMoore’s Law which states that the number of components per IC doubles everymonth Conversely, the circuit area is shrinking by the day Due to the com-plexity of the circuitries, more interconnectivity is required As such, the number

of lithography sequence for a particular chip rose as the mask layers increased.Based on the worldwide semiconductor revenue forecast of $304 billion in 2010from market research firm iSuppli (now part of IHS Inc) and an average grossprofit margin for the sector of approximately 40%, a hefty $55 billion is spent

on lithography alone Second, lithography tends to be the technical limiter forfurther advances in transistor size reduction and thus chip performance and area.Due to the ever increasing demand from the consumer market for more compact,

high performance, greater functionality yet cheaper devices, global semiconductormanufacturers are always on the verge to squeeze more transistors in lesser area

on the wafer Of all the processing steps, lithography is the key technology driverfor the semiconductor industry Although there are other technical challenges inthe IC manufacturing flow other than lithography, we should bear in mind thatadvances in lithography have gated advances in IC cost and performance in thepast [8]

The general sequence of a typical optical lithography process is as follows [9]:Substrate preparation, photoresist spin coat, post-apply bake (PAB), exposure,post-exposure bake (PEB), development, etch/implant and resist strip Metrologyand inspection followed by resist strip are the final operations in the lithographicprocess, after the resist pattern has been transferred into the underlying layer.This sequence is shown diagrammatically in Figure 1.2

Figure 1.2: A typical sequence of lithographic processing steps, illustrated for apositive resist

Substrate preparation is intended to clean the wafer surface and to improvethe adhesion of photoresist to the substrate This is accomplished by substratecleaning, dehydration bake to remove moisture and addition of adhesion promoter.The wafer is then coated with photoresist via spin coating where puddle of liq-uid resist is deposited on the center of the wafer and is spun off by centrifugalforces to produce leveled resist film across the wafer Next, the wafer will besubjected to post-apply bake (soft bake or prebake) prior to exposure to removethe solvent without degradation of the resist components By removing excesssolvent in the photoresist, the thin film of resist becomes stable in room temper-ature, adhesion of the resist is improved, and the film become less tacky and thusless susceptible to particulate contamination After exposure, the wafer will besubjected to post-exposure bake (PEB) which primarily is aimed to promote dif-fusion to remove standing waves induced during exposure [10] For another class

of photoresist used in deep ultraviolet (DUV) lithography which is called chemicalamplified resist (CAR), PEB kicks start the chemical reactions to create a solubil-ity differential between exposed and unexposed parts of the resist [11] The wafer

is then subjected to development where the soluble resist will be washed awayusing developers, leaving circuit patterns which will be transfer onto the substratevia etching, selective deposition and ion implantation And finally, the residualphotoresist must be removed via resist stripping Resist patterns which form thecritical features are then inspected and measured to determine their dimensions,which is known as critical dimensions (CD)

Understanding the vital role of optical lithography in current and future ICfabrication and its feasibility to scale down integrated circuits in a cost-effective

way, advances in optical lithography must continue and it is appropriate to vice solutions to undertake the challenges and to optimize the interim solutionscurrently available It is apparent that each process in a lithography sequencerequires the aid of sophisticated equipment and each step has the possibility toinduce some kind of error or defect and therefore stringent process monitoring andcontrol along the line is required for real-time fault detection and correction Thisstudy is aimed to explore three major elements within the lithographic process tofurther enhance its performance: process control, process equipment design andprocess monitoring.

de-We limit our scope of research to deep ultraviolet (DUV) lithography which

is utilizing the chemically amplified resist (CAR) Near UV lithography using thenovolak resist, electron beam lithography, X-ray lithography, extreme ultraviolet(EUV) lithography, ion projection lithography and immersion lithography will not

be considered in this study And due to the extensive use of thermal processingsteps in a typical lithographic sequence and their dominance in affecting the end

CD profile, we will focus our effort on devising a solution to optimize the thermalprocesses Among the thermal processing steps in DUV lithography, post-exposurebake (PEB) will be the central of this research due to its prominence in CDformation Nevertheless, it should be noted that the proposed system can beproliferated to other lithography thermal processes as well without much effort.The discussion on the metrology technique in this thesis will be primarily focused

on ellipsometry

1.1.1 Process Control

Similar to any production facilities in the world, semiconductor manufacturersare driven by cost and productivity needs irrespective of technology nodes Semi-conductor device fabrication involves a series of precise chemical and mechanicalprocesses and like any other processes, they are subjected to process drift If theprocess drifts beyond the prescribed specification limits (process window), it willcompromise the reliability of the devices More devices will be screened out duringwafer sort test (wafer level) and production final test (package level) which willlower device yield, resulting in higher cost per unit If not caught during test,devices with potential reliability issue due to poor process control tend to havelower life span or tend to fail early, which will be rejected and returned for failureanalysis This will incur extra engineering time and cost Therefore, it is essential

to maintain the processes within the specification limits, thus process control isrequired

Historically, semiconductor manufacturing has relied on statistical process trol (SPC) to maintain fabrication processes within the process window As thename has it, SPC involves using statistical techniques to measure and analyze thevariation in processes Conventionally, the machinery or the equipment will be cal-ibrated using a monitor wafer (some called it golden wafer) Once calibrated, theequipment is assumed to perform its task without any deviation, which is not thecase in reality During production, data will be collected lot by lot The data col-lected will be translated into statistical charts and analyzed by process engineers

con-or technicians fcon-or next course of action befcon-ore subsequent wafer lot is subjected

through the same process Production runs continuously as long as the processdrift fluctuates within the process window But when there is an excursion, thefault can only be detected after a wafer lot has been processed The equipmentwill be shut down for inspection and repair while the affected wafer lot will bereworked or scrapped depending on the severity of the damage As semiconductorproducts are manufactured in high volume, the repair of finished semiconductorproducts and longer production down time is impractical and costly.

The limitation with conventional process control is its passivity, based on theprinciple that the process parameters are held invariant over long periods of time.Process drifts beyond specification limits are not detected real-time and error willonly be flagged when the monitored parameters exceed the limits with specifiedstatistical significance And although the fault is detected with in-situ sensors,current equipment does not have the mechanism to react immediately to bringthe parameters back to nominal value Apart from lot-to-lot or wafer-to-wafervariation, process deviation also happens during processing of a single wafer wherevariations occur across one single wafer For example, the resist film thickness atthe edge of the wafer maybe thinner than film thickness at the center of wafer.All these trends call for active control where defects are detected within a shortertimeframe during processing of every wafer and process parameters are adjustedimmediately to reverse the fault

The International Technology Roadmap of Semiconductor (ITRS) calls for tory level and companywide metrology integration for real time in-situ, integratedand inline metrology tools [12] In the ITRS 2010 report [12], metrology is defined

fac-as mefac-asurements that are done in situ, in-line, and off-line Off-line metrology

refers to measurement done outside of the cleanroom In-line metrology refers tomeasurement and process control done inside the cleanroom In situ metrologyrefers to measurements and process control done using sensors placed inside pro-cess chamber Advanced equipment control (AEC) and advanced process control(APC) have been considered the ultimate goal of semiconductor manufacturing asdevice geometries shrink below 250nm These approaches are the current paradigmthat attempt to solve three specific problems [13]:

1 Processing anomalies be determined by examining a much wider domain ofparameters

2 Processing anomalies be detected in shorter timeframes, within wafer or atleast wafer to wafer

3 Processing emphasis be focused on decreasing the variance of the wafer-stateparameters instead of controlling the variance of the setpoints

Fault detection and classification (FDC) component addresses the first two quirements, and model-based process control (MBPC) addresses the last one Incontrast to the conventional statistical process control (SPC) approach, APC andAEC is a closed-loop, interactive method where the processing of every wafer isclosely monitored in a time scale that is much more relevant to the manufacturingprocess When a problem is detected, the controller can determine whether toadjust the process parameters or to stop the misprocessing of subsequent wafers

re-In short, the key premise of this approach is the goal of real-time process control.AEC and APC require complex, flexible architecture to be in place to executethe approach, cutting-edge equipment, and state-of-the-art integrated sensory sys-

tem Currently lithography process is monitored before photoresist spin on andafter development This only provides a measurement of cumulative effects of allthe upstream process steps To isolate the effect of each process step, monitor-ing at each step is necessary This need for wafer process monitoring requiresin-line sensors and real-time algorithms to facilitate real-time analysis of sensorsignals [14] Therefore, in order to implement real-time CD monitoring and con-trol effectively, we need more advanced hardware and software For photoresistthermal processing in lithography, we have identified the need to integrate anoptical sensor employing scatterometry technique for real-time CD monitoring.The data from the sensor will be analyzed and translated into CD information.The CD information will be compared with the desired CD profile and based onthe CD error, a control signal will be generated and fed immediately back to the

bake-plate to control the thermal processing of photoresist Other than in-situ

sen-sor, we have also identified limitations of existing bake-plate module and devise anew multi-zone bake-chill system which is able to overcome the shortcomings andsignificantly enhance across-wafer CD uniformity

1.1.2 Equipment Design

The DUV lithographic sequence entails numerous thermal processes as shown inFigure 1.3 The formation of the latent image on the CAR is primarily due tochemical reactions which change the solubility of the resist Nevertheless, theunderlying factor is that these chemical reactions are typically temperature de-pendent, which strongly emphasize the importance and the need of a controlledbaking process to be in place Thermal processing of photoresist can dramatically

influence resist performance in a number of ways Post apply bake (PAB) or softbake will remove excess solvent in the resist to reduce the diffusivity of exposureproduct and thus stabilize the resist film at room temperature while post-exposurebake (PEB) reduces standing wave ridges on the resist sidewall significantly due

to the diffusion of sensitizer which acts as a dissolution inhibitor for conventionalresist

Figure 1.3: Thermal processing steps in lithography

For DUV lithography, the chemically amplified resist (CAR) requires two arate chemical reactions in order to change the solubility of the resist [15] First,exposure turns an aerial image into a latent image of exposure reaction prod-ucts which do not appreciably change the solubility of the resist The secondreaction is catalyzed by the exposure reaction product during post-exposure bakewhich eventually leads to change in the solubility of the resist Therefore, PEB is

sep-Table 1.1: Lithography technology requirements

considered as one of the most critical steps in DUV lithography as PEB ature variation directly affects CDs of final resist patterns [16] and resist pattern

temCD uniformity improvement through PEB control can contribute to device formance improvement [17] The importance of excellent process control duringPEB becomes more significant as pattern size decreases for higher density devicebecause CD variation due to PEB sensitivity can be more than 10% of the tar-geted CD [18] Apart from having an impact in the CD formation within PEB,recent investigation by Zhang et al [19] reveals that PEB is able to compensateupstream and downstream systematic CD variation components in the litho-etchprocess sequence They also reported that CD variation reduction of 40% can berealized by employing advanced thermal processing system and control method

per-in PEB step Accordper-ing to ITRS [12], the post-exposure bake resist sensitivity

to temperature will be more stringent for each new lithography generation as picted in Table 1.1 By the year 2013, the post-exposure bake resist sensitivity

de-is expected to be 1nm/◦C, making temperature control even more critical Theconventional wafer baking module has two weaknesses in general in terms of acrosswafer temperature control and hardware characteristic

Traditionally, the PEB step is conducted by transferring the wafer onto a hot,high-mass metal plate (hot-plate) where it is baked at a temperature typicallybetween 70◦C to 150◦C for a time period between 60s and 90s Due to high

thermal conductivity of the silicon substrate, the photoresist is heated to near thehot-plate temperature quickly The heated wafer is then mechanically transferred

to a chill-plate where it is cooled to a temperature between 18◦C to 30◦C [20] Evenwith state-of-the-art wafer tracks, the across-wafer PEB temperature range can be

as much as 9◦C during the heating and cooling transient and 0.7◦C during state [21] Numerous works to improve the PEB cycle has been done [22, 23, 24, 25]and better perfomance is achieved Nonetheless, it is very difficult to achieve gooduniformity, especially during the heating and cooling transient phase due to thelack of temperature control during wafer transport

steady-The conventional bake plate is usually thermally massive and is maintained

at a constant temperature by a feedback controller Because of its large thermalmass and sluggish dynamics, conventional hot-plates are robust to large temper-ature fluctuations and loading effects, and demonstrate good long-term stability.These advantages however become shortcomings in terms of process control andachievable performance when tight tolerances must be maintained Although ad-vanced control schemes can be used to improve performance [26, 27, 28, 29], it hasbeen shown that the conventional hot-plate design has poor controllability [30] due

to its inherent sluggish dynamic response and that ultimately limits the achievableperformance Other disadvantages include uncontrolled and non-uniform temper-ature fluctuation during the mechanical transfer of the substrates from the bakeplate to chill plate, and spatial temperature non-uniformities during the entirethermal cycle [31, 32]

In summary, the lack of a real-time, distributed and closed-loop temperaturecontrol method in the conventional hot plate is a source of process error in the

lithography chain Our objective is to design a new thermal processing system toachieve rapid dynamic temperature response and minimize the temperature non-uniformity during the transfer from heating to cooling process by real-time wafertemperature control method.

1.1.3 Integrated Metrology

To maintain good process yield and improve device performance, wafer fabs haveimproved control over process parameters and reduced source of defects duringfabrication These improvements could not have occurred without the ability tomeasure wafers and evaluate process performance This evaluation is done usingadvanced measurement equipment that provides production data about the waferfabrication performance, giving key information to the engineer and technicianfor decision making Wafer process inspection technology has undergone dramaticchanges as feature sizes continue to shrink New metrology techniques are re-quired with the jump from 45nm to 32nm, because the existing way of checkingfor faults on chips may not be sufficient to accommodate stringent measurementrequirements at this new level

According to ITRS [12], the next generation lithographic technology requiresadvances in the area of metrology equipment for critical dimension measurement.Typical process tolerances for linewidths are specified at 10% of the nominal width,but metrology tools must be capable of measurement precision even smaller thanthis As a general rule of thumb, the semiconductor industry would like metrologyprecision, or the repeatability of a given measurement, to be 10% of the tolerance,

or 1% of the nominal linewidth The measurement precision requirement on a

0.18um device, then, is a mere 1.8nm Measurement precision is just one facet ofthe metrology problem Metrology measurements must also be accurate, in thesense that the information they provide truthfully reflects the actual dimensions

of the device being measured [13]

Bearing all this considerations in mind, the perfect metrology, then, is one that

is capable of meeting or exceeding industry standards for measurement precisionwhile being versatile enough to measure several different process parameters Forin-line applications, it should also be able to perform these measurements unobtru-sively, non-destructive and with high throughput Finally, of course, this perfectmetrology should be cheap

Scatterometry is an ideal candidate for in-situ CD monitoring which fulfillsmany of these needs and thereby offers advantages over existing metrologies such

as critical dimension-scanning electron microscopy (CD-SEM) and atomic forcemicroscopy (AFM) The optical instrument can be fabricated small enough tofit in the space of the bake module on a wafer track, enabling a true run-to-run metrology scheme Furthermore, the quality (full profile versus top-townview) and quantity (accuracy, precision, and throughput) of the collected dataunderscore its clear advantage for inline application [33] Moreover, this singlesensory system can be employed in different wafer fabrication process steps such

as etching [34], exposure dose and focus [35, 36] and overlay [37, 38] Hence, theuse of scatterometry in semiconductor metrology has been widely reported sincethe 1990s and it has played a ubiquitous role for more than two decades

Scatterometry can be defined as the measurement and characterization of thediffracted light from periodic structures Due to complex interactions between the

incident light and the material itself, the fraction of incident power diffracted intoany order is sensitive to the shape and dimensions of the diffracting structure andmay be used to characterize that structure itself [39] Other than the period ofthe structure, thickness of the photoresist, the width of the resist line, and thethickness of several underlying film layers can also be measured by analyzing thescatter pattern The scatterometric analysis can be divided into two parts Thefirst part is known as the Forward Problem where the diffracted light is measuredusing a scatterometer The second part is the Inverse Problem where the periodicstructure is determined using the scatter signature.

In the Forward Problem, a variety of scatterometer configurations has beenexplored and published in literature and can be broadly categorized into threeconfigurations: fixed-angle scatterometers [40, 41, 42], variable-angle scatterom-eters [43, 44, 45], and dome scatterometers [46] As for the Inverse Problem,there are several approaches to obtain the grating parameters from the scattersignature, each with its own merits These solutions, again, can be classified intothree groups: Theoretical Models, Empirical Models, and Model Regression versusLibrary Search

Our objective is to develop an optical sensor based on spectrosocpic

ellipsom-etry which is non-destructive with high-throughput which can be used for in-situ

monitoring of patterned resist film during PEB

In this thesis, advanced process control, equipment design and metrology issuesduring the thermal processing steps in lithography are addressed This thesis

contributions are summarized as follows.

1.2.1 Design and Implementation of Programmable

Inte-grated Bake-Chill System

The real-time spatial wafer temperature control method provides an effective way

to improve wafer transient temperature uniformity However, the achievable formance gain is ultimately limited by the drawbacks of the conventional bakingsystem Firstly, the wafer dynamic response is constrained by the inherent sluggishdynamic of the bake plate due to its large thermal mass Secondly, the mechani-cal wafer transfer from hot plate to chill plate results in the uncontrollable wafertemperature fluctuations

per-To solve the above mentioned problems, we developed a novel design of chill integrated thermal processing module to achieve rapid dynamic response andgood wafer temperature controllability throughout the entire processing temper-ature cycle of ramp, hold and quench in lithography The system integrates thebaking and chilling processes of the lithography sequence, and thus eliminatesthe undesirable and uncontrollable temperature fluctuations during the substratetransfer process Moreover, the system is also physically compact and easy toimplement

bake-In the designed bake-chill integrated thermal processing module, a set of moelectric devices (TEDs) are employed as the main mode of heat transfer TheTEDs can provide rapid distributing heating to the substrate for facilitating uni-formity and transient temperature control Besides, the TEDs are also used to

ther-provide active cooling for chilling the substrate to a temperature suitable for sequent processing steps In the designed module, the resistance temperature de-

sub-tectors (RTDs) are embedded in the proximity pins to provide in-situ temperature

measurement

The proposed module is analyzed via first principle heat transfer analysisand backed up by experimental validation By adopting a new proposed modelbased feedback control algorithm, the temperature difference between the feed-back points can be minimized to less than 0.1◦C in the entire thermal process

In addition, the wafer spatial temperature non-uniformity can be well-controlledwithin the range of 0.4◦C and 0.1◦C during the transient and steady-state phaserespectively

1.2.2 Design and Implementation of Scatterometry in CD

fab-tion, coupled with a very efficient rigorous coupled-wave analysis (RCWA) [52]implementation, seems to be adequate for detailed reconstruction of the profiles

of periodic gratings

In this thesis, we developed a fixed angle scatterometer based on specular troscopic scatterometry proposed by Niu et al [53] This technique makes use ofthe existing spectroscopic ellipsometry (SE) equipment to measure intensity andphase of the zeroth-order diffraction at a fixed incident angle but multiple incidentwavelengths The fixed angle scatterometer configuration is mechanically less com-plex than the variable-angle scatterometer The advantage of the variable-anglescatterometry setup is that higher order diffraction can be measured Nonethe-less, as the device geometries continue to shrink, higher diffraction orders canbecome all evanescent and not measurable at far field, thus defeating the purpose

spec-to measure higher order diffraction order

Our method makes use of existing spectroscopic ellipsometer which can be

easily installed in-situ and rotating-polarizer configuration is adopted Forward

Problem including signal processing method to obtain the ellipsometric parameterswill be discussed Some sources of systematic errors of the setup such as polarizer-analyzer axis alignment, optical element imperfection, incident plane nonzero az-imuth angle effect and sample orientation are identified and proposed calibrationmethods will be included in ellipsometer calibration and data-reduction proceduresduring actual measurements The ellipsometer can complete one measurement cy-cle within 20s in spectroscopic mode (scanning mode) which is significantly fasterthan commercial ellipsometer at a spectral range of 350nm to 850nm

1.2.3 Real-time CD Monitoring and Control

An advanced process control (APC) system for real time CD monitoring andcontrol is proposed The framework of the APC system consists of a spectroscopicellipsometer and multi-zone bake-plate In this architecture, the optical sensormeasures the reflected light from the resist film during PEB at fix interval duringthe entire PEB cycle At each interval, the ellipsometric spectrums are computedand compare against a set of reference spectrums based on a set of merit functions.Based on the error amplitude, a new temperature setpoint is determined andadjusted accordingly as the chemical amplification in DUV resist is temperaturedependent

Experiment result shows that the the glass temperature of the photoresist isapproximately at 140◦C and the resist film starts to degrade after 150◦C De-protection kinetic (deblocking) commences at approximately 100◦C as latent im-age is detected Development result shows that ridge width difference between thereference wafer and controlled wafer is less than 10nm, whereas the difference be-tween the uncontrolled wafer and the reference wafer is more than 50nm, for resistfilm with same thickness after softbake With the implementation of matching thesignature plots, CD uniformity can be improved by more than 5 folds

This thesis is organized as follows In Chapter 2, a programmable multi-zoneintegrated bake-chill thermal processing system for across-wafer temperature uni-formity control is designed and developed Chapter 3 describes an optical sensor

developed for in-situ CD monitoring during PEB The sensor is based on

spectro-scopic ellipsometry and the underlying theory, signal processing and equipmentcharacterization and calibration are discussed in this chapter In Chapter 4, anadvanced process control system integrating the metrology system and multi-zonebake-plate is developed for real-time monitoring and control for DUV photoresistduring PEB Conclusions and future work are given in Chapter 5

Chapter 2

Programmable Integrated

Bake-Chill System

Resist processing in lithography sequence entails numerous thermal processes such

as post-apply bake, post-exposure bake and post-develop bake Typically, the strate will be baked on a hot-plate, which is a large piece of metal plate Aftereach baking step, the wafer will then be mechanically moved to a fixed temper-ature chill-plate where it is cooled to a temperature between 18◦C and 30◦C [20]

sub-as shown in Figure 2.1 Therefore, despite advances in steady-state and sient temperature control [54, 55], the uncontrolled and non-uniform temperaturefluctuation during the mechanical transfer of the substrate from the bake to chillplates will result in spatial temperature non-uniformities during the entire thermalcycle [31, 32] Moreover, constrained by the inherent sluggish dynamic response

tran-of the conventional bake-plate, the wafer temperature response is not fast enough

in the transient period or when there is a sudden temperature fluctuation due toexternal disturbances As depicted in Figure 2.1, the bake-plate and chill-plateare actually large one-piece plates maintained at a fixed temperature This dis-ables the regulation of spatial temperature across-wafer Failure to maintain bothsteady-state and transient state temperature uniformity will significantly impactacross-wafer CD uniformity [21, 56, 57] Requirements call for temperature to becontrolled within 0.1◦C at temperatures between 70◦C and 150◦C [16] Althoughadvanced control can be used to improve performance [26, 27, 28, 29], it has beenshown that the conventional hotplate design has poor controllability [30] due toits inherent sluggish dynamic response and that ultimately limits the achievableperformance Other disadvantage includes the lacking of a real-time, distributedand closed-loop temperature control method in the conventional hot plate as this

is another source of process error in the lithography chain

Figure 2.1: The conventional approach for lithography baking and chilling processinvolves substrate transfer between large thermal mass, fixed temperature plates

Having identified the aforementioned issues of concern, numerous works inthese directions have been done Narasimhan and Karra [58] proposed an inverse

heat transfer method to provide near-isothermal surface for conventional plate Tay et al [59] proposed a new thermal processing system consists of aheating chamber with three annuli of tungsten halogen lamp arrays to heat upthe wafer and an array of bismuth telluride thermoelectric devices as the chiller.Goto et al [24] studied the Dynamic Temperature CD Sensitivity (DTCS) of PEBprocessing and performed optimizations during transient and reported improvedtemperature controllability Zhang et al [23] proposed a multi-zone bake-platewith array of Peltier devices and thermal sensors so that thermal uniformity can

bake-be continuously measured and controlled simultaneously Most of these reportedimprovements are actually simulation results involving a preset heater temperature

to achieve uniform wafer temperature In most of these systems, the difficulties inachieving uniform temperature control are primarily due to the hardware systems.From the above review, it becomes obvious that the conventional photoresistthermal processing system has many inherent limitations which hinder the efficacy

of advanced temperature control Moreover, earlier works which demonstratedsignificant temperature uniformity improvements theoretically were not translatedinto real world applications Therefore, our objective is to design a new thermalprocessing system to achieve rapid dynamic temperature response and minimizethe temperature non-uniformity during the transfer from heating to cooling process

by real-time wafer temperature control method The system completely eliminatessubstrate movement and the attendant temperature uncontrollability between thebaking and chilling processes Finally, a new control scheme is designed to achievetemperature non-uniformity to within 0.1◦C at the controlled points

In this chapter, we propose an integrated multi-zone bake-chill system to vide fast dynamic response and achieve spatial temperature uniformity of a sili-con wafer throughout the entire processing temperature cycle of ramp, hold andquench In the proposed system, a set of thermoelectric devices is employed toprovide spatial and temporal temperature uniformity control The thermoelec-tric devices (TEDs) sit on the surface of a heat sink and together forming anactive cooling system so that we completely eliminate substrate movement andthus remove any uncontrollability between the baking and chilling processes.This chapter is organized as follows In Section 2.2, the proposed integratedbake-chill thermal processing system is illustrated The thermal modeling of thesystem is presented and the effectiveness of the model is verified in Section 2.3.

pro-In Section 2.4, the model-based controller is designed to achieve temperature formity in the thermal process Experimental results are given in Section 2.5 todemonstrate the effectiveness of the proposed method Finally, conclusions aregiven in Section 2.6

The schematic of the proposed thermal processing system is shown in Figure 2.2(A)

In this system, the wafer is placed on an array of proximity pins and is set proximately 5mils above the TEDs These proximity pins can be embedded with

ap-“S102404” thin film RTD (class B) sensors from Minco Corporation [60] to provide

in-situ temperature measurement The bake-chill surface is formed by an array of

TEDs The “HOT2.0-65-F2A” TEDs from Melcor Corporation [61] are attached

to the top of a heat sink via carbon film and integrally form the cooling system.Figure 2.2(B) depicts the plan view of the heat sink.

Figure 2.2: Schematic diagram of the integrated bake/chill design (A) schematicdrawing of the system, (B) plan view of the heat sink (Note: Figures are notdrawn to scale)

The prototype two-zone bake-chill system is shown in Figure 2.2 Two resistancetemperature detection (RTD) sensors are positioned on a 2-inch wafer to monitorthe temperature of the two zones The TEDs are grouped into 2 pseudo-circularzones and their behaviors are dictated by the calculated control signal to providethe desired heating and cooling processes and maintain temperature uniformity

In each zone, all TEDs are powered identically and one temperature sensor ischosen to represent the temperature of the zone.

Figure 2.3: Experimental setup

A mathematical model is developed for the integrated bake-chill operation to sess the performance of the proposed design The system consists of three majorentities: the wafer, the TEDs and the heat sink The wafer is assumed to be per-fectly cylindrical with a diameter of 50mm The TED selected for the system has

as-a dimension of 13.2mm×13.2mm in length (L T ) and width (W T) The TEDs areattached to a passive heat sink which dissipates heat through natural convection