Embedding TCP_IP Working Through Implementation Challenges

Device Drivers Physical hardwareTCP, UDP IP, ARP, ICMP PPP,SLIP, Ethernet User data Physical Devices AppHeader TCP Segment Application dataTCP Header Application dataTCP Header IPHeader

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Embedding TCP/IP

Working Through Implementation Challenges

Micriµm

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Renesas Technology & Solution Portfolio

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Introduction : Objectives

Block 1 : What is a TCP/IP stack?

Block 2 : Embedded system requirements

Block 3 : LAN = Ethernet

Block 4 : ARP Operation

Block 5 : Hardware/Software setup

Block 6 : IPv4 Addressing

Block 7 : IPv6 Addressing

Block 8 : Troubleshooting connection

Agenda

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 Learn to use TCP/IP properly from the start.

 Understand the requirements difference to perform IP

connectivity versus IP performance.

 Perform TCP/IP networking activities Record network traffic

and analyze results.

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Block 1

What is a TCP/IP stack?

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The Internet Protocol suite—like many protocol suites—can be viewed as a set

of layers

Each layer solves a set of problems involving the transmission of data, and

provides a well-defined service to the upper layer protocols based on using

services from some lower layers

Upper layers are logically closer to the user and deal with more abstract data,

relying on lower layer protocols to translate data into forms that can

eventually be physically transmitted

It has also been referred to as the TCP/IP protocol suite, which is named after

two of the most important protocols in it: the Transmission Control Protocol

(TCP) and the Internet Protocol (IP), which were also the first two IP

networking protocols defined

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1 Device Drivers Physical (hardware)

TCP, UDP

IP, ARP, ICMP

PPP,SLIP, Ethernet

User data

Physical Devices

AppHeader

TCP Segment

Application dataTCP

Header

Application dataTCP

Header

IPHeader

IP Datagram

14

Application data

420

20

46 to 1500 bytes

Transport Protocol Messages

Network-Specific Frames

User Data(Messages or Streams)

EthernetTrailer

TCPHeader

IPHeader

IP Datagrams

Layers in the Internet Protocol suite

EthernetHeader

User data

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Layered communication

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TCP/IP Protocol Architecture

Protocol Family

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The starting point

Implementing

TCP/IP

Understanding

TCP/IP

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Block 2

Requirements

 Connectivity only Or

 Throughput?

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CPU

Most embedded targets are slower consumers

when compared to laptop and desktop

computers.

Packets generated by a faster producer and

received by the target will consume most or all

NIC network buffers and some packets will be

dropped

Hardware features such as DMA and CPU speed

can improve this situation The latter is trivial,

the faster the target can receive and process the packets, the faster the network buffers can be

freed

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Footprint

For connectivity, a TCP/IP stack or a subset of it

can be implemented with very few RAM

(approximately 32K)

For a few Megabits per second, a more complete

TCP/IP stack is required In this case, embedded system requirements dictate in the range of 96K

of RAM for a minimal sustained throughput

Resources need to be allocated to the protocol

stack so that it can perform its duties

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Memory Usage Summary

of our setup

Other ROM / RAM Usage (cstartup, µC/CPU, CPU, µC/LCD, ) 7406 1120 1.63%

8 receive buffers

8 large transmit buffers

2 small transmit buffers

3 receive descriptors

8 transmit descriptors

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Questions?

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Block 3

LAN = Ethernet

Why Ethernet?

Because Ethernet is the ubiquitous LAN (Local Area Network)

Most of the world wide data initiates or terminates on an

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Ethernet technology

Topology

1st Generation

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Ethernet 802.3 Frame Structure

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Unicast (point to point) 00-02-0C-4B-59-78 = unique station address

Traffic types

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Broadcast (point to all-point) FF-FF-FF-FF-FF-FF = all stations group address

Traffic types

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Multicast (point to a group) 01-80-C2-00-00-01 = spanning tree group address

Traffic types

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Network buffers

A TCP-IP stack network buffer includes the Ethernet frame and

metadata to manage the buffer.

Network Buffer

Typically 1518 (1520 for alignment)

A TCP/IP stack places received packets in network buffers to be processed by the upper

protocol layers and also places data to send in network buffers for transmission Network

buffers are data structure defined in RAM

The data portion of the network buffer contains the application data and protocol headers

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– The software that interfaces between the TCP/IP stack and

the Ethernet controller

 Could be complex depending on the Ethernet controller (1000-3000 lines)

– Has dedicated memory

– Uses main memory

– Ethernet packets need to be transferred to these network

buffers

– Either copied by the CPU or through a DMA controller

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Ethernet Controller Interface

When a packet is received by the MAC, a

DMA transfer from the MAC’s internal buffer

is initiated by the MAC into main memory

This method generally provides for

shortened development time and excellent

performance.

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CPU with an internal MAC

but with dedicated memory.

When a packet is received, the MAC initiates

a DMA transfer into dedicated memory

Generally, most configurations this type

allow for transmission from main memory

while reserving dedicated memory for either

receive or transmit operations Both the

MAC and the CPU can read and write from

dedicated memory and thus the stack can

process packets directly from dedicated

memory

Porting to this architecture is generally not

difficult and provides for excellent

performance However, performance may

be limited by the size of the dedicated

memory; especially in cases where transmit

and receive operations share the dedicated

memory space.

DMA

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Ethernet Controller

Internal FIFO

& Memory DMA

CPU

TCP/IP

Main Memory

Cooperative DMA solution where both

the CPU and MAC take part in the

DMA operation.

This configuration is generally found on

external devices that are either connected

directly to the processor bus or connected via

the ISA or PCI standard This method

requires that the CPU contain a DMA

peripheral that can be configured to work

within the architectural limitations of the

external device This method is more difficult

to port to, but generally offers excellent

performance.

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Data is moved to and from main memory and

the external device’s internal memory via bus

read and write cycles The amount of data

transferred in a given bus operation depends

on the width of the data bus This method

requires additional CPU intervention in order to

copy all of the data to and from the device

when necessary This method is generally

easy to port and offers average performance Parallel I/O (Non DMA)

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CPU_REG32 Status CPU_REG32 Addr

.

DMA Descriptors Descriptor List DMA

Data

Register

Software Hardware

BufDescPtrStart

Int Ptr (BufDescPtrStart + i) % n

Step 4 With each new received frame, software increments BufDescPtrCur by 1 and wraps around the descriptor list as necessary; hardware applies the same logic to an internal descriptor pointer.

Step 1 Software allocates receive buffers.

Step 2 Software allocates a list of buffer descriptors and configures each address field to point to the start address of a receive buffer.

Step 3 Software initializes three pointers One to track the current descriptor which is expected to contain the next received frame, and two, to remember the

descriptor list boundaries Hardware is informed of the descriptor list starting address.

Step 5 When a received frame is processed, software obtains a pointer to a new data buffer and updates the current descriptor address field The previous buffer address is passed to the protocol stack for processing If

a buffer pointer cannot be obtained, the existing pointer remains in place and the frame is dropped.

DMA

Descriptors and Buffers

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Zero Copy

A true zero copy architecture - negating the need for

performance reducing memory buffer moves

Zero copy networking enables the network adapter to transfer data directly to or from application memory, eliminating the need to copy data between application memory and the data buffers in the operating system

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(2,048) 204.8

(4,883) 20.4

(48,828) 2.04

(488,281) 1024

(8,192) 819.2

(1,221) 81.9

(12,207) 8.19

(122,070) 1518

(12,144) 1,214

(823) 121.4

(8,234) 12.14

(82,345)

– Depends on many factors:

 Data is moved between the controller and the main memory using DMA?

 The CPU needs to be capable of processing all the data

 Can the CPU produce or consume the data at this rate?

 Amount of memory available for the TCP/IP stack

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IEEE 1588

Timestamping in the Application Layer

PTP UDP IP MAC PHY

T S

Milliseconds introduced by router processing

Milliseconds

of delay variation introduced

by protocol stack

processing delays

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IEEE 1588

Timestamping in the Ethernet Driver

PTP UDP IP MAC PHY

T S

Network jitter remains

Other techniques must be used to reduce this effect.

…8:40

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IEEE 1588

IEEE 1588 PTP_TSYNC Engine

TCP/IP stack

IEEE 1588 PTP protocol

stack

Software Hardware

External

• The IEEE 1588 PTP protocol stack is shown operating at the Application layer

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Embedded systems typical usage

WiFi Hardware

SPI Interface

Wifi Radio and Firmware

Handler

TxRx Handler

WiFi Driver

Application Task

WiFi Task

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Block 4

ARP Operation

ARP allows us to associate a layer 3 address (like IP) with a

layer 2 address (for example Ethernet) of different lengths.

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Station 172.16.10.5 sends a ping request (ICMP) to the station

172.16.10.8.

ARP Operation