ADC Resolution_Myth and Reality

 Collecting, analyzing and transmitting real-world signals is a major focus of the smart society.. Real-world signals are analog, so converting these signals to digital is a key focus f

Renesas Electronics America Inc.

ADC Resolution: Myth and Reality

Renesas Technology & Solution Portfolio

Microcontroller and Microprocessor Line-up

Wide Format LCDsIndustrial & Automotive, 130nm

 350µA/MHz, 1µA standby

44 DMIPS, True Low Power Embedded Security, ASSP

25 DMIPS, Low Power

10 DMIPS, Capacitive Touch

 Industrial & Automotive, 150nm

 190µA/MHz, 0.3µA standby

 Industrial, 90nm

 200µA/MHz, 1.6µA deep standby

 Automotive & Industrial, 90nm

 600µA/MHz, 1.5µA standby

 Automotive & Industrial, 65nm

 600µA/MHz, 1.5µA standby  Automotive, 40nm

 500µA/MHz, 35µA deep standby

 Industrial, 40nm

 200µA/MHz, 0.3µA deep standby

 Industrial, 90nm

 1mA/MHz, 100µA standby

 Industrial & Automotive, 130nm

 144µA/MHz, 0.2µA standby

 Collecting, analyzing and transmitting real-world signals is a major focus of the smart society Real-world signals are

analog, so converting these signals to digital is a key focus for the smart

 Understanding the specifications and hidden errors in ADC circuits will enable designs that meet the intended

specifications

‘Enabling The Smart Society’

 What does the “resolution” spec really mean

 Some standard converters and resolution

 DC accuracy specifications

 Review offset, gain, DNL and INL errors

 How the ADC is tested

 What those errors don’t tell you

 AC specifications

 SNR

 ENOB

 System errors and resolution requirements

 ADC required accuracy

 Reference errors

 Source impedance errors

 What does the term resolution mean to you?

Successive Approximation (SAR) ADC

DAC (R2R Ladder)

Comparator

Vref AVss

ADC Register

Sample and Hold Circuit Input Analog

• GPIO = Hi-Z

• Timer started

• Comp out = H – Conversion ends

L

Clock

Delta Sigma Converter

Ref

Digital Filter D

CK

4V

HH

0V

5V

+V

Result Register

Delta Sigma Converter

Ref

Digital Filter D

CK

Result Register

 Oversampling frequency (flip flop clock rate, e.g RX21A 3.125MHz)

 Minimum Conversion time – rate the result register is updated

(81.92 uS or 12.2 kHz on RX21A ) – This is based on the decimation factor of the digital filter– Some converters allow reducing decimation factor

• Faster conversion

• Lower resolution

03

ADC InputVoltage

Result will be 04 when samples are added Result will still be 04 when samples are added if no noise

xx

xx

xx

xx

S3

S402

03

ADC InputVoltage

00

01

ADC Transition Voltages

 Oversample 2X results in ½ bit increase resolution

 To increase resolution by n bits

– Oversample 4n and decimate 2n

ADC Accuracy Specifications

Non-Linearity Error

Absolute Error

Input Voltage

ADC Counts

Full Scale

Vfull Scale 0V

Real Curve

AC Specifications

 DC testing does not describe dynamic characteristic

 Sample and hold errors

 Measure SNDR, SNR and/or Spurious Free Dynamic Range

 SNR, SNDR – Ratio of RMS value to noise

 SNDR (SINAD) includes harmonics or distortion

 SFDR - ratio of the RMS value of input sine wave to the RMS

PGA Gain

 We can calculate the equivalent perfect ADC from equation

ENOB = (SNDR -1.76)/ 6.02

 The 6.02 term in the divisor converts decibels (a log10 representation)

to bits (a log2 representation).

 The 1.76 term comes from quantization error in an ideal ADC

 86 dB would then have the equivalent resolution of a 14 bit perfect ADCENOB = log2 [full-scale input voltage range/(ADC RMS noise × √12)]

Interpreting Specification

 AC testing does not provide linearity data

 DNL affects SNR

 INL affect THD

 Oversampling is still valid and reduces the average noise if Gaussian distribution

Example

Understanding the Errors an Example

 Decreasing Vref to 2.5V

– 10 mV / 2.5V = 1/250– 8 bit ADC meets resolution requirement

Understanding the Errors an Example

Output

Code

 Assume Vref = 2.56V, 8 Bit ADC (10 mV per step)

010203

Understanding the Errors an Example

 Can we use a 10 bit ADC with +/- 2 bits INL

 What about 1 bit of error

 Worst case ADC error is 2.5 mV + 1.25 mV

 0.1875% error

Understanding the Errors an Example

Output

Code

 Assume Vref = 2.56V, 10 Bit ADC (2.5 mV per step)

010203

Indicated Voltage (mV)

2.5 mV

5 mV7.5 mV

1.251 mV code 01

With 2 LSB error

Specification Condtion Min Typ Max Units TUE - Unadjusted 12 Bit Mode - ± 4 ± 6.8 LSB DNL 12 Bit Mode - ± 0.7 -1.1 to +1.9 LSB INL 12 Bit Mode - ± 1.0 -2.7 to +1.9 LSB Efs -Full Scale 12 Bit Mode - ± 4 ± 6.8 LSB

Eq - Quantization 16 Bit Mode - -1 to 0

≤ 13 Bits - ± 0.5

16 bit single ended mode avg = 32 12.2 13.9 - bits avg = 4 11.4 13.1 - bits SINAD See ENOB dB THD 16 bit single

System Considerations

Errors That Are Sometimes Forgotten

Check Accuracy Conditions

 Specification may expect:

 MCU in a sleep mode

 No IO toggling

 Specified ADC clock speed

What is the ADC Reading for the Circuit Below?

+V

R1

R2R1=R2

+Vref

MCU

Ratiometric and Non-Ratiometric Conversions

+V +Vref

AD Input

Vref Vcc

+V +Vref

AD Input

Vref Vcc

+V

AD Input

Vref Vcc

 Treat as power supply pin

– Typically <100 uA– Bypass properly

 3 mV ripple = 1 LSB error on 10bit 3V ADC

 Vref is a power supply pin

Understanding Ratiometric Reference Errors

 Vcc ≠ Vref

 Sensor biased from Vref

 Vref can pick up noise

 Bypassing ADC input can help

Loads

Reference Errors – External References

 Consider design example

 Measure 0 – 2V with < 0.5% FS error

 2.5V reference

 This measurement is non-ratiometric

 Previously calculate 0.1875% error from ADC

 Can I use a 2.56V 0.5% accurate reference diode?

AD In Vref Vcc

MCU

Reference Errors – Reference Accuracy

Source Resistance Errors

To AD Converter Block

RC time constant of source resistance and sampling cap can cause error

For M16C/62P Req = 7.8k Ceq = 1.5 pF S1 closed for 3 fAD cycles ADC Input Ckt Equivalent

Rs

Source Resistance Limitation (An Intuitive Approach)

 Desired charge error much less than

1/1024 (0.1%)

 Allow 10 time constants (0.005%)

 Sampling occurs for 300 nSec

 (3 cycles of 10 MHz AD clock)

 10 time constants = 300 nSec 1 TC = 30 nSec

 C = 1.5 pF so Rtotal (Rs + Req) must be 20Kohm or less

 (300 nSec/1.5 pF)

 Rsource can not be greater than 12.2 K ohms

 Equivalent resistance of the AD circuit is 7.8K

 (Strict analysis indicated 13.8 kOhm)

Source Resistance Errors

For M16C/62P Req = 7.8k Ceq = 1.5 pF

C1

Rs

 What does the “resolution” spec really mean

 Some standard converters and resolution

 DC accuracy specifications

 Review offset, gain, DNL and INL errors

 How the ADC is tested

 What those errors don’t tell you

 AC specifications

 SNR

 THD

 ENOB

 How does this affect my application

 Errors and considerations

Questions?

 Collecting, analyzing and transmitting real-world signals is a major focus of the smart society Real-world signals are

analog, so converting these signals to digital is a key focus for the smart

 Understanding the specifications of an ADC and the effects

of system device selections will help the information

delivered by the smart society provide an accurate picture of

‘Enabling The Smart Society’

Also Check the Conditions

Delta Sigma Converter

Effect of Adding Capacitor to Input Pin

Adding capacitor creates a low pass filter

To AD Converter

Block S1

Ceq Req

Rs

C1

Freq Gain

fc

fc = 1/2πRC 20k Rs and 0015 uF = 5.3 kHz corner

 Below a certain frequency, THD is only dependent on the

overall INL of the converter

 For an example, if the converter depicted in Figure 2 is

being used to digitize a signal which can slew at an

equivalent rate to that of a 10kHz signal, then the "THD"

performance of the converter will be roughly -86dB This

figure means that the harmonic distortion is 86dB below the converter's full-scale range Since the full-scale range of this 16-bit converter is ±32,768, then the harmonic distortion represents roughly ±1.6 LSB of error.