Tài liệu tham khảo về ATM

Lợi ích của ATM • Cho phép hội tụ của Voice, Video, dữ liệu trên một mạng chuyển mạch • Tốc độ cao ở cấp độ phần cứng • Băng thông có thể được cấp phát khi cần thiết • Được xác định trước và chất lượng dịch vụ (QoS) và Class of Service (CoS) đảm bảo quản lý • Superior tính năng • Khả năng mở rộng trong tốc độ và quy mô mạng lưới • Dễ tích hợp với các công nghệ khác

Asynchronous Transfer Mode

Introduction

What is ATM?

switching architecture

– Operates at Layer 2 of the OSI-RM

Data traffic on the same network

– Guarantees Quality and Class of Service

backbone networks

Benefits of ATM

Class of Service (CoS)

Applications of ATM

networks

History and Market Dynamics

Need for Network

Convergence

(Frame Relay, SMDS, etc.)

PSTN is circuit switched (voice-optimized) and based WAN not efficient

networks since no guarantee of QoS

too successful, i.e ISDN

History of ATM

technology for a new Broadband ISDN (B-ISDN) network

required to implement a multi-service ATM network

1992 - ATM Forum issues 1st Spec

1993 - ATM Forum adds user committees

1996 - ATM Forum approves the Anchorage Accord

0 1000 2000 3000 4000 5000 6000 7000

2 0 0 0 2 00 1 2 0 0 2 20 0 3 2 00 4 2 0 0 5 2 00 6

Source: IDC Jan '02

ATM Today

networks

ATM Market Drivers

– 9% CAGR from 2001 to 2006

– Data Services (X.25, Frame Relay and ATM)

– IP Virtual Private Networks

– New World Voice

– 3G Wireless

– Continued deployment of legacy equipment

ATM Technology

ATM Technology Topics

– ATM Adaptation Layer (AAL) and Class of Service

– ATM Cell Structure & ATM Layer

Fundamental ATM Concept

Interfaces (NNI) are specifications for the connections

ATM Switching Backbone (WAN)

ATM

Switch

ATM Switch

ATM Service Switch

ATM Service Switch

Fundamental ATM Concept

to switch, in sequential order

Virtual Connection

Voice ATM Cell

Video ATM Cell

Data ATM Cell

Customer Premise

ATM Switching Backbone (WAN)

ATM

Switch

ATM Switch

ATM Service Switch

ATM Service Switch

Customer Premise

Virtual Paths and Channels

networks to guarantee quality of service

• A Virtual Path Connection (VPC) is a logical, end connection

end-to-– Indentified in the VPI bits of the cell header

(VCC) which have same end points as the Virtual Path

– Can be permanent, i.e, Permanent Virtual Channel (PVC) or dynamic, i.e Switched Virtual Channel (SVC)

– Identified in the VCI bits of the cell header

Virtual Paths and Channels

Transmission

Path

VPC 2 VPC 2

VCC 1 VCC 2

VPC = Virtual Path Connection VCC = Virtual Channel Connection

ATM Reference Model

– ATM Adaptation Layer - with convergence and SAR sub-layers

– ATM Cell Structure and ATM Layer

Physical Medium sub-layers

ATM Adaptation Layer (AAL) ATM Layer Physical Layer

Convergence Sublayer (CS)

Segmentation and Reassembly Sublayer (SAR)

Transmission Convergence

Sublayer (TC) Physical Medium Sublayer

ATM Adaptation Layer (AAL)

– Convergence Sublayer (CS)

access point (NSAP)

– Segmentation and Reassembly Sublayer (SAR)

necessary overhead at the sending node and reassembles cells

at receiving node

Classes of Service

format of incoming information based on 1 of 4 classes of service assigned by the application

– Class A: Constant bit rate (CBR), Connection oriented, strict timing relationship between source and destination, i.e voice

– Class B: Variable bit rate (VBR), Connection oriented, strict

timing, e.g packet-mode video for video conferencing

– Class C: Connection oriented VBR, not strict timing, e.g LAN data transfer applications such as Frame Relay

– Class D: Connectionless VBR, not strict timing, e.g LAN data transfer applications such as IP

AAL Types and Class of

Service (CoS)

AAL types to accommodate a particular service class

– For IP, LAN frames, signaling messages, frame relay, video

AAL Type

Classes Supported Traffic Characteristics

AAL1 Class A

Connection Oriented, CBR (e.g

Voice) AAL2 Class B

Connection Oriented, VBR (e.g

packet based video)

ATM Cell

fixed size units called “cells”

the hardware level

these fixed length cells

ATM Cell Structure

• GFC - Generic Flow Control (4 bits)

– Controls the flow of data across the UNI

permitting multiple ATM devices to be

attached to the same network interface

• VPI - Virtual Path Identifier (8 bits)

– Contains the address of the Virtual Path

for the end-to-end connection

• VCI - Virtual Channel Identifier (16 bits)

– A pointer that identifies the virtual

channel the system is using on a

• PTI - Payload Type Identifier (3 bits)

– Indicates the type of traffic contained in the cell (User Information or Control)

• CLP - Cell Loss Payload (1 bit)

– Indicates droppability or droppability of a cell during congestion

non-– 1 = droppable; 0 = not droppable

• HEC - Header Error Control (8 bits)

– Provides error control for single-bit errors and error detection for multiple-bit errors in the cell error

• Payload - User Information

ATM Layer Functions

cells and also does the switching

– based on information received from higher layers

cell payload to higher layers

Physical Layer

defines mechanical specs (connectors, etc.)

– Transmission Convergence Sublayer

on transmit and delineates ATM cells in the received bit stream

– Physical Medium Sublayer

ATM/SONET Internetworking

SONET or SDH

frame is done by the PHY layer’s TC sublayer

ATM Cell Mapping into

SONET Frame

ATM Cell

T O H

T O H

Spans across Path Overhead

STS-1 SPE

P O H

P O H

UTOPIA Interface

ATM (UTOPIA)

1st UTOPIA spec in 1994

ATM Layer IC

PHY Layer IC

UTOPIA Interface

UTOPIA Interface

– Level 3 & 4 not backward compatible with Level 1 & 2

– Level 4 uses Differential Signaling (LVDS)

– Multiple PHY support on Levels 2-4 allows breaking down of faster channels into multiple smaller channels

Speed (bps) 155M 622M/155M 3.2G/1.6G/800M 10G/5G/2.5G

ATM Standards

Anchorage Accord

Accord is the milestone ATM Forum document which

comprises sixty specifications

ATM Standards

evolving and growing in size

– Foundation Standards

– Application and Service Standards

creation and revising of ATM specs

Foundation Standards

• UNI - User-Network Interface

• NNI - Network-Network

Interface

• PHY - Physical Specifications

• B-ICI - Broadband ISDN

Application & Service

Standards

• FUNI - Frame UNI

• FR/ATM - Frame Relay over

UNI Standards

(ES) and switches, also called Intermediate Systems (IS)

or public

allows a frame-based, legacy CPE device to interface

with ATM networks

NNI Standards

as switches, from the same network or different networks

or public as in a Service Providers network

protocol used for connecting nodes within a network or for interconnecting networks

ATM Equipment

Types of ATM Equipment

ATM Switch Key Attributes

– Blocking, virtually non-blocking, or non-blocking

switch size and maximum port speed

– Single bus, Multiple bus, Self Routing, Augmented Self

Routing

service categories and statistical multiplexing gain

– Internal Queuing, Input Queuing, Output Queuing, Output

Queuing/Shared Buffer

Types of Switches

– the core of a public ATM service Network

– Located in carrier POPs; feed into Carrier Backbone Switch

– Along with Backbone Switch, can connect to other networks such as voice, frame relay and the internet

– Found in the Customer premise; connects to the WAN via UNI

ATM Switch Hierarchy

Carrier

Enterprise

LAN/Campus Backbone

Carrier Backbone

Enterprise

LAN/Campus Backbone

Voice IP

Frame Relay

.

Carrier Point of Presence (POP) or Central Office (CO)

Customer Premises Location (CPE)

ATM Enabled Devices

– Routers - Convert between IP packets and ATM cells

– Bridges - connects bridgeable protocol such as Ethernet or Token Ring and connects it over an ATM network

– Hubs - allows ATM equipped Clients to share medium

– Multiplexers - takes multiple interfaces on input and

concentrates them into a single ATM WAN trunk

– CSUs/DSUs - Channel Service Unit/Data Service Unit

utilizing the frame-based ATM DXI or FUNI protocol into a stream of ATM cells for transmission over an ATM UNI

ATM NICs

ATM end systems computer bus

supports the AAL and ATM protocols

hub to interface with a legacy LAN device

– This is called a virtual LAN and uses the LANE ATM Standard

Xilinx Solutions for ATM

Xilinx – The PLD Industry

Leader

Virtex-II: The Winning

Architecture

• #1 FPGA architecture

• 150 nm 8-layer metal CMOS

• Advanced logic & routing

• Highest density in the industry

• Embedded Dual Port RAM

Virtex-II 97%

Other 3%

50 :

50 :

Impedance Controller

0 500 1000 1500 2000 2500 3000 3500 4000

Embedded DSP

functionality - up to

500 Billion MAC/s

Embedded DualPort RAM

-for Data Buffering

CLKFX180

PSDONE

CLK2X180 PSINCDEC

STATUS[7:0]

DSSEN

PSCLK

CLK2X CLKFB

Virtex-II Series Expanded to

Include Virtex-II Pro

• Virtex-II Logic, Routing, Features

– Upward compatible, same design tools

– Embedded Multipliers, SelectIO-Ultra (with 840Mbps LVDS), DCI/XCITE, DCM

• Up to 24, 3.125 Gbps serial transceivers

– Channel bonding, 8b/10b encoding

– Supports high-speed interfaces GbE, 10GbE (XAUI), PCI/PCI-X, Infiniband, RapidIO, HyperTransport, FlexBus 3/4, POS-PHY 3/4

• Up to four IBM 405 PowerPC®

– 32-bit RISC CPU: 420 DMIPS @ 300 MHz

– The leading embedded CPU architecture in telecom & networking infrastructure

– IBM CoreConnect™ on-chip bus

Virtex-II Pro and IP Solutions will Further Enable Next

Generation Networking and Telecom Products

Virtex-II Pro Helps You Manage the Transition from Parallel to Serial I/Fs

Reg Reg

DDR FF

• Helps preserve investment in legacy designs

• Eases transition from parallel to serial technology

• Parallel interface designs will not go away

Supporting Legacy &

Evolving System Interfaces

Xilinx Virtex-II Pro FPGAs

PCI 32/64 10/100 Ethernet (MII)

Proprietary

RapidIO POS-PHY L3/L4 FlexBus 3/4 CSIX HyperTransport SPI4 Phase1, Phase2 Gigabit Ethernet - GMII

10 Gbit Ethernet (XGMII)

840Mbps LVDS Proprietary

QDR SRAM

NoBL/ZBT SRAM

SDR/DDR SDRAM

FCRAM Sigma RAM

RLDRAM CAMs

Serial RapidIO Infiniband 3GIO/Arapahoe Fibre Channel

10 Gbit Ethernet (XAUI)

CLB IOB

CLB

CLB CLB IOB

IOB IOB CLB

CLB CLB CLB CLB

CLB CLB CLB

CLB IOB

CLB

CLB CLB

IOB

B R A M DLL

CLB

CLB CLB CLB CLB

CLB CLB CLB

CL

I O B

CL

I O B I O B

I O B I O B

B R A M

DLL CLB

IOB

CLB CLB IOB

IOB IOB

B R A M CLB

CLB CLB CLB

B R A M CLB

CLB CLB CLB

I O B I O B

I O B I O B

I O B I O B CL

CL

B R A M

I O

DLL

B R A M IOB

Delay Lock Loops

CLK0 CLK90 CLK180 CLK270 CLK2X CLKDV LOCKED

DLL

Dual-Port 4Kbit BRAM Po

Optical Networking Related

Soft IP Available Today

• Networking / Telecom

– 1/10Gb Ethernet MACs - XAUI, XGMII

– 10/100 Mbps Ethernet MACs

– T1/E1 Framer/De-framer

– UTOPIA Level-2/3 PHY-ATM

– Network Classification Processor (2.5Gbps)

ATM Switch

Memory

Memory I/F

Network Management CPU

Framer

SER / DES Optics

Framer Optics

Framer Optics

Switch Fabric ASIC or ASSP

System Bus

Cell Buffer

SER / DES

SER / DES

ATM Cell Assembly / Delineation

ATM Cell Assembly / Delineation

ATM Cell Assembly / Delineation

Backplane SERDES

UTOPIA

SFI

SFI

SFI

Cell Assembly & Delineation

– Performs the functions required in the transmit stream of the

TC sub-layer of an ATM PHY processor

– Conforms to SDH based specifications of ITU I.432.1.

– Clock of up to 80 Mhz compatible w/ DS3, E3, STS-3c/12c

– Performs the functions required in the receive stream of the Transmission Convergence

– Conforms to SDH based specifications of ITU I.432.1.

– Clock of up to 80 Mhz compatible w/ DS3, E3, STS-3c/12c

Inverse Multiplexing over

ATM (IMA) Core

high bandwidth stream of

ATM cells over multiple

lower rate facilities like

T1/E1

links and 32 groups

Cell Rate (IDCR)

specified by the ATM

Forum

• Utopia Level 2 Interfaces to PHY side and ATM side

• Programmable µP interface compatible w/ Intel & Motorola

• Implementation Example

Target Device Virtex E

XCV400E-6

Virtex-II XC2V1000-4 Size 4798 CLBs 5118 CLBs

IMA Core Block Diagram

– Fully compliant with ATM Forum UTOPIA specifications

– Single and Muti PHY support

32-bit Soft Processor

Solution

Harvard style 32-bit RISC architecture

– More than three times the D-MIPS speed and half the density

of the nearest competitor

– Full 32-bit operands, 32-bit data path and 32-bit registers

providing maximum performance

– Supports both on-chip BlockRAM and/or external memory

– Standard set of peripherals use the same CoreConnect OPB bus as the PowerPC

MicroBlaze Diagram

Off-Chip Memory 0-4GB

Off-Chip Memory 0-4GB

Machine Status Reg

Program Counter

32 x 32bit

r0 r1

r3 1

Address side LMB

CoreConnect OPB I/F

CoreConnec t OPB I/F

Data Side LMB

UART

Timer / Counters

Interrupt Controller

General Purpose I/O

Watchdog Timer

Instruction Buffer

Multipl y

Add / Subtract Shift /

• Processor

– Powerful 32-bit RISC architecture

– Efficient Harvard-style busses

– Efficient 3-operand instruction word

– 100 D-MIPS (Dhrystone 2.1)

– 32-bit data path (non-multiplexed)

– 32-bit general purpose registers

(32 registers)

– Fast operation – 125MHz on

Virtex-II (-5) FPGAs

– Minimal logic requirements – uses

less than 900 Logic Cells

– IBM CoreConnect bus for

interconnect

• Peripheral set:

– UART, GPIO – Timer/Counter – Interrupt Controller – Watchdog Timer – External Flash and SRAM interface – Arbiter

– 10/100 Ethernet MAC – SPI

– IIC

• Internet Reconfigurable Logic (IRL)

– allows change of hardware design remotely over any network

MicroBlaze Features

Summary

QoS and CoS has made it the dominant cell switching technology in WAN backbones

experience single digit growth over the next few years

– High-performance Virtex-II and Spartan-IIE fabric & features; addition of Power PC and MGTs on Virtex-II Pro

– IP for Framing, System I/O, Memory Interfaces, General

processing IP

For more information, go to:

Or contact the eSP team

espteam@xilinx.com