MIPS processor design

MIPS processor design 1 Introduction “The performance of software systems is dramatically affected by how well soft ware designers understand the basic hardware technologies at work in a system.” According to the book “Computer Organization Design” written by David A. Patterson and John L. Hennessy the hardware and behaviour of a micropro cessor is implemented in VHDL.

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University of Ulster at Jordanstown

University of Applied Sciences, Augsburg

Master of Engineering

VLSI Design Project Report

Processor Implementation

in VHDL

According to Computer Organisation & Design

by David A Patterson and John L Hennessy

M Schmid

Supervisor(s): J Färber

A Eder

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Document Revision History, Designers

Document Revision History

0.1 15/05/2007 M Schmid First draft release

0.2 15/05/2007 M Linder Features of the project

0.3 29/05/2007 M Linder Target Spec (2.1, 2.2)

0.4 10/06/2007 M Linder Target Spec (2.3)

0.5 30/06/2007 M Linder - include jump instruction to Target Spec

- Module Spec of Control0.6 02/07/2007 M Linder Module Spec of Data

0.6.1 02/07/2007 M Schmid Module Spec of ALU and Memory

0.6.2 03/07/2007 M Schmid Design Tasks

0.7 04/07/2007 M Linder - Module Spec of Datapath

- Synthesis Results

- References0.8 05/07/2007 M Linder, M Schmid - Synthesis Results

- Source Code

- Conclusion1.0 05/07/2007 M Linder, M Schmid Final release

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Contents

1 Introduction 1

1.1 Starting from a Simple Implementation Scheme 1

1.2 Using Multicycle Implementations 2

1.3 Enhancing Performance with Pipelining 2

2 Target Specification 3

2.1 Building a Datapath 3

2.1.1 Major Components 3

2.1.2 Components for Arithmetic and Logic Functions 4

2.1.3 Load word (lw) and store word (sw) instructions 5

2.1.4 Branch on equal instruction 6

2.1.5 Jump Instruction 6

2.2 Simple Implementation Scheme 7

2.2.1 Creating a Single Datapath 7

2.2.2 ALU Control 8

2.2.3 Main Control 9

2.2.4 Disadvantages of a Single-Cycle Implementation 10

2.3 Multicycle Implementation 11

2.3.1 Additions and Changes in the Scheme 11

2.3.2 Execution of Instructions in Clock Cycles 14

2.3.3 Defining the Control by a Finite State Machine 18

3 Design Tasks 21

4 Module Specification 22

4.1 ALU 22

4.1.1 Functional Description 22

4.1.2 Block Diagram 23

4.1.3 Simulation Results 26

4.1.4 Design Files 26

4.2 Memory 27

Department of Electrical Engineering

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4.3 Control 30

4.3.2 State Diagram 31

4.3.5 Design Files 33

4.4 Data Path 34

4.4.1 Instruction Fetch 34

4.4.1.1 Functional Description 34

4.4.1.2 Block Diagram 34

4.4.1.3 Design Files 35

4.4.2 Instruction Decode 35

4.4.3 Execution 36

4.4.4 Memory Writeback 39

4.4.5 Data Path 42

4.5 Processor and Memroy 43

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7.2 Annotations to “Computer Organization & Design” [PaHe98] 50

7.3 Further work on the project 51

8 Appendix 52

8.1 Design files 52

8.1.1 Project Entities 52

8.1.2 Project Architectures 58

8.1.3 Package 79

8.1.4 Testbenches 80

8.2 References 91

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List of Figures

Figure 1.1: Simple block diagram with datapaths [PaHe98] p 352 1

Figure 1.2: Multicycle Datapath [PaHe98] p 414 2

Figure 1.3: Pipelined Version of the Datapath [PaHe98], p 452 2

Figure 2.1: Instruction Memory, Program Counter and Adder [PaHe98], p 344 3

Figure 2.2: Datapath for fetching instructions and incrementing the PC [PaHe98] p 345 3

Figure 2.3: Register and ALU [PaHe98] p 346 4

Figure 2.4: Datapath for R-type Instructions [PaHe98] p 347 4

Figure 2.5: Data Memory and Sign extension unit [PaHe98] p 348 5

Figure 2.6: Load or Store Word instruction field 5

Figure 2.7: Datapath for Load Word and Store Word [PaHe98] p 348 5

Figure 2.8: Datapath for a branch instruction [PaHe98] p 350 6

Figure 2.9: Completed Simple Datapath [PaHe98] p 353 7

Figure 2.10: MIPS field 8

Figure 2.11: Table for ALU Control 8

Figure 2.12: Datapath with ALU Control Unit [PaHe98] p 358 9

Figure 2.13: Meaning of the main control signals [PaHe98] p 359 9

Figure 2.14: The simple datapath with the control unit [PaHe98] p 360 10

Figure 2.15: Truth table of the main control unit [PaHe98] p 361 10

Figure 2.16: Abstract view of a multicycle desing [PaHe98] p 378 11

Figure 2.17: Complete Datapath for multicycle design [PaHe98] p 383 13

Figure 2.18: Actions of 1-bit control signals [PaHe98] p 384 14

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Figure 4.6: Simulation Results of Memory (registered outputs) 28

Figure 4.7: Simulation Results of Memory (unregistered outputs) 29

Figure 4.8: Control Finite State Machine 31

Figure 4.9: Control FSM 32

Figure 4.10: ALU Control 32

Figure 4.11: Control 33

Figure 4.12: Simulation Results of the Control FSM 33

Figure 4.13: Instruction Fetch 34

Figure 4.14: Instruction Decode 35

Figure 4.15: Execution 37

Figure 4.16: Memory Writeback 40

Figure 4.17: Processing Unit (Datapath & Controlpath) 43

Figure 4.18: Processing Unit & Memory 43

Figure 5.1: Analysis & Synthesis Summary 45

Figure 5.2: Analysis & Synthesis Settings 46

Figure 5.3: Compilation History 46

Figure 6.1: Simulation Results of MIPS and Memory 49

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List of VHDL-Source

VHDLSource 8.1: e_control_ControlFSM.vhd 52

VHDLSource 8.2: e_control_ALUControl.vhd 52

VHDLSource 8.3: e_control.vhd 52

VHDLSource 8.4: e_tempreg.vhd 53

VHDLSource 8.5: e_pc.vhd 53

VHDLSource 8.6: e_instreg.vhd 53

VHDLSource 8.7: e_regfile.vhd 54

VHDLSource 8.8: e_alu_vhd 54

VHDLSource 8.9: e_data_fetch.vhd 54

VHDLSource 8.10: e_data_decode.vhd 55

VHDLSource 8.11: e_data_execution.vhd 55

VHDLSource 8.12: e_data_memwriteback.vhd 56

VHDLSource 8.13: e_data.vhd 56

VHDLSource 8.14: e_ram.vhd 56

VHDLSource 8.15: e_memory.vhd 57

VHDLSource 8.16: e_mips.vhd 57

VHDLSource 8.17: e_procmem.vhd 57

VHDLSource 8.18: a_control_ControlFSM.vhd 60

VHDLSource 8.19: a_control_ALUControl.vhd 61

VHDLSource 8.20: a_control.vhd 62

VHDLSource 8.21: a_tempreg_behave.vhd 63

VHDLSource 8.22: a_pc_behave.vhd 63

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VHDLSource 8.32: a_memory_behave.vhd 75

VHDLSource 8.33: a_mips.vhd 77

VHDLSource 8.34: a_procmem.vhd 78

VHDLSource 8.35: p_procmem_definitions.vhd 79

VHDLSource 8.36: t_alu_fileio.vhd 83

VHDLSource 8.37: t_memory.vhd 86

VHDLSource 8.38: t_procmem.vhd 87

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1 Introduction

1 Introduction

“The performance of software systems is dramatically affected by how well ware designers understand the basic hardware technologies at work in a system.” According to the book “Computer Organization & Design” written by David

soft-A Patterson and John L Hennessy the hardware and behaviour of a cessor is implemented in VHDL.

micropro-1.1 Starting from a Simple Implementation Scheme

In the first section starting from a simple implementation scheme of a MIPS set the basic hardware of the microcontroller´s datapath and its control is devel- oped step by step and implemented in VHDL Testbenches will verify the correct

sub-implementation of the arithmetic-logical instructions (add, sub, and, or and slt), the memory-reference instructions (load word and store word) and the branch instructions (beq and jump).

Figure 1.1: Simple block diagram with datapaths [PaHe98] p 352

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1.2 Using Multicycle Implementations

1.2 Using Multicycle Implementations

Establishing that the efficiency of a long single-cycle implementation is not likely

to be very good the processor´s speed is improved by using multicycle mentations Then, instructions are allowed to take different numbers of clock cycles and functional units can be shared within the execution of single instructions.

imple-1.3 Enhancing Performance with Pipelining

In order to enhance the performance and to get very fast processors another plementation technique called pipelining is introduced Multiple instructions are overlapped in execution so that some stages are working in parallel.

im-Figure 1.2: Multicycle Datapath [PaHe98] p 414

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incre-All these elements are shown in figure 2.1.

After fetching one instruction from the instruction memory, the program counter has to be incremented so that it points to the address of the next instruction 4 bytes later.

This is realised by the datapath shown in figure 2.2.

Figure 2.1: Instruction Memory, Program Counter and Adder

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2.1 Components for Arithmetic and Logic Functions

2.1.2 Components for Arithmetic and Logic Functions

The instructions we use all read two registers, perform an ALU operation and write back the result.

These arithmetic-logical instructions are also called R-type instructions

([PaHe98] p 154) This instruction class considers add, sub, slt, and and or.

The 32 registers of the processor are stored in a Register File To read a word two inputs and two outputs are needed The inputs are 5 bits wide and specify the register number to be read, the outputs are 32 bits wide and carry the value of the register.

data-To write the result back two inputs are needed: one to specify the register ber and one to supply the data to be written The Register is shown in Figure 2.3.

num-To process the data from the Register, an ALU with two data inputs is used Figure 2.4 shows the combination of Register and ALU to operate on R-type instructions.

Figure 2.3: Register and ALU [PaHe98] p 346

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2.1 Load word (lw) and store word (sw) instructions

2.1.3 Load word (lw) and store word (sw) instructions

Two more elements are needed to implement the sw- and lw-instructions: the

Data Memory and the Sign Extension Unit.

The sw- and lw-instructions compute a memory address by adding a register

val-ue to the 16-bit signed offset field contained in the instruction.

Because the ALU has 32-bit values, the instruction offset field must be sign tended from 16 to 32 bits simply by concatenating the sign-bit 16 times to the original value.

ex-The instruction field for a lw- or sw-instruction is shown in figure 2.6:

6 bits 5 bits 5 bits 16 bits

Figure 2.6: Load or Store Word instruction field Figure 2.5: Data Memory and Sign extension unit [PaHe98] p 348

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2.1 Branch on equal instruction

2.1.4 Branch on equal instruction

The beq instruction has three operands, two registers that are compared for

equality, and a 16-bit offset used to compute the branch target address relative

to the branch instruction address.

Figure 2.8 shows the datapath for a branch on equal instruction This datapath must do two operations: compare the register contents and compute the branch target.

Therefore two things must be done: The address field of the branch instruction must be sign extended from 16 bits to 32 bits and must be shifted left 2 bits so that it is a word offset.

The branch target address is computed by adding the address of the next struction (PC + 4) to the before computed offset.

in-2.1.5 Jump Instruction

Figure 2.8: Datapath for a branch instruction [PaHe98] p 350

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2.2 Simple Implementation Scheme

2.2 Simple Implementation Scheme

The simplest possible implementation of the MISP Processor contains the ath segments explained above added by the required control lines.

datap-2.2.1 Creating a Single Datapath

The simplest datapath might attempt to execute all instructions in one clock cle This means that any element can be used only once per instruction So these elements have to be duplicated.

cy-If possible datapath elements can be shared by different instruction flows fore multiple connections to the input must be realised This is commonly done

There-by a multiplexer.

Figure 2.9 shows the combined datapath including a memory of instructions and one for data, the ALU, the PC-unit and the mentioned multiplexers.

Figure 2.9: Completed Simple Datapath [PaHe98] p 353

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6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Figure 2.10: MIPS field The meaning of the fields are:

Instruction

opcode ALUOp Instruction operation Funct field ALU action Desired ALU control input

LW 00 load word XXXXXX add 010

SW 00 store word XXXXXX add 010Branch equal 01 branch equal XXXXXX subtract 110R-type 10 add 100000 add 010R-type 10 subtract 100010 subtract 110R-type 10 AND 100100 and 000R-type 10 OR 100101 or 001R-type 10 set on less than 101010 set on less than 111

Figure 2.11: Table for ALU Control

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Figure 2.13 shows the meaning of the several control signals.

Signal name Effect when deasserted Effect when asserted

RegDst The register destination number for the Write

re-gister comes from the rt field (bits 20-16) The register destination number for the Write re-gister comes from the rd field (bits 15-11).RegWrite None The register on the Write register input is written

with the value on the Write data input

ALUSrc The second ALU operand comes from the

se-cond register file output (Read data 2)

The second ALU operand is the sign-extended, lower 16 bits of the instruction

PCSrc The PC is replaced by the output of the adder

that computes the value of PC + 4

The PC is replaced by the output of the adder that computes the branch target

MemRead None Data memory contents designated by the

ad-dress input are put on the Read data output.MemWrite None Data memory contents designated by the ad-

dress input are replaced by the value on the

Wri-te data input

MemtoReg The value fed to the register Write data input

co-mes from the ALU The value fed to the register Write data input co-mes from the data memory

Figure 2.13: Meaning of the main control signals [PaHe98] p 359

Figure 2.12: Datapath with ALU Control Unit [PaHe98] p 358

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2.2 Main Control

The connection of the main control unit is shown in figure 2.14 This and the meaning of the signals described in figure 2.13 leads directly to the truth table for the main control unit shown in figure 2.15.

Instruction RegDst ALUSrc

Reg

Memto-Reg Write

Mem Read

Mem Write Branch ALUOp1 ALUOp2

Figure 2.15: Truth table of the main control unit [PaHe98] p 361

2.2.4 Disadvantages of a Single-Cycle Implementation

Figure 2.14: The simple datapath with the control unit [PaHe98] p 360

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2.3.1 Additions and Changes in the Scheme

Figure 2.16 shows a abstract design of a multicycle datapath.

Comparing to the single-cycle datapath the differences are that only one memory unit is used for instructions and data, there is only one ALU instead of an ALU and two adders and several output registers are added to hold the output value

of a unit until it is used in a later clock cycle.

The instruction register (IR) and the memory data register (MDR) are added to save the output of the memory The registers A and B hold the register operands read form the register file and the ALUOut holds the output of the ALU.

With exception of the IR all these registers hold data only between a pair of adjacent clock cycles.

Figure 2.16: Abstract view of a multicycle desing [PaHe98] p 378

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2.3 Additions and Changes in the Scheme

Because the IR holds the value during the whole time of the execution of a instruction, it requires a write control signal.

The reduction from former three ALUs to one causes also the following changes

in the datapath:

An additional multiplexer is added for the first ALU input to choose between the

A register and the PC.

The multiplexer at the second ALU input is changed from a two-way to a way multiplexer The two new inputs are a constant 4 to increment the PC and the sign-extended and shifted offset field for the branch instruction.

four-In order to handle branches and jumps more additions in the datapath are required.

The three cases of R-type instructions, branch instruction and jump instruction cause three different values to be written into the PC:

• The output of the ALU which is PC + 4 should be stored directly to the PC.

• The register ALUOut after computing the branch target address.

• The lower 26 bits of the IR shifted left by two and concatenated with the upper 4 bits of the incremented PC, when the instruction is jump.

If the instruction is branch, the write signal for the PC is conditional Only if the the two compared registers are equal, the computed branch address has to be written to the PC.

Therefore the PC needs two write signals, which are PCWrite if the write is unconditional (value is PC + 4 or jump instruction) and PCWriteCond if the write

is conditional.

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2.3 Additions and Changes in the Scheme

Figure 2.17 shows the completed datapath for a multicycle implementation including the whole control.

It also shows that the write signal for the PC is combined form the ALU zero bit and the two write signals PCWrite and PCWriteCond by an AND gate and OR gate.

Figure 2.17: Complete Datapath for multicycle design [PaHe98] p 383

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2.3 Execution of Instructions in Clock Cycles

2.3.2 Execution of Instructions in Clock Cycles

The execution of an instruction is broken into clock cycles, that means that each instruction is divided into a series of steps.

Therefore the setting of the control signals are shown in figures 2.18 and 2.19.

Signal name Effect when deasserted Effect when asserted

RegDst The register file destination number for the Write

register comes from the rt field The register file destination for the Write register comes from the rd fieldRegWrite None The general-purpose register selected by the Wri-

te register number is written with the value of the Write data input

ALUSrcA The first ALU operand is the PC The first ALU operand comes from the A registerMemRead None Content of memory at the location specified by the

Address input is put on Memory data output.MemWrite None Memory contents at the location specified by the

Address input is replaced by value on Write data input

MemtoReg The value fed to the register file Write data input

comes from ALUOut

The value fed to the register file Write data input comes from the MDR

IorD The PC is used to supply the address to the

Figure 2.18: Actions of 1-bit control signals [PaHe98] p 384

ALUOp 00 The ALU performs an add operation

01 The ALU performs an subtract operation

10 The function field of the instruction determines the ALU operation

ALUSrcB 00 The second input to the ALU comes from the B register

01 The second input to the ALU is the constant 4

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The execution of an instruction is divided into maximal five steps.

Different elements of the datapath can work in parallel during one clock cycle, whereas others can only be used in series.

So there must be sure, that after one step the values computed are stored either

in the memory or in one of the registers.

The operation steps are:

1 Instruction fetch step

Fetch the instruction from the memory and computed the address of the sequential instruction:

2 Instruction decode and register fetch step

It is still unknown what the instruction is, so there can only be performed actions that are applicable for all instructions or are not harmful.

The registers indicated by the rs and rd field of the instruction are read and store into the A and B register, and the potential branch target is computed and stored into the ALUOut register.

A = Reg[IR[25-21]]

B = Reg[IR[20-16]]

ALUOut = PC + (sign-extend (IR[15-0]) << 2)

Control signal setting:

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3 Execution, memory address computation or branch completion

In this step the instruction is known and the operation depends on what the instruction is One of these four functions is executed:

1 Memory reference:

ALUOut = A + sign-extend(IR[15-0])

ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00

2 Arithmetic-logical instruction:

ALUOut = A op B

ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10

3 Branch:

if (A == B) PC = ALUOut

ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond = 1 PCSource = 01

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4 Memory access or R-type instruction completion step

In this step a load or store instruction accesses memory or a logical instruction writes its result.

2 Arithmetic-logical instruction:

Reg[IR[15-11]] = ALUOut

RegDst = 1 RegWrite = 1 MemtoReg = 0

5 Memory read completion step

The load instruction is completed by writing back the value from the memory:

These five steps are summarised in figure 2.20.

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Step name Action for R-type

instructions

Action for reference instructions

memory-Action for branches

Action for jumps

Instruction fetch IR = Memory[PC]

PC = PC + 4Instruction decode

register fetch

A = Reg[IR[25-21]]

B = Reg[IR[20-16]]

ALUOut = PC + (sign-extend(IR[15-0] << 2)Execution, address

computation,

branch/jump

completi-on

ALUOut = A op B ALUOut = A + sign-extend

(IR[15-0]) if (A == B) then PC = ALUOut PC = PC[31-28] || (IR[25-0] << 2)

Memory access or

R-type completion

Reg[IR[15-11]] = ALUOut

Load: MDR = Memory[ALUOut]

orStore: Memory[ALUOut] = BMemory read comple-

Figure 2.20: Summary of the multicycle steps [PaHe98] p 389

2.3.3 Defining the Control by a Finite State Machine

In the single step implementation the control was defined by simple truth tables that set the control signals depending on the instruction.

This does not work for a mulitcycle datapath.

The control is more complex, because it must specify both the signals to be set

in any step and the next step in the sequence.

Therefore a finite state machine is used.

Figure 2.21 shows the finite state machine for the control of the multicycle datapath implementation.

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2.3 Defining the Control by a Finite State Machine

The setting of the control signals is also shown in figure 2.21.

All unused signals have to be deasserted or keep their value during the next states until they are set again.

All signal settings in all states is shown in figure 2.22.

Figure 2.21: Complete finite state machine control [PaHe98] p 396

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2.3 Defining the Control by a Finite State Machine

Figure 2.22: Setting of Control Signals

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3 Design Tasks

3 Design Tasks

• Block Diagram of first hierarchy levels

• Register Transfer Level Models implemented in pure VHDL

• VHDL Testbench of important RTL Models

• Implementation in Altera Target Technology

• Prototype Testing

• Simulation Tool: ModelSim

• Synthesis Tool: Altera Quartus

• Milestone Presentations

• Design Project Report in OpenOffice Document Format

• Design Directory Structure is mandatory according to the following table:

toplevel Root directory for a VHDL design project

toplevel/src directory for VHDL source code

toplevel/work directory for VHDL working library, contains compiled object code of

ModelSim VHDL compiler toplevel/simulation simulation results

toplevel/stimuli stimuli files of extended simulation runs should be stored in

this directory toplevel/pnr data produced after a place&route run can be found in this directory toplevel/scripts scriptfiles for automated batch processing of the design steps

should be placed here toplevel/log log files of the different design steps

toplevel/doc directory for project documentation, data sheets, etc.

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At the present time, the basic arithmetic operations add and sub and the logic operations and, or and slt can be applied to inputs The inputs are 32 bit wide

with type unsigned A detection of overflow or borrow is not supported at the ment.

mo-Department of Electrical Engineering

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4.1 Block Diagram

4.1.2 Block Diagram

Figure 4.1: ALU 1/3

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4.1 Block Diagram

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4.1 Block Diagram

Figure 4.3: ALU 3/3

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a_alu_behave.vhd VHDL Source Files Arithmetic-logic unit

t_alu.vhd VHDL Testbench File Testbench for single operationst_alu_fileio.vhd VHDL Testbench File Testbench using file I/O

Figure 4.4: Simulation Results of ALU

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4.2 Memory

4.2 Memory

4.2.1 Functional Description

Data is synchronously written to or read from the memory with a data bus width

of 32 bit The memory consists of four ram blocks with 8 bit data width each

A control signal enables the memory to be written, otherwise data is only read In order to store data to the memory the data word is subdivided into four bytes which are separately written to the ram blocks Vice versa, the single bytes are concatenated to get the data word back again.

At the moment, it is only possible to read and write data words An addressing of half-words or single bytes is not allowed In order to write or read data words, all ram blocks have to be selected Hence, the lowest two bit are not examined for chip-select logic.

Data is addressed by the MIPS-processor with an address width of 32 bit, while the address width of a ram block is 8 bit each All ram blocks are connected to

the same address, namely from mem_address(9 downto 2) Since we do not use

the full address width for addressing and chip selects, data words are addressed

by multiple addresses

Unfortunately, some problems occurred during simulation of the memory unit According to the MIPS design shown in literature [PaHe98], there should be implemented a memory unit with an unregistered output The Altera Quartus MegaWizard Plug-In Manager yielded a ram block with a synchronous output (a_ram_syn.vhd) , although the output was defined as unregistered

In order to get an unregistered memory output, another ram block was defined in VHDL code (a_ram_rtl.vhd) There, the output directly yields the data being addressed by the unregistered input address Unfortunately, the synthesizer does not support memory initialisation files in the RTL-code for setting data to the

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4.2 Simulation Results

Figure 4.7 shows the simulation results with unregistered output Note that the simulation contains unknown values, because the memory initialisation files are not supported.

Figure 4.7: Simulation Results of Memory (unregistered outputs)

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