magma training talus design

Magma Talus Design Training Agenda Timing Analysis, Placement, and Timing Optimization Import Lib and RTL - Reading in Library Volcanos - Reading in HDL fix rtl - High-Level Synthesi

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Magma Talus Design Training Agenda

Timing Analysis, Placement, and Timing Optimization

Import Lib and RTL

- Reading in Library Volcanos

- Reading in HDL fix rtl

- High-Level Synthesis

- Data Path Generation fix netlist

- Area Optimization

- Initial HyperCell Mapping

LAB: RTL Import fix netlist

fix time

- Timing-Driven Optimization Static Timing Analysis

- Timing Analysis and Debug in Magma

- Check Timing and Reporting/Timing Viewer

LAB: Fix Time

Import Library and RTL

Import lib & RTL

Import lib & RTL

Magma Design Flow

RTL OptimizationRTL Import

Area Optimization

Ti i O ti i ti

You are here

fix rtlfix netlist

Iterate as Needed

DevelopConstraints

DFT InsertionTiming Optimization

Floorplanning

HyperCell Domain Real Cell Domain

fix time

fix planfix cell (early CTS)

Physical Synthesis

Clock Tree Synth fix clock (opto CTS)

Needed

Report Analysis

Final mode optimization fix optimize

Talus COreTMTechnology

Concurrent timing optimization throughout the flow

Import lib & RTL

Importing the Library

• Import previously prepared library Volcano database

import volcano stdcell_lib_name.volcano -object $l

• After importing the technology Volcano set $l if you haven’t After importing the technology Volcano, set $l, if you haven t

already

set l /stdcell_lib_name

• Set the target library configuration

• Set the RTL search path

• For Verilog 2000 designs, enable support

Import lib & RTL

• m is the top-level model name

• l is the name of the standard cell library

• lr is the name of the RAM library

Magma Confidential - 5

y

• You can use any name for the secondary libraries Talus Design assumes

that $l points to your standard cell library

• These variables are used by almost every Magma command

It is important to define this early in the flow.

Import lib & RTL

Compatible RTL Coding

• Magma RTL synthesis is

• Completely compatible with industry-standard coding style

• Talus Design fully supports the Synopsys coding style, commonly used

pragmas, instantiated DesignWare components, and hard macros

• Magma does not support design constraints as pragmas (dont_touch,

dont_use, and so forth)

• Language-neutral for Verilog and VHDL

• Mix both VHDL and Verilog blocks within a single design anywhere in the

hierarchy

• Verilog 95/2000 and VHDL-87/93 System Verilog 2005 support Verilog 95/2000 and VHDL 87/93 System Verilog 2005 support

Import lib & RTL

Pragma Support

• Talus Design interprets the commonly used Synopsys

pragmas (directives) for both VHDL and Verilog.

• Translate_off/on case (Sel) //synopsys full_case

• Full/parallel case

• Function map to module

• Asynchronous set and reset

• The following syntax is supported:

• -pragma or -synopsys for VHDL designs

_2'b00 : D_Out = A;

2'b01 : D_Out = B;

2'b10 : D_Out = C;

endcase

Magma Confidential - 7

• //synthesis or //synopsys for Verilog designs

• You can also use config rtl directive to specify compiler

directives

Import lib & RTL

Third Party Module Support

• Talus Design supports direct instantiation of the commonly

used Synopsys DesignWare components

DW01_add, DW01_sub, DW01_addsub, DW01_csa, DW_square, DW01_dec,

DW01_inc, DW01_absval, DW01_incdec, DW01_ash, DW01_bsh,

DW shifter DW01 cmp2 DW01 cmp6 DW01 decode DW01 binenc

DW_shifter, DW01_cmp2, DW01_cmp6, DW01_decode, DW01_binenc,

DW01_prienc, DW01_mux_any, DW01_satrnd, DW02_prod_sum, DW02_sum,

DW02_mult_2_stage, DW02_mult_3_stage, DW02_mult_4_stage,

DW02_mult_5_stage, DW02_mult_6_stage, DW02_mult, DW02_div_rem,

DW02_divide, DW02_rem, DW02_mac, DW03_bict_dcnto,

DW03_bict_scnto, DW03_updn_ctr, DW03_bictr_decode

….the list is constantly growing…

See Appendix slide in this module for current component list

• DW01_add #(8,8) U1 (.A (in1), B (in2), CI (cin), SUM (sum), CO

Import lib & RTL

Importing RTL Into Talus

• Use the following command to import RTL into Talus:

import rtl -analyze [-vhdl|-verilog] -include directory_name file_list

Analyzes the RTL file but does not perform elaboration

Indicates that RTL files are Verilog

-analyze

verilog Indicates that RTL files are Verilog

Defines `ifdef variable names in Verilog

Specifies the name of the directory with any include files referenced

in the Verilog RTL

Indicates the RTL files are VHDL

For VHDL designs, allows source files to be specified in any order

Specifies to use VHDL-87 mode rather than VHDL-93 (VHDL-93 is

import rtl -analyze –verilog \

-include /include_dir chip.v cntr.v interface.v

p

Specifies the work library The default is work

Specifies a list of all the RTL files to import

-lib

file_list

Import lib & RTL

run rtl elaborate -vhdl -verilog [-parameters param_name] \

-architecture arch_name -lib -add_dc -case top_model_name

Elaborating the Design

• After analyzing the RTL, elaborate the design.

Performs elaboration on a Verilog design

Specifies the library The default is work

Specifies default architectures for datapath elements (auto, small, fast) Overrides default parameters or generic values of the module

Performs elaboration on a VHDL design Specifies an architecture for VHDL designs Handles how the case of names are translated for VHDL designs (upper,lower, preserve)

• During elaboration, the design is loaded into the Talus /work library

unless you specify the -lib option

• Example: run rtl elaborate chip

(upper,lower, preserve)

Import lib & RTL

Useful Configuration Settings

• Set the target library configuration

config rtl targetlib $l

• For designs that contain macros within the RTL, this is necessary to resolve

and bind all cells; otherwise you will have unresolved references

• Set the RTL search path

config rtl searchpath

• For designs that contain extensive directory structures, this makes scripts

much cleaner (You do not need to specify the full path for each RTL file)

• Enable Verilog 2000 support

Import lib & RTL

Importing RTL: Resulting Directories

• After import rtl, two Talus libraries called /work and

/macro_lib are created

• The Talus library /work contains the design data after elaboration

• The Talus /macro_lib library contains the basic architecture for data

path components

• A UNIX directory called /work is created under the directory

where Talus was started

• The work directory contains intermediate binary files (.mod for Verilog

modules, ent, pkg, and cnf for VHDL) created after import rtl

modules, ent, pkg, and cnf for VHDL) created after import rtl

• These binaries are loaded into the Talus work library /work during

elaboration

Import lib & RTL

Importing RTL – Mixed Language

import rtl -analyze -vhdl \

reg_file.vhd \alu.vhd \

pads.v core.v interface.v

Match the language

to the top-level design

Import lib & RTL

Supported DW Components – Talus Design

Import lib & RTL

fix rtl

Magma Design Flow

RTL OptimizationRTL Import

DevelopConstraints

DFT InsertionTiming Optimization

Floorplanning

HyperCell Domain Real Cell Domain

fix time

fix planfix cell (early CTS)

fix clock (opto CTS)

Physical Synthesis

Clock Tree Synth

Needed

Report Analysis

Final mode optimization

Talus COreTMTechnology

Concurrent timing optimization throughout the flow

fix rtl

RTL Optimization

• fix rtl performs high-level optimization including:

• Constant propagation and dead code removal

• Clockgating for power (if enabled) g g p ( )

• Creation of optimized structures for arithmetic logic

• Flattening of small user modules (if enabled)

• Mapping design to primitives (equations)

fix rtl model

fix rtl

RTL Optimization Config Settings: Clockgating

• Support for advanced and hierarchical clockgating

• Two methods to control insertion of clockgating logic

• To enable clockgating on the entire design

\config rtl clockgate [ on|off] \

[-style latched|combinational] [-min_bits integer] \

[-test before|after]

config rtl clockgate [on|off] [-integrated $l/entity] \

[-min_bits integer]

• To enable clockgating on the specified model or hierarchy only

force rtl clockgate model [on|off] \

Magma Confidential - 5

[-test before|after] [-hier]

• -hier – Traverses the hierarchy starting from the specified model

• -min_bits – The default is 4

fix rtl

RTL Optimization Config Settings: Clockgating

Tool detects synchronously enabled RTL

registers and synthesizes to simple

D-type registers with a gated clock

CLOCK

OUT

CLOCK TEST

latch ENA

TEST

fix rtl

RTL Optimization Config Settings: Clockgating

(contd)

• Select between combinational and latched gating to control

the position of test OR gate

config rtl clockgate -test before

CLOCK

D Q G

latch ENA

TEST

TEST

config rtl clockgate -test after

Magma Confidential - 7

CLOCK

D Q G

latch ENA

fix rtl

RTL Optimization Settings: Clockgating With ICG

• Same functionality as discrete cell clockgating

• Minimizes risk of clock skew between the latch and clock signal

• Easier to route (fewer total pins)

• Integrated Clock Gates are fully supported during synthesis and DFT

• The test mode pins are tied low when introduced; they are connected to scan

enable during DFT

• ICG cells are provided by the library vendor

dout din

D ECK

ICG EN

D Q

Test

fix rtl

RTL Opt Settings: Data-Path Optimization

• Talus optimizes arithmetic components by using derived function

• This can be controlled by these commands (default is on)

config rtl sharing on|off|single|expr

force rtl sharing $m on|off|single|expr

• Scope is module for Verilog, architecture for VHDL

fix rtl

• Talus synthesizes arithmetic expression by merging and

creating Wallace tree or Carry Skip Ahead (CSA) adder

RTL Opt Settings: Data-Path Optimization (contd)

a b c d e f

a b c d e f

Wallace tree

+

• Formal tool might need advance features to verify it

• To control it, use config rtl merging on | off

fix rtl

RTL Opt Settings: Data Path Architectures

• Talus creates and selects data-path components from a wide range

available in Magma; you can also control the selection

• While elaborating

run rtl elaborate object [-arithmetic auto|fast|small]

• To enable change of architecture in physical synthesis

config rtl datapath physical on|off

• To select implementation type

config rtl datapath option_name value [-list]

Magma Confidential - 11

cpa_arch mult_arch

fcla, mcla, ecla, ripple booth, nonbooth, auto

mux_arch mux, invmux, andor, invandor, auto

mux_order ascend, descend, delay

wt_opt area, delay

wt_int_trunc on, off

Option Name Value

fix rtl

RTL Opt Settings: Partial Flattening Autoflatten

• Talus creates hierarchy to handle the data path It is removed in the latter

part of the flow But the user hierarchy is preserved.

• You can allow RTL flattening of small modules to increase optimization

config rtl autoflatten [-bitwidth_threshold integer]

[-min integer] [-max integer] [-comb] [-rtl]

D Q

Module A Module B Module C

Module D

D Q Flattened Module C

Module D

• Prevent flattening of models using the force keep command, but use it

sparingly because this affects QOR.

• To generate a report of modules that can be flattened, use report rtl

autoflatten.

fix rtl

Creating Domains

• To create a domain:

• Execute the data create domain command

• Associate cells (logical hierarchy) ( g y)

• Associate floorplans (physical hierarchy)

• Create nets (for power and ground)

• Re-initialize HyperCell models

• Domain cells are cells attached to a domain from a

hierarchical module

Magma Confidential - 13

• Use data attach to associate cells with domains:

data attach $m/my_cell cell_domain $m/my_domain

• Domains contain the power and ground nets

fix rtl

Basic Domain Creation Procedure

• Create the domain

data create domain

• Create domain nets

force domain net

• Set the domain PVT settings

• Set the domain PVT settings

force domain [process, temperature, voltage]

• Set the library rail associations

force domain rail

• Attach cells/floorplans to a domain

force domain net

• Create domain-specific constraints (if needed)

• For example, domain specified hiding w/ force hide -domain

• Apply the domain

• Apply the domain

run domain apply

• Re-extract HyperCells

run prepare hyper

fix rtl

Domain Application

• A domain is ‘applied’ via the run domain apply -mode

apply command

• When a domain is applied the domain power and ground pp p g

nets are created within the logical hierarchy in accordance

with the domain setup (domain net to domain rail mappings),

and any user specific overrides specified via the force

domain pin command

• The application of the domain only causes the logical nets to

be created and for the design to become PG connected

Magma Confidential - 15

be created and for the design to become PG connected

• Domain application will not affect the timing or derating

characteristics of the domain

fix rtl

Example Script for Creating a Domain

proc createdomain {

global m l

data create domain $m dom1

force domain process $m/domain:dom1 1.0 -case best

force domain process $m/domain:dom1 1.0 -case worst

Advanced

force domain temperature $m/domain:dom1 -40 -case best

force domain temperature $m/domain:dom1 125 -case worst

force domain net $m/domain:dom1 VDD power -primary -supply_type constant

force domain voltage $m/domain:dom1 VDD 1.1 -case best

force domain voltage $m/domain:dom1 VDD 0.9 -case worst

force domain rail $m/domain:dom1 VDD $l MAGMA_DEFAULT_POWER_RAIL

force domain net $m/domain:dom1 VSS ground -primary -supply_type constant

force domain voltage $m/domain:dom1 VSS 0.00 -case best

force domain voltage $m/domain:dom1 VSS 0.00 -case worst

force domain rail $m/domain:dom1 VSS $l MAGMA_DEFAULT_GROUND_RAIL

}

• A more sophisticated version of this script can be found in the lab files

fix rtl

Snap Procedure to Create Initial Domain

• Combine the procedure from the previous foil with a snap

procedure

• Use run domain apply -mode uniquify after the domain is created

• Re-extract HyperCells with run prepare hyper after run domain

Multi-Domain Flow Example

• Create the primary domain

data create domain $m top_domain

• Create the secondary domains

data create domain $m sub1_dom

• Specify domain parameters

force domain net, force domain process, force domain temperature, force domain voltage

• Specify domain specific hiding

force hide object –domain domain

on a per domain basis.

• Specify library lib_groups to be associated with a domain.

force derate method nearest/user force delay lib_group -domain

fix rtl

Cell Domain and Floorplan Associations

• If all domains are created in a common scope, for example $m, the cells need to

be associated with these domains, using data attach Domain and floorplan relations remain the same

before and after flattening

data create domain $m top_dom data create domain $m sub1_dom data create domain $m sub2_dom data attach $m/sub1 cell_domain $m/domain:sub1_dom data attach $m/sub1 cell_domain $m/domain:sub1_dom

• Alternatively the domains can be created directly on models.

• During flattening the domain information is preserved, and

re-Magma Confidential - 19

data create domain $m top_dom

data create domain /work/sub1/sub1 sub1_dom

data create domain /work/sub2/sub2 sub2_dom

rooted at the point of flattening.

• Post flattening domain and floorplan relations are the

same as with the first method

fix rtl

Floorplanning and run domain apply

• Create floorplans, and cell/domain/floorplan associations.

data create floorplan $m/domain:top_dom TOP_FP data create floorplan $m/domain:sub1_dom SUB1_FP data attach $m2 cell_floorplan $m/floorplan:SUB1_FP data create floorplan $m/domain:sub2_dom SUB2_FP data attach $m cell floorplan $m/floorplan:SUB2 FP

sub1

($m2)

top ($m)

top

data attach $m cell_floorplan $m/floorplan:SUB2_FP

• The domains have the following domain net definitions.

force domain net $m/domain:top_dom VDD power –primary force domain net $m/domain:top_dom VDDH1 power force domain net $m/domain:top_dom VDDH2 power force domain net $m/domain:top_dom GND ground –primary force domain net $m/domain:sub1_dom VDDH1 power –primary force domain net $m/domain:sub1_dom VDDH2 power force domain net $m/domain:sub1_dom GND ground –primary force domain net $m/domain:sub2_dom VDDH2 power –primary force domain net $m/domain:sub2 dom GND ground –primary

sub1

sub2

($m3)

force domain net $m/domain:sub2_dom GND ground primary

• report object $m/sub1/OPcache_reg[0]

CELL m_sub/OPcache_reg[0] <bound> /tcbn90g/DFCNQ/DFCNQ_SUPER PIN VSS other () [OPcache_reg[0]]

PIN VDD other () [OPcache_reg[0]]

• run domain apply $m -create_mpins

sub2

$m/domain:top_dom

fix netlist

Magma Design Flow

RTL OptimizationRTL Import

Area Optimization

Ti i O ti i ti

You are here

fix rtlfix netlist

Iterate as Needed

DevelopConstraints

DFT InsertionTiming Optimization

Floorplanning

HyperCell Domain Real Cell Domain

fix time

fix planfix cell (early CTS)

Physical Synthesis

Clock Tree Synth fix clock (opto CTS)

Needed

Report Analysis

Final mode optimization fix optimize

Talus COreTMTechnology

Concurrent timing optimization throughout the flow

fix netlist

Area Optimization Overview

[-effort low | medium | high] [-parallel launch_spec]

• Boolean logic area optimization

• Final product is a netlist of HyperCell abstracts for a design

with the least possible area

fix netlist

Area Optimization Settings: Scan Considerations

• Use the -scan option if you are going to insert scan

• The -scan option changes all flip-flops to scan flip-flops

• SE pin is connected to ground, while SI pin is looped to Q S p s co ected to g ou d, e S p s ooped to Q

• Required procedure for -scan option:

• Ensure that scan flip-flops exist in library

report dft scan cell $m -lib

• Define the scan style

force dft scan style $m muxed_flip_flop

• Need to define scan style even if library lacks nonscan flip-flops

Magma Confidential - 5

Need to define scan style even if library lacks nonscan flip flops

• If some flip-flops have both scan and nonscan, and some

have only scan, hide all nonscan flip-flops to enable tool to

select from all the variations of scan flip-flops

fix netlist

Area Optimization Settings: QOR Considerations

• Area optimization stops at module boundary

• For better area QOR, flatten non-timing-critical blocks

data flatten /work/moduleA/moduleA

data flatten $m/moduleB_inst3

• To prevent all flattening of a particular module use

force keep /work/moduleB/moduleB

• To retain netlist hierarchy of a particular module use

force maintain /work/moduleB/moduleB

f

• If design is timing critical, override area optimization steps,

which create more levels of logic:

force gate opt_mode object delay/area -hier

• This can be done for the whole design or part of it

fix netlist

Area Optimization Settings: QOR Considerations

(contd)

• For custom-designed blocks (such as data paths or control

logic), optimization steps can be skipped to preserve

redundant structures

• To prevent area optimization on a given block

force gate independent /work/moduleC/moduleC 0 -hier

• Specify a non-default number of literals for optimization partitioning

• For precompiled blocks, area optimization can be skipped

force keep /work/precompiled/precompiled -content

Magma Confidential - 7

• Use the strategy that is best suited for your design

fix netlist

Area Optimization Settings: Hierarchy

• Talus provides control over preserving cells and hierarchy in

the flow

• Preserve specific instance that might be used later in flow p g

(defining clock, scan control, and so on)

force keep /work/clkcntl/clkcntl/inst_clk_div

• Prevent an instance from being mapped to a different drive

cell

force keep /work/clkcntl/clkcntl/inst_clk_div -model

• Launches a set of slaves for DPX processing

run parallel connection launch launch_spec \

[-lifetime lifetime] [-group group] [-port port] \

[-directory directory] [-nowait]

• Performs DPX fix netlist

run parallel netlist model lib [-verbose] [-cpu] \

[-effort ] [-scan ]

Magma Confidential - 9

[ effort ] [ scan ]

• Closes all DPX connections

run parallel connection close

fix netlist

Lab 1: RTL Import, Area Optimization

• In this lab, you will:

• Import Verilog HDL

• Elaborate the design g

• Perform area-based HyperCell optimization

• Expected time: 30 – 60 mins

Magma Confidential - 11

Appendix:

fix netlist

What’s a Literal?

• Literal count measurement

• N-input AND gate => (N-1) 2-input gates

1+2+4+ … + N/2 ≈ N-1

• (#literals-1) ≈ number of 2-input gates

required to implement the factored form

assuming a log-based decomposition

Constraints for Timing Optimization

Timing Constraints

Agenda

• Define paths

• Define clock domains

• Latency and Margin

• Latency and Margin

• Define I/O timing

• Define constants

• Constant propagation

• Define timing exceptions

• Appendix: PLL Constraints & Multi-Mode Analysis

Timing Constraints

Magma Design Flow

fix rtlfix netlist

DevelopConstraints You are here

HyperCell Domain Real Cell Domain

Clock Tree Synth

fix cell (early CTS)

fix clock (opto CTS)

Report Analysis

Talus COreTMTechnology

Concurrent timing optimization throughout the flow

Logi c Logi

c

Check Delay

On-Chip Latency

I/O Latency

I/O

Latency

Margin Margin Margin

Defining Magma Constraints

• Specifying clocks, skew and

jitter

force timing clock

• Specifying absolute inputs and outputs

force timing arrivalforce timing margin

• Specifying clock latency

force timing latency

• Specifying relative inputs and

force timing required

• Specifying false and multicycle paths

force timing falseforce timing multicycle

outputs

force timing delay

force timing check

• Breaking timing arcs

force timing break

[-slew slew] [-virtual] [-name name] [-generated] \

[-inverted] [-divider float] [-edges edge list] \

[-shifts shift time list] [-source node] \

[-context top model] [-pullup cell] [-pushdown] \

[-mode mode_list] [-master_clock clock_name] \

Clock Specification (cont.)

• -waveform – This can be a complex value consisting of the

rise and fall time The default value is

{-rise 0 -fall period / 2}

• -slew – This can be a complex value consisting of the rise

and fall time The default value is {-rise 0 -fall 0}

• -virtual – Indicates that the clock is virtual The node

specified cannot exist in the design and the -name option

cannot be used

• Use virtual clocks for flexibility with unusual requirements, like DDR

(Double Data Rate)

Timing Constraints

Clock Specification (cont.)

• -name – A name to use for the clock

• -generated – Indicates that this clock is to be derived from a

previously defined clock source

• -source – The source clock for a generated clock

• -divider – Scales the period of the source clock by the

specified number

Magma Confidential - 9

Timing Constraints

Options Common to Several Commands

• -context top_model – The name of the top model

associated with all nodes specified in a timing constraint

• -mode mode list – The list of timing analysis modes in _ g y

which the constraint is active

• Create modes with force timing mode model {mode_list} -create

• -pullup cell – The name of the cell from which the constraint

was pulled up Use this option only for constraints created by

the data pullup timing command

• -pushdown – Indicates that this command was created by

the data pushdown timing command Changing or deleting

commands with this option invalidates the pushed-down

timing budget

Timing Constraints

Clock Examples

• Define a clock named control_clk on model pin $m/mpin:clk

with a period of 5 ns

force timing clock $m/mpin:clk 5n -name control_clk

• Define a clock on model pin $m/tclock with a period of 5 ns, a

rise time at 1 ns, and a fall time at 3 ns, with a slew of 30 ps

force timing clock $m/tclock 5n -waveform \

{-rise 1n -fall 3n} -slew 30p

• Define a derived clock at model pin $m/v_clk based on the

source clock defined at $m/clk The derived clock has a

Magma Confidential - 11

source clock defined at $m/clk The derived clock has a

period of twice the source clock

force timing clock $m/v_clk -generated \

-source $m/clk -divider 2

Timing Constraints

Network, Source, and I/O Latency

• In Talus, the I/O latency is added to the arrival time

constraint of the chip inputs and subtracted from the setup

time constraint on the chip outputs

latency

I/O latency source latency

(off-chip)

Timing Constraints

Network, Source, and I/O Latency (contd)

• The source and I/O latency are persistent

• They remain as timing constraints throughout the entire flow

• Use them while in ideal mode in hierarchical designs to mimic

insertion delays in neighboring blocks to avoid potential CTS problems

• The network latency value remains until the real clock tree is

inserted

• Before clock tree insertion, the network latency is “ideal.” After clock

tree insertion, the network latency value is “computed” and is replaced

with the actual clock tree delay

• Use realistic network source and I/O latency values

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• Use realistic network, source, and I/O latency values

• This minimizes the timing impact when the network latency is changed

from “ideal” to “computed”

Timing Constraints

Latency

• force timing latency – Specifies different clock delay values

at various points for the same clock signal

force timing latency node latency \

[-type type][-context string] \

[-pullup cell] [-pushdown] [-mode mode_list]

• node – The name of the node where the latency is applied

(typically a clock node)

• latency – This can be a complex value that can include rise,

fall, min, max, best, and worst case values.

• -type – network, source, or io

Timing Constraints

Network, Source, and I/O Latency (contd)

• Define a source latency of 2 ns and I/O and network

latencies of 1 ns

force timing latency $m/mpin:clk 2n -type source

force timing latency $m/mpin:clk 1n -type network

force timing latency $m/mpin:clk 1n -type io

D Q

D Q

On-chip latency ( t k)

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Source latency

(off-chip)

2 ns Clock

I/O latency

• force timing margin – Defines clock skew and jitter

force timing margin type value

[-node node] [-from node] [-to node] \

[-jitter] [-from edge edge] \

[-to_edge edge] [-context top model] \

[-pullup cell] [-pushdown] [-mode mode_list]

• type –Specifies whether the margin is used under setup or hold

analysis Valid values are setup and hold.

• value – The value of the margin

• -node – The name of the node (clock) that the margin is to be applied

• -jitter – Designates that the margin is to be treated as clock jitter If

this option is omitted, the margin is treated as skew