ia-32 intel® architecture software developer’s manual

Interrupt Handling with the Pentium 4 and Intel Xeon Processors.. Selecting Memory Types for Pentium 4, Intel Xeon, and Pentium® III Processors.. New Features Incorporated in the Local A

Software Developer’s

Manual

Volume 3: System Programming Guide

NOTE: The IA-32 Intel Architecture Developer’s Manual consists of three

books: Basic Architecture, Order Number 245470-007; Instruction Set Reference Manual, Order Number 245471-007; and the System

Programming Guide, Order Number 245472-007.

Please refer to all three volumes when evaluating your design needs

2002

purpose, merchantability, or infringement of any patent, copyright or other intellectual property right Intel products are not intended for use in medical, life saving, or life sustaining applications

Intel may make changes to specifications and product descriptions at any time, without notice

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or

“undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them

Intel’s IA-32 Intel® Architecture processors (e.g., Pentium® 4 and Pentium® III processors) may contain design defects or errors known as errata Current characterized errata are available on request.

Intel, Intel386, Intel486, Pentium, Intel Xeon, Intel NetBurst, MMX, Intel Celeron, and Itanium are trade

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

P.O Box 7641

Mt Prospect IL 60056-7641

CHAPTER 1

ABOUT THIS MANUAL

1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL 1-1

DEVELOPER’S MANUAL, VOLUME 3: SYSTEM PROGRAMMING GUIDE 1-2

DEVELOPER’S MANUAL, VOLUME 1: BASIC ARCHITECTURE 1-4

DEVELOPER’S MANUAL, VOLUME 2: INSTRUCTION SET REFERENCE 1-51.5 NOTATIONAL CONVENTIONS 1-61.5.1 Bit and Byte Order 1-61.5.2 Reserved Bits and Software Compatibility 1-61.5.3 Instruction Operands 1-71.5.4 Hexadecimal and Binary Numbers 1-81.5.5 Segmented Addressing 1-81.5.6 Exceptions 1-91.6 RELATED LITERATURE 1-9

CHAPTER 2

SYSTEM ARCHITECTURE OVERVIEW

2.1 OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE 2-12.1.1 Global and Local Descriptor Tables 2-32.1.2 System Segments, Segment Descriptors, and Gates 2-32.1.3 Task-State Segments and Task Gates 2-42.1.4 Interrupt and Exception Handling 2-42.1.5 Memory Management 2-52.1.6 System Registers 2-52.1.7 Other System Resources 2-62.2 MODES OF OPERATION 2-62.3 SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER 2-72.4 MEMORY-MANAGEMENT REGISTERS 2-102.4.1 Global Descriptor Table Register (GDTR) .2-102.4.2 Local Descriptor Table Register (LDTR) 2-112.4.3 IDTR Interrupt Descriptor Table Register 2-112.4.4 Task Register (TR) 2-112.5 CONTROL REGISTERS 2-122.5.1 CPUID Qualification of Control Register Flags 2-182.6 SYSTEM INSTRUCTION SUMMARY 2-182.6.1 Loading and Storing System Registers 2-202.6.2 Verifying of Access Privileges 2-212.6.3 Loading and Storing Debug Registers .2-212.6.4 Invalidating Caches and TLBs .2-212.6.5 Controlling the Processor 2-222.6.6 Reading Performance-Monitoring and Time-Stamp Counters 2-222.6.7 Reading and Writing Model-Specific Registers 2-23

CHAPTER 3

PROTECTED-MODE MEMORY MANAGEMENT

3.1 MEMORY MANAGEMENT OVERVIEW 3-13.2 USING SEGMENTS 3-33.2.1 Basic Flat Model 3-33.2.2 Protected Flat Model 3-33.2.3 Multi-Segment Model 3-53.2.4 Paging and Segmentation 3-63.3 PHYSICAL ADDRESS SPACE 3-63.4 LOGICAL AND LINEAR ADDRESSES 3-63.4.1 Segment Selectors 3-73.4.2 Segment Registers 3-83.4.3 Segment Descriptors 3-93.4.3.1 Code- and Data-Segment Descriptor Types .3-133.5 SYSTEM DESCRIPTOR TYPES 3-143.5.1 Segment Descriptor Tables 3-153.6 PAGING (VIRTUAL MEMORY) OVERVIEW 3-173.6.1 Paging Options 3-183.6.2 Page Tables and Directories 3-193.7 PAGE TRANSLATION USING 32-BIT PHYSICAL ADDRESSING 3-203.7.1 Linear Address Translation (4-KByte Pages) 3-203.7.2 Linear Address Translation (4-MByte Pages) 3-213.7.3 Mixing 4-KByte and 4-MByte Pages 3-223.7.4 Memory Aliasing 3-233.7.5 Base Address of the Page Directory 3-233.7.6 Page-Directory and Page-Table Entries 3-233.7.7 Not Present Page-Directory and Page-Table Entries 3-28

3.8.1 Linear Address Translation With PAE Enabled (4-KByte Pages) 3-293.8.2 Linear Address Translation With PAE Enabled (2-MByte Pages) 3-303.8.3 Accessing the Full Extended Physical Address Space With the

Extended Page-Table Structure 3-313.8.4 Page-Directory and Page-Table Entries With Extended Addressing

Enabled 3-31

MECHANISM 3-343.10 MAPPING SEGMENTS TO PAGES 3-363.11 TRANSLATION LOOKASIDE BUFFERS (TLBS) 3-37

CHAPTER 4

PROTECTION

PAGE-LEVEL PROTECTION 4-24.3 LIMIT CHECKING 4-54.4 TYPE CHECKING 4-6

4.8 PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL

BETWEEN CODE SEGMENTS 4-124.8.1 Direct Calls or Jumps to Code Segments 4-134.8.1.1 Accessing Nonconforming Code Segments 4-144.8.1.2 Accessing Conforming Code Segments 4-154.8.2 Gate Descriptors 4-164.8.3 Call Gates 4-174.8.4 Accessing a Code Segment Through a Call Gate 4-184.8.5 Stack Switching 4-214.8.6 Returning from a Called Procedure 4-244.8.7 Performing Fast Calls to System Procedures with the SYSENTER and

SYSEXIT Instructions4-25

4.9 PRIVILEGED INSTRUCTIONS 4-264.10 POINTER VALIDATION 4-274.10.1 Checking Access Rights (LAR Instruction) 4-274.10.2 Checking Read/Write Rights (VERR and VERW Instructions) 4-284.10.3 Checking That the Pointer Offset Is Within Limits (LSL Instruction) 4-294.10.4 Checking Caller Access Privileges (ARPL Instruction) 4-294.10.5 Checking Alignment 4-314.11 PAGE-LEVEL PROTECTION 4-314.11.1 Page-Protection Flags 4-324.11.2 Restricting Addressable Domain 4-324.11.3 Page Type 4-334.11.4 Combining Protection of Both Levels of Page Tables 4-334.11.5 Overrides to Page Protection 4-334.12 COMBINING PAGE AND SEGMENT PROTECTION 4-34

CHAPTER 5

INTERRUPT AND EXCEPTION HANDLING

5.1 INTERRUPT AND EXCEPTION OVERVIEW 5-15.2 EXCEPTION AND INTERRUPT VECTORS 5-25.3 SOURCES OF INTERRUPTS 5-25.3.1 External Interrupts 5-25.3.2 Maskable Hardware Interrupts 5-45.3.3 Software-Generated Interrupts 5-45.4 SOURCES OF EXCEPTIONS 5-55.4.1 Program-Error Exceptions 5-55.4.2 Software-Generated Exceptions 5-55.4.3 Machine-Check Exceptions 5-55.5 EXCEPTION CLASSIFICATIONS 5-65.6 PROGRAM OR TASK RESTART 5-65.7 NONMASKABLE INTERRUPT (NMI) 5-85.7.1 Handling Multiple NMIs 5-85.8 ENABLING AND DISABLING INTERRUPTS 5-85.8.1 Masking Maskable Hardware Interrupts 5-85.8.2 Masking Instruction Breakpoints 5-95.8.3 Masking Exceptions and Interrupts When Switching Stacks 5-10

5.10 INTERRUPT DESCRIPTOR TABLE (IDT) 5-115.11 IDT DESCRIPTORS 5-125.12 EXCEPTION AND INTERRUPT HANDLING 5-145.12.1 Exception- or Interrupt-Handler Procedures 5-14

5.12.1.1 Protection of Exception- and Interrupt-Handler Procedures 5-165.12.1.2 Flag Usage By Exception- or Interrupt-Handler Procedure 5-175.12.2 Interrupt Tasks .5-185.13 ERROR CODE 5-195.14 EXCEPTION AND INTERRUPT REFERENCE 5-20

Interrupt 0—Divide Error Exception (#DE) 5-22Interrupt 1—Debug Exception (#DB) .5-23Interrupt 2—NMI Interrupt 5-24Interrupt 3—Breakpoint Exception (#BP) 5-25Interrupt 4—Overflow Exception (#OF) 5-26Interrupt 5—BOUND Range Exceeded Exception (#BR) 5-27Interrupt 6—Invalid Opcode Exception (#UD) 5-28Interrupt 7—Device Not Available Exception (#NM) 5-30Interrupt 8—Double Fault Exception (#DF) 5-32Interrupt 9—Coprocessor Segment Overrun .5-34Interrupt 10—Invalid TSS Exception (#TS) 5-35Interrupt 11—Segment Not Present (#NP) 5-37Interrupt 12—Stack Fault Exception (#SS) 5-39Interrupt 13—General Protection Exception (#GP) 5-41Interrupt 14—Page-Fault Exception (#PF) 5-44Interrupt 16—x87 FPU Floating-Point Error (#MF) 5-47Interrupt 17—Alignment Check Exception (#AC) 5-49Interrupt 18—Machine-Check Exception (#MC) 5-51Interrupt 19—SIMD Floating-Point Exception (#XF) 5-53Interrupts 32 to 255—User Defined Interrupts 5-56

CHAPTER 6

TASK MANAGEMENT

6.1 TASK MANAGEMENT OVERVIEW 6-16.1.1 Task Structure 6-16.1.2 Task State 6-26.1.3 Executing a Task 6-36.2 TASK MANAGEMENT DATA STRUCTURES 6-46.2.1 Task-State Segment (TSS) 6-46.2.2 TSS Descriptor 6-76.2.3 Task Register 6-86.2.4 Task-Gate Descriptor 6-96.3 TASK SWITCHING 6-126.4 TASK LINKING 6-166.4.1 Use of Busy Flag To Prevent Recursive Task Switching 6-176.4.2 Modifying Task Linkages 6-186.5 TASK ADDRESS SPACE 6-186.5.1 Mapping Tasks to the Linear and Physical Address Spaces .6-196.5.2 Task Logical Address Space 6-20

CHAPTER 7

MULTIPLE-PROCESSOR MANAGEMENT

7.1 LOCKED ATOMIC OPERATIONS 7-27.1.1 Guaranteed Atomic Operations 7-37.1.2 Bus Locking 7-37.1.2.1 Automatic Locking 7-47.1.2.2 Software Controlled Bus Locking 7-47.1.3 Handling Self- and Cross-Modifying Code 7-67.1.4 Effects of a LOCK Operation on Internal Processor Caches 7-77.2 MEMORY ORDERING 7-77.2.1 Memory Ordering in the Pentium® and Intel486 Processors 7-87.2.2 Memory Ordering Pentium® 4, Intel® Xeon™, and P6 Family Processors 7-87.2.3 Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and

P6 Family Processors 7-107.2.4 Strengthening or Weakening the Memory Ordering Model 7-11

ENTRY CHANGES TO MULTIPLE PROCESSORS 7-137.4 SERIALIZING INSTRUCTIONS 7-147.5 MULTIPLE-PROCESSOR (MP) INITIALIZATION 7-157.5.1 BSP and AP Processors 7-167.5.2 MP Initialization Protocol Requirements and Restrictions for Intel Xeon

Processors 7-167.5.3 MP Initialization Protocol Algorithm for the Intel Xeon Processors 7-177.5.4 MP Initialization Example 7-187.5.4.1 Typical BSP Initialization Sequence 7-197.5.4.2 Typical AP Initialization Sequence 7-217.5.5 Identifying the Processors in an MP System 7-227.6 HYPER-THREADING TECHNOLOGY 7-237.6.1 Implementation of Hyper-Threading Technology in IA-32 Processors 7-237.6.2 Hyper-Threading Technology Architecture 7-247.6.2.1 IA-32 Architectural State of a Logical Processor 7-247.6.2.2 Local APIC Functionality 7-267.6.2.3 Memory Type Range Registers (MTRR) 7-267.6.2.4 Page Attribute Table (PAT) 7-277.6.2.5 Machine Check Architecture 7-277.6.2.6 Debug Registers and Extensions 7-277.6.2.7 Performance Monitoring Counters 7-287.6.2.8 IA32_MISC_ENABLE MSr 7-287.6.2.9 Memory Ordering 7-287.6.2.10 Serializing Instructions 7-287.6.2.11 Microcode Update Resources 7-287.6.2.12 Self Modifying Code 7-297.6.3 Implementation-Specific Facilities of IA-32 Processors with

Hyper-Threading Technology 7-297.6.3.1 Processor Caches 7-297.6.3.2 Processor Translation Lookaside Buffers (TLBs) 7-307.6.3.3 Thermal Monitor 7-307.6.4 External Signal Compatibility 7-307.6.4.1 STPCLK# 7-307.6.4.2 LINT0 and LINT1 Pins 7-317.6.4.3 A20M# Pin 7-317.6.5 Detecting Hyper-Threading Technology 7-31

7.6.6 Initializing IA-32 Processors With Hyper-Threading Technology 7-327.6.7 Executing Multiple Threads on an IA-32 Processor With

Hyper-Threading Technology 7-327.6.8 Handling Interrupts on an IA-32 Processor With

Hyper-Threading Technology 7-337.6.9 Management of Idle and Blocked Conditions 7-347.6.9.1 HLT Instruction 7-347.6.9.2 PAUSE Instruction 7-347.6.10 Identifying Logical Processors in an MP System .7-347.6.11 Required Operating System Support .7-407.6.11.1 Use the PAUSE Instruction in Spin-Wait Loops 7-407.6.11.2 Halt Idle Logical Processors 7-417.6.11.3 Guidelines for Scheduling Threads On Multiple Logical Processors 7-417.6.11.4 Eliminate Execution-Based Timing Loops 7-417.6.11.5 Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory 7-42

CHAPTER 8

ADVANCED PROGRAMMABLE

INTERRUPT CONTROLLER (APIC)

8.1 LOCAL AND I/O APIC OVERVIEW 8-18.2 SYSTEM BUS VS APIC BUS 8-5

8.4 LOCAL APIC 8-68.4.1 The Local APIC Block Diagram 8-68.4.2 Presence of the Local APIC 8-98.4.3 Enabling or Disabling the Local APIC 8-108.4.4 Local APIC Status and Location 8-118.4.5 Relocating the Local APIC Registers 8-118.4.6 Local APIC ID 8-118.4.7 Local APIC State 8-128.4.7.1 Local APIC State After Power-Up or Reset 8-128.4.7.2 Local APIC State After It Has Been Software Disabled 8-138.4.7.3 Local APIC State After an INIT Reset (“Wait-for-SIPI” State) 8-138.4.7.4 Local APIC State After It Receives an INIT-Deassert IPI 8-148.4.8 Local APIC Version Register 8-148.5 HANDLING LOCAL INTERRUPTS 8-158.5.1 Local Vector Table .8-158.5.2 Valid Interrupt Vectors 8-188.5.3 Error Handling 8-188.5.4 APIC Timer 8-208.5.5 Local Interrupt Acceptance 8-218.6 ISSUING INTERPROCESSOR INTERRUPTS 8-218.6.1 Interrupt Command Register (ICR) 8-218.6.2 Determining IPI Destination 8-278.6.2.1 Physical Destination Mode 8-27

8.8.1 Interrupt Handling with the Pentium 4 and Intel Xeon Processors 8-328.8.2 Interrupt Handling with the P6 Family and Pentium Processors 8-328.8.3 Interrupt, Task, and Processor Priority 8-348.8.3.1 Task and Processor Priorities 8-358.8.4 Interrupt Acceptance for Fixed Interrupts 8-368.8.5 Signaling Interrupt Servicing Completion 8-378.9 SPURIOUS INTERRUPT 8-38

8.10.1 Bus Message Formats 8-40

CHAPTER 9

PROCESSOR MANAGEMENT AND INITIALIZATION

9.1 INITIALIZATION OVERVIEW 9-19.1.1 Processor State After Reset 9-29.1.2 Processor Built-In Self-Test (BIST) 9-29.1.3 Model and Stepping Information 9-59.1.4 First Instruction Executed 9-69.2 X87 FPU INITIALIZATION 9-69.2.1 Configuring the x87 FPU Environment 9-69.2.2 Setting the Processor for x87 FPU Software Emulation 9-79.3 CACHE ENABLING 9-89.4 MODEL-SPECIFIC REGISTERS (MSRS) 9-89.5 MEMORY TYPE RANGE REGISTERS (MTRRS) 9-99.6 SSE AND SSE2 EXTENSIONS INITIALIZATION 9-9

9.7.1 Real-Address Mode IDT 9-109.7.2 NMI Interrupt Handling 9-10

9.8.1 Protected-Mode System Data Structures 9-129.8.2 Initializing Protected-Mode Exceptions and Interrupts 9-129.8.3 Initializing Paging 9-129.8.4 Initializing Multitasking 9-139.9 MODE SWITCHING 9-139.9.1 Switching to Protected Mode 9-149.9.2 Switching Back to Real-Address Mode 9-159.10 INITIALIZATION AND MODE SWITCHING EXAMPLE 9-169.10.1 Assembler Usage 9-189.10.2 STARTUP.ASM Listing 9-199.10.3 MAIN.ASM Source Code 9-289.10.4 Supporting Files 9-299.11 MICROCODE UPDATE FACILITIES 9-319.11.1 Microcode Update 9-319.11.2 Microcode Update Loader 9-349.11.2.1 Update Loading Procedure 9-359.11.2.2 Hard Resets in Update Loading 9-369.11.2.3 Update in a Multiprocessor System 9-369.11.2.4 Update Loader Enhancements 9-369.11.3 Update Signature and Verification 9-369.11.3.1 Determining the Signature 9-379.11.3.2 Authenticating the Update 9-37

9.11.4 Pentium 4, Intel Xeon, and P6 Family Processor Microcode

Update Specifications 9-389.11.4.1 Responsibilities of the BIOS 9-389.11.4.2 Responsibilities of the Calling Program 9-399.11.4.3 Microcode Update Functions 9-429.11.4.4 INT 15H-based Interface 9-429.11.4.5 Function 00H—Presence Test 9-439.11.4.6 Function 01H—Write Microcode Update Data 9-439.11.4.7 Function 02H—Microcode Update Control 9-479.11.4.8 Function 03H—Read Microcode Update Data 9-489.11.4.9 Return Codes 9-49

CHAPTER 10

MEMORY CACHE CONTROL

10.1 INTERNAL CACHES, TLBS, AND BUFFERS 10-110.2 CACHING TERMINOLOGY 10-410.3 METHODS OF CACHING AVAILABLE 10-510.3.1 Buffering of Write Combining Memory Locations 10-710.3.2 Choosing a Memory Type 10-810.4 CACHE CONTROL PROTOCOL 10-910.5 CACHE CONTROL 10-1010.5.1 Cache Control Registers and Bits 10-1010.5.2 Precedence of Cache Controls 10-1410.5.2.1 Selecting Memory Types for Pentium Pro and Pentium® II Processors .10-1510.5.2.2 Selecting Memory Types for Pentium 4, Intel Xeon, and

Pentium® III Processors 10-1610.5.2.3 Writing Values Across Pages with Different Memory Types .10-1710.5.3 Preventing Caching 10-1710.5.4 Disabling and Enabling the L3 Cache 10-1810.5.5 Cache Management Instructions .10-1810.6 SELF-MODIFYING CODE 10-19

10.8 EXPLICIT CACHING 10-2010.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) 10-2110.10 STORE BUFFER 10-2210.11 MEMORY TYPE RANGE REGISTERS (MTRRS) 10-2210.11.1 MTRR Feature Identification 10-2410.11.2 Setting Memory Ranges with MTRRs 10-2510.11.2.1 IA32_MTRR_DEF_TYPE MSR 10-2510.11.2.2 Fixed Range MTRRs 10-2610.11.2.3 Variable Range MTRRs 10-2710.11.3 Example Base and Mask Calculations 10-2910.11.4 Range Size and Alignment Requirement 10-3010.11.4.1 MTRR Precedences 10-3110.11.5 MTRR Initialization 10-31

10.12 PAGE ATTRIBUTE TABLE (PAT) 10-3710.12.1 Detecting Support for the PAT Feature 10-3810.12.2 IA32_CR_PAT MSR 10-3810.12.3 Selecting a Memory Type from the PAT 10-3910.12.4 Programming the PAT 10-4010.12.5 PAT Compatibility with Earlier IA-32 Processors 10-41

CHAPTER 11

INTEL MMX TECHNOLOGY SYSTEM PROGRAMMING

11.1 EMULATION OF THE MMX INSTRUCTION SET 11-111.2 THE MMX STATE AND MMX REGISTER ALIASING 11-111.2.1 Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on

the x87 FPU Tag Word 11-311.3 SAVING AND RESTORING THE MMX STATE AND REGISTERS 11-411.4 SAVING MMX STATE ON TASK OR CONTEXT SWITCHES 11-5

11.5.1 Effect of MMX Instructions on Pending x87 Floating-Point Exceptions 11-611.6 DEBUGGING MMX CODE 11-6

CHAPTER 12

SSE AND SSE2 SYSTEM PROGRAMMING

12.1.1 General Guidelines for Adding Support to an Operating System for

the SSE and SSE2 Extensions 12-112.1.2 Checking for SSE and SSE2 Support 12-212.1.3 Checking for Support for the FXSAVE and FXRSTOR Instructions 12-212.1.4 Initialization of the SSE and SSE2 Extensions 12-212.1.5 Providing Non-Numeric Exception Handlers for Exceptions

Generated by the SSE and SSE2 Instructions 12-312.1.6 Providing an Handler for the SIMD Floating-Point Exception (#XF) 12-512.1.6.1 Numeric Error flag and IGNNE# 12-612.2 EMULATION OF THE SSE AND SSE2 EXTENSIONS 12-612.3 SAVING AND RESTORING THE SSE AND SSE2 STATE 12-6

AUTOMATICALLY SAVING X87 FPU, MMX, SSE, AND SSE2 STATE

ON TASK OR CONTEXT SWITCHES 12-712.5.1 Using the TS Flag to Control the Saving of the x87 FPU, MMX, SSE,

and SSE2 State 12-8

13.4.2 SMRAM Caching 13-813.5 SMI HANDLER EXECUTION ENVIRONMENT 13-913.6 EXCEPTIONS AND INTERRUPTS WITHIN SMM 13-1013.7 NMI HANDLING WHILE IN SMM 13-1213.8 SAVING THE X87 FPU STATE WHILE IN SMM 13-1213.9 SMM REVISION IDENTIFIER 13-1313.10 AUTO HALT RESTART 13-1413.10.1 Executing the HLT Instruction in SMM 13-1513.11 SMBASE RELOCATION 13-1513.11.1 Relocating SMRAM to an Address Above 1 MByte .13-1513.12 I/O INSTRUCTION RESTART 13-1613.12.1 Back-to-Back SMI Interrupts When I/O Instruction Restart Is Being Used 13-1713.13 SMM MULTIPLE-PROCESSOR CONSIDERATIONS 13-1713.14 THERMAL MONITORING 13-1813.14.1 Catastrophic Shutdown Detector .13-1913.14.2 Automatic Thermal Monitor 13-1913.14.3 Software Controlled Clock Modulation 13-2113.14.4 Detection of Thermal Monitor and Software Controlled Clock

Modulation Facilities 13-2213.14.5 Usage Models for the Thermal Monitor and Software Controlled

Clock Modulation 13-2213.14.6 Detection and Measurement of Over-Temperature Conditions .13-23

CHAPTER 14

MACHINE-CHECK ARCHITECTURE

14.1 MACHINE-CHECK EXCEPTIONS AND ARCHITECTURE 14-114.2 COMPATIBILITY WITH PENTIUMPROCESSOR 14-114.3 MACHINE-CHECK MSRS 14-214.3.1 Machine-Check Global Control MSRs .14-214.3.1.1 IA32_MCG_CAP MSR (Pentium 4 and Intel Xeon Processors) .14-214.3.1.2 MCG_CAP MSR (P6 Family Processors) .14-314.3.1.3 IA32_MCG_STATUS MSR .14-414.3.1.4 IA32_MCG_CTL MSR 14-514.3.1.5 IA32_MCG_MISC MSR 14-514.3.2 Error-Reporting Register Banks 14-514.3.2.1 IA32_MCi_CTL MSRs 14-514.3.2.2 IA32_MCi_STATUS MSRs 14-614.3.2.3 IA32_MCi_ADDR MSRs 14-714.3.2.4 IA32_MCi_MISC MSRs 14-814.3.2.5 IA32_MCG Extended Machine Check State MSRs 14-814.3.3 Mapping of the PentiumProcessor Machine-Check Errors to the

Machine-Check Architecture 14-914.4 MACHINE-CHECK AVAILABILITY 14-1014.5 MACHINE-CHECK INITIALIZATION 14-1014.6 INTERPRETING THE MCA ERROR CODES 14-1114.6.1 Simple Error Codes 14-11

CHAPTER 15

DEBUGGING AND PERFORMANCE MONITORING

15.1 OVERVIEW OF THE DEBUGGING SUPPORT FACILITIES 15-115.2 DEBUG REGISTERS 15-215.2.1 Debug Address Registers (DR0-DR3) 15-315.2.2 Debug Registers DR4 and DR5 15-415.2.3 Debug Status Register (DR6) 15-415.2.4 Debug Control Register (DR7) 15-415.2.5 Breakpoint Field Recognition 15-615.3 DEBUG EXCEPTIONS 15-615.3.1 Debug Exception (#DB)—Interrupt Vector 1 15-715.3.1.1 Instruction-Breakpoint Exception Condition 15-715.3.1.2 Data Memory and I/O Breakpoint Exception Conditions 15-915.3.1.3 General-Detect Exception Condition 15-915.3.1.4 Single-Step Exception Condition 15-1015.3.1.5 Task-Switch Exception Condition 15-1015.3.2 Breakpoint Exception (#BP)—Interrupt Vector 3 15-1015.4 LAST BRANCH RECORDING OVERVIEW 15-11

15.5.1 IA32_DEBUGCTL MSR (Pentium 4 and Intel Xeon Processors) 15-1215.5.2 LBR Stack (Pentium 4 and Intel Xeon Processors) 15-1315.5.3 Monitoring Branches, Exceptions, and Interrupts (Pentium 4 and

Intel Xeon Processors) 15-1515.5.4 Single-Stepping on Branches, Exceptions, and Interrupts 15-1515.5.5 Branch Trace Messages 15-1515.5.6 Last Exception Records (Pentium 4 and Intel Xeon Processors) 15-1615.5.7 Branch Trace Store (BTS) 15-1615.5.7.1 Detection of the BTS Facilities 15-1615.5.7.2 Setting Up the DS Save Area 15-1715.5.7.3 Setting Up the BTS Buffer 15-1815.5.7.4 Writing the DS Interrupt Service Routine 15-18

15.6.1 DebugCtlMSR Register (P6 Family Processors) 15-1915.6.2 Last Branch and Last Exception MSRs (P6 Family Processors) 15-2115.6.3 Monitoring Branches, Exceptions, and Interrupts (P6 Family Processors) 15-2115.7 TIME-STAMP COUNTER 15-2215.8 PERFORMANCE MONITORING OVERVIEW 15-23

15.9.1 ESCR MSRs 15-2715.9.2 Performance Counters 15-2915.9.3 CCCR MSRs 15-3015.9.4 Debug Store (DS) Mechanism 15-3315.9.5 DS Save Area 15-3315.9.6 Programming the Performance Counters for Non-Retirement Events 15-3615.9.6.1 Selecting Events to Count 15-3715.9.6.2 Filtering Events 15-4015.9.6.3 Starting Event Counting 15-4115.9.6.4 Reading a Performance Counter’s Count 15-4215.9.6.5 Halting Event Counting 15-42

15.9.6.6 Cascading Counters 15-4215.9.6.7 Generating an Interrupt on Overflow 15-4315.9.6.8 Counter Usage Guideline 15-4415.9.7 At-Retirement Counting 15-4415.9.7.1 Using At-Retirement Counting 15-4515.9.7.2 Tagging Mechanism for Front_end_event 15-4615.9.7.3 Tagging Mechanism For Execution_event 15-4615.9.7.4 Tagging Mechanism For Replay_event 15-4715.9.8 Precise Event-Based Sampling (PEBS) 15-4715.9.8.1 Detection of the Availability of the PEBS Facilities 15-4815.9.8.2 Setting Up the DS Save Area 15-4815.9.8.3 Setting Up the PEBS Buffer 15-4815.9.8.4 Writing a PEBS Interrupt Service Routine 15-4915.9.8.5 Other DS Mechanism Implications 15-4915.9.9 Counting Clocks 15-4915.9.10 Operating System Implications 15-51

15.10.1 ESCR MSRs 15-5215.10.2 CCCR MSRs 15-5315.10.3 IA32_PEBS_ENABLE MSR 15-5515.10.4 Performance Monitoring Events 15-5615.11 PERFORMANCE MONITORING (P6 FAMILY PROCESSOR) 15-5715.11.1 PerfEvtSel0 and PerfEvtSel1 MSRs 15-5815.11.2 PerfCtr0 and PerfCtr1 MSRs 15-6015.11.3 Starting and Stopping the Performance-Monitoring Counters 15-6115.11.4 Event and Time-Stamp Monitoring Software .15-6115.11.5 Monitoring Counter Overflow .15-6215.12 PERFORMANCE MONITORING (PENTIUM PROCESSORS) 15-6215.12.1 Control and Event Select Register (CESR) 15-6315.12.2 Use of the Performance-Monitoring Pins .15-6415.12.3 Events Counted 15-65

CHAPTER 16

8086 EMULATION

16.1 REAL-ADDRESS MODE 16-116.1.1 Address Translation in Real-Address Mode 16-316.1.2 Registers Supported in Real-Address Mode 16-416.1.3 Instructions Supported in Real-Address Mode 16-416.1.4 Interrupt and Exception Handling 16-616.2 VIRTUAL-8086 MODE 16-716.2.1 Enabling Virtual-8086 Mode 16-816.2.2 Structure of a Virtual-8086 Task 16-916.2.3 Paging of Virtual-8086 Tasks 16-1016.2.4 Protection within a Virtual-8086 Task 16-1116.2.5 Entering Virtual-8086 Mode 16-1116.2.6 Leaving Virtual-8086 Mode 16-12

16.3.1 Class 1—Hardware Interrupt and Exception Handling in

Virtual-8086 Mode 16-1716.3.1.1 Handling an Interrupt or Exception Through a Protected-Mode

Trap or Interrupt Gate 16-1716.3.1.2 Handling an Interrupt or Exception With an 8086 Program Interrupt

or Exception Handler 16-1916.3.1.3 Handling an Interrupt or Exception Through a Task Gate 16-2016.3.2 Class 2—Maskable Hardware Interrupt Handling in Virtual-8086

Mode Using the Virtual Interrupt Mechanism 16-2016.3.3 Class 3—Software Interrupt Handling in Virtual-8086 Mode 16-2316.3.3.1 Method 1: Software Interrupt Handling 16-2516.3.3.2 Methods 2 and 3: Software Interrupt Handling 16-2616.3.3.3 Method 4: Software Interrupt Handling 16-2616.3.3.4 Method 5: Software Interrupt Handling 16-2616.3.3.5 Method 6: Software Interrupt Handling 16-2716.4 PROTECTED-MODE VIRTUAL INTERRUPTS 16-28

CHAPTER 17

MIXING 16-BIT AND 32-BIT CODE

17.1 DEFINING 16-BIT AND 32-BIT PROGRAM MODULES 17-2

17.3 SHARING DATA AMONG MIXED-SIZE CODE SEGMENTS 17-3

17.4.1 Code-Segment Pointer Size 17-517.4.2 Stack Management for Control Transfer 17-517.4.2.1 Controlling the Operand-Size Attribute For a Call 17-717.4.2.2 Passing Parameters With a Gate 17-717.4.3 Interrupt Control Transfers 17-817.4.4 Parameter Translation 17-817.4.5 Writing Interface Procedures 17-8

CHAPTER 18

IA-32 COMPATIBILITY

18.1 IA-32 PROCESSOR FAMILIES AND CATEGORIES 18-118.2 RESERVED BITS 18-118.3 ENABLING NEW FUNCTIONS AND MODES 18-2

18.5 INTEL MMX TECHNOLOGY 18-318.6 STREAMING SIMD EXTENSIONS (SSE) 18-318.7 STREAMING SIMD EXTENSIONS 2 (SSE2) 18-318.8 HYPER-THREADING TECHNOLOGY 18-3

18.9.1 Instructions Added Prior to the Pentium Processor 18-418.10 OBSOLETE INSTRUCTIONS 18-518.11 UNDEFINED OPCODES 18-518.12 NEW FLAGS IN THE EFLAGS REGISTER 18-518.12.1 Using EFLAGS Flags to Distinguish Between 32-Bit IA-32 Processors 18-618.13 STACK OPERATIONS 18-618.13.1 PUSH SP 18-618.13.2 EFLAGS Pushed on the Stack 18-718.14 X87 FPU 18-7

18.14.2 x87 FPU Status Word 18-818.14.2.1 Condition Code Flags (C0 through C3) 18-818.14.2.2 Stack Fault Flag 18-918.14.3 x87 FPU Control Word 18-918.14.4 x87 FPU Tag Word 18-918.14.5 Data Types 18-1018.14.5.1 NaNs .18-1018.14.5.2 Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal Formats 18-1018.14.6 Floating-Point Exceptions 18-1018.14.6.1 Denormal Operand Exception (#D) 18-1118.14.6.2 Numeric Overflow Exception (#O) 18-1118.14.6.3 Numeric Underflow Exception (#U) 18-1118.14.6.4 Exception Precedence 18-1218.14.6.5 CS and EIP For FPU Exceptions 18-1218.14.6.6 FPU Error Signals 18-1218.14.6.7 Assertion of the FERR# Pin 18-1218.14.6.8 Invalid Operation Exception On Denormals 18-1318.14.6.9 Alignment Check Exceptions (#AC) 18-1318.14.6.10 Segment Not Present Exception During FLDENV 18-1318.14.6.11 Device Not Available Exception (#NM) .18-1318.14.6.12 Coprocessor Segment Overrun Exception 18-1318.14.6.13 General Protection Exception (#GP) 18-1418.14.6.14 Floating-Point Error Exception (#MF) 18-1418.14.7 Changes to Floating-Point Instructions 18-1418.14.7.1 FDIV, FPREM, and FSQRT Instructions 18-1418.14.7.2 FSCALE Instruction 18-1418.14.7.3 FPREM1 Instruction 18-1518.14.7.4 FPREM Instruction 18-1518.14.7.5 FUCOM, FUCOMP, and FUCOMPP Instructions .18-1518.14.7.6 FPTAN Instruction 18-1518.14.7.7 Stack Overflow 18-1518.14.7.8 FSIN, FCOS, and FSINCOS Instructions 18-1518.14.7.9 FPATAN Instruction 18-1618.14.7.10 F2XM1 Instruction 18-1618.14.7.11 FLD Instruction 18-1618.14.7.12 FXTRACT Instruction 18-1618.14.7.13 Load Constant Instructions 18-1618.14.7.14 FSETPM Instruction 18-1718.14.7.15 FXAM Instruction 18-1718.14.7.16 FSAVE and FSTENV Instructions 18-1718.14.8 Transcendental Instructions 18-1718.14.9 Obsolete Instructions 18-1818.14.10 WAIT/FWAIT Prefix Differences 18-1818.14.11 Operands Split Across Segments and/or Pages 18-1818.14.12 FPU Instruction Synchronization 18-1818.15 SERIALIZING INSTRUCTIONS 18-1818.16 FPU AND MATH COPROCESSOR INITIALIZATION 18-19

18.18.1.1 Physical Memory Addressing Extension 18-2218.18.1.2 Global Pages 18-2218.18.1.3 Larger Page Sizes 18-2318.18.2 CD and NW Cache Control Flags 18-2318.18.3 Descriptor Types and Contents 18-2318.18.4 Changes in Segment Descriptor Loads 18-2318.19 DEBUG FACILITIES 18-2318.19.1 Differences in Debug Register DR6 18-2418.19.2 Differences in Debug Register DR7 18-2418.19.3 Debug Registers DR4 and DR5 18-2418.19.4 Recognition of Breakpoints 18-2418.20 TEST REGISTERS 18-2418.21 EXCEPTIONS AND/OR EXCEPTION CONDITIONS 18-2518.21.1 Machine-Check Architecture 18-2618.21.2 Priority OF Exceptions 18-2618.22 INTERRUPTS 18-2718.22.1 Interrupt Propagation Delay 18-2718.22.2 NMI Interrupts 18-2718.22.3 IDT Limit 18-27

18.23.1 Software Visible Differences Between the Local APIC and the 82489DX 18-2818.23.2 New Features Incorporated in the Local APIC for the P6 Family

and Pentium Processors 18-2818.23.3 New Features Incorporated in the Local APIC of the Pentium 4 and

Intel Xeon Processors 18-2918.24 TASK SWITCHING AND TSS 18-2918.24.1 P6 Family and Pentium Processor TSS 18-2918.24.2 TSS Selector Writes 18-2918.24.3 Order of Reads/Writes to the TSS 18-2918.24.4 Using A 16-Bit TSS with 32-Bit Constructs 18-3018.24.5 Differences in I/O Map Base Addresses 18-3018.25 CACHE MANAGEMENT 18-3118.25.1 Self-Modifying Code with Cache Enabled 18-3218.25.2 Disabling the L3 Cache 18-3318.26 PAGING 18-3318.26.1 Large Pages 18-3318.26.2 PCD and PWT Flags 18-3318.26.3 Enabling and Disabling Paging 18-3318.27 STACK OPERATIONS 18-3418.27.1 Selector Pushes and Pops 18-3418.27.2 Error Code Pushes 18-3518.27.3 Fault Handling Effects on the Stack 18-3518.27.4 Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate 18-3518.28 MIXING 16- AND 32-BIT SEGMENTS 18-3518.29 SEGMENT AND ADDRESS WRAPAROUND 18-3618.29.1 Segment Wraparound 18-3618.30 STORE BUFFERS AND MEMORY ORDERING 18-3718.31 BUS LOCKING 18-3818.32 BUS HOLD 18-3918.33 MODEL-SPECIFIC EXTENSIONS TO THE IA-32 18-3918.33.1 Model-Specific Registers 18-3918.33.2 RDMSR and WRMSR Instructions 18-39

18.33.3 Memory Type Range Registers 18-4018.33.4 Machine-Check Exception and Architecture 18-4018.33.5 Performance-Monitoring Counters 18-4118.34 TWO WAYS TO RUN INTEL 286 PROCESSOR TASKS 18-41

APPENDIX A

PERFORMANCE-MONITORING EVENTS

PERFORMANCE-MONITORING EVENTS A-1

APPENDIX B

MODEL-SPECIFIC REGISTERS (MSRS)

B.1 MSRS IN THE PENTIUM 4 AND INTEL XEON PROCESSORS B-1B.2 MSRS IN THE P6 FAMILY PROCESSORS B-16B.3 MSRS IN PENTIUM PROCESSORS B-25B.4 ARCHITECTURAL MSRS B-26

APPENDIX C

MP INITIALIZATION FOR P6 FAMILY PROCESSORS

FAMILY PROCESSORS C-1C.2 MP INITIALIZATION PROTOCOL ALGORITHM C-2C.2.1 Error Detection and Handling During the MP Initialization Protocol C-4

APPENDIX D

PROGRAMMING THE LINT0 AND LINT1 INPUTS

D.1 CONSTANTS D-1D.2 LINT[0:1] PINS PROGRAMMING PROCEDURE D-1

APPENDIX E

INTERPRETING MACHINE-CHECK

ERROR CODES

APPENDIX F

APIC BUS MESSAGE FORMATS

F.1 BUS MESSAGE FORMATS F-1F.2 EOI MESSAGE F-1F.2.1 Short Message F-2F.2.2 Non-focused Lowest Priority Message F-3F.2.3 APIC Bus Status Cycles F-4

Figure 1-1 Bit and Byte Order 1-7Figure 2-1 IA-32 System-Level Registers and Data Structures 2-2Figure 2-2 Transitions Among the Processor’s Operating Modes 2-7Figure 2-3 System Flags in the EFLAGS Register .2-8Figure 2-4 Memory Management Registers 2-10Figure 2-5 Control Registers 2-12Figure 3-1 Segmentation and Paging 3-2Figure 3-2 Flat Model 3-4Figure 3-3 Protected Flat Model .3-4Figure 3-4 Multi-Segment Model 3-5Figure 3-5 Logical Address to Linear Address Translation 3-7Figure 3-6 Segment Selector 3-8Figure 3-7 Segment Registers 3-9Figure 3-8 Segment Descriptor 3-10Figure 3-9 Segment Descriptor When Segment-Present Flag Is Clear 3-12Figure 3-10 Global and Local Descriptor Tables 3-16Figure 3-11 Pseudo-Descriptor Format 3-17Figure 3-12 Linear Address Translation (4-KByte Pages) 3-21Figure 3-13 Linear Address Translation (4-MByte Pages) .3-22Figure 3-14 Format of Page-Directory and Page-Table Entries for 4-KByte Pages

and 32-Bit Physical Addresses 3-24Figure 3-15 Format of Page-Directory Entries for 4-MByte Pages and

32-Bit Addresses 3-25Figure 3-16 Format of a Page-Table or Page-Directory Entry for a

Not-Present Page 3-28Figure 3-17 Register CR3 Format When the Physical Address Extension

is Enabled 3-29Figure 3-18 Linear Address Translation With PAE Enabled (4-KByte Pages) 3-30Figure 3-19 Linear Address Translation With PAE Enabled (2-MByte Pages) 3-31Figure 3-20 Format of Page-Directory-Pointer-Table, Page-Directory, and

Page-Table Entries for 4-KByte Pages with PAE Enabled 3-32Figure 3-21 Format of Page-Directory-Pointer-Table and Page-Directory

Entries for 2-MByte Pages with PAE Enabled 3-33Figure 3-22 Linear Address Translation (4-MByte Pages) .3-35Figure 3-23 Format of Page-Directory Entries for 4-MByte Pages and 36-Bit

Physical Addresses 3-35Figure 3-24 Memory Management Convention That Assigns a Page Table to

Each Segment 3-36Figure 4-1 Descriptor Fields Used for Protection 4-4Figure 4-2 Protection Rings 4-8Figure 4-3 Privilege Check for Data Access 4-10Figure 4-4 Examples of Accessing Data Segments From Various Privilege Levels 4-11Figure 4-5 Privilege Check for Control Transfer Without Using a Gate 4-13Figure 4-6 Examples of Accessing Conforming and Nonconforming Code

Segments From Various Privilege Levels .4-15Figure 4-7 Call-Gate Descriptor 4-17Figure 4-8 Call-Gate Mechanism 4-19Figure 4-9 Privilege Check for Control Transfer with Call Gate 4-19

Figure 4-11 Stack Switching During an Interprivilege-Level Call 4-23Figure 4-12 Use of RPL to Weaken Privilege Level of Called Procedure 4-30Figure 5-1 Relationship of the IDTR and IDT .5-12Figure 5-2 IDT Gate Descriptors 5-13Figure 5-3 Interrupt Procedure Call 5-15Figure 5-4 Stack Usage on Transfers to Interrupt and Exception-Handling

Routines 5-16Figure 5-5 Interrupt Task Switch 5-19Figure 5-6 Error Code 5-20Figure 5-7 Page-Fault Error Code 5-45Figure 6-1 Structure of a Task 6-2Figure 6-2 32-Bit Task-State Segment (TSS) 6-5Figure 6-3 TSS Descriptor 6-8Figure 6-4 Task Register 6-10Figure 6-5 Task-Gate Descriptor 6-10Figure 6-6 Task Gates Referencing the Same Task 6-12Figure 6-7 Nested Tasks 6-16Figure 6-8 Overlapping Linear-to-Physical Mappings 6-20Figure 6-9 16-Bit TSS Format 6-22Figure 7-1 Example of Write Ordering in Multiple-Processor Systems 7-10Figure 7-2 Interpretation of APIC ID in MP Systems 7-23Figure 7-3 Generalized View of an IA-32 Processor with Hyper-Threading

Technology with Two Logical Processors .7-25Figure 7-4 Local APICs and I/O APIC When IA-32 Processors with

Hyper-Threading Technology Are Used in MP Systems 7-33Figure 7-5 Interpretation of the APIC ID for an Intel Xeon Processor MP 7-35Figure 8-1 Relationship of Local APIC and I/O APIC In Single-Processor

Systems 8-3Figure 8-2 Local APICs and I/O APIC When Intel Xeon Processors Are

Used in Multiple-Processor Systems 8-4Figure 8-3 Local APICs and I/O APIC When P6 Family Processors Are

Used in Multiple-Processor Systems 8-4Figure 8-4 Local APIC Structure 8-7Figure 8-5 IA32_APIC_BASE MSR 8-10Figure 8-6 Local APIC ID Register .8-12Figure 8-7 Local APIC Version Register 8-14Figure 8-8 Local Vector Table (LVT) 8-16Figure 8-9 Error Status Register (ESR) 8-19Figure 8-10 Divide Configuration Register 8-20Figure 8-11 Initial Count and Current Count Registers 8-20Figure 8-12 Interrupt Command Register (ICR) .8-22Figure 8-13 Logical Destination Register (LDR) 8-28Figure 8-14 Destination Format Register (DFR) 8-28Figure 8-15 Arbitration Priority Register (APR) 8-30Figure 8-16 Interrupt Acceptance Flow Chart for the Local APIC (Pentium 4 and

Intel Xeon Processors) 8-32Figure 8-17 Interrupt Acceptance Flow Chart for the Local APIC (P6 Family and

Figure 8-22 Spurious-Interrupt Vector Register (SVR) 8-39Figure 9-1 Contents of CR0 Register after Reset 9-5Figure 9-2 Version Information in the EDX Register after Reset 9-5Figure 9-3 Processor State After Reset 9-17Figure 9-4 Constructing Temporary GDT and Switching to Protected Mode

(Lines 162-172 of List File) 9-26

(Lines 196-261 of List File) 9-27Figure 9-6 Task Switching (Lines 282-296 of List File) 9-28Figure 9-7 Integrating Processor Specific Updates 9-31Figure 9-8 Format of the Microcode Update Data Block 9-34Figure 9-9 Write Operation Flow Chart 9-46Figure 10-1 Cache Structure of the Pentium 4 and Intel Xeon Processors 10-1Figure 10-2 Cache-Control Registers and Bits Available in IA-32 Processors 10-11Figure 10-3 Mapping Physical Memory With MTRRs 10-24Figure 10-4 IA32_MTRRCAP Register 10-25Figure 10-5 IA32_MTRR_DEF_TYPE MSR 10-26

Variable-Range Register Pair 10-28Figure 10-7 IA32_CR_PAT MSR 10-38Figure 11-1 Mapping of MMX Registers to Floating-Point Registers 11-2Figure 11-2 Mapping of MMX Registers to x87 FPU Data Register Stack 11-7Figure 12-1 Example of Saving the x87 FPU, MMX, SSE, and SSE2 State

During an Operating-System Controlled Task Switch 12-9Figure 13-1 SMRAM Usage 13-5Figure 13-2 SMM Revision Identifier 13-13Figure 13-3 Auto HALT Restart Field 13-14Figure 13-4 SMBASE Relocation Field 13-15Figure 13-5 I/O Instruction Restart Field 13-16Figure 13-6 Processor Modulation Through Stop-Clock Mechanism 13-18Figure 13-7 IA32_THERM_STATUS MSR 13-20Figure 13-8 IA32_THERM_INTERRUPT MSR 13-20Figure 13-9 IA32_THERM_CONTROL MSR 13-21Figure 14-1 Machine-Check MSRs 14-2Figure 14-2 IA32_MCG_CAP Register 14-3Figure 14-3 MCG_CAP Register 14-3Figure 14-4 IA32_MCG_STATUS Register 14-4Figure 14-5 IA32_MCi_CTL Register 14-5Figure 14-6 IA32_MCi_STATUS Register 14-6Figure 14-7 IA32_MCi_ADDR MSR 14-8Figure 15-1 Debug Registers 15-3Figure 15-2 IA32_DEBUGCTL MSR (Pentium 4 and Intel Xeon Processors) 15-13Figure 15-3 LBR MSR Stack Structure 15-13Figure 15-4 MSR_LASTBRANCH_TOS MSR Layout 15-14Figure 15-5 LBR MSR Branch Record Layout 15-14Figure 15-6 DebugCtlMSR Register (P6 Family Processors) 15-20Figure 15-7 Event Selection Control Register (ESCR) (Pentium 4 and

Intel Xeon processors) 15-28Figure 15-8 Performance Counter (Pentium 4 and Intel Xeon Processors) 15-30Figure 15-9 Counter Configuration Control Register (CCCR) 15-32Figure 15-10 DS Save Area 15-35Figure 15-11 Branch Trace Record Format 15-36

Figure 15-12 PEBS Record Format 15-37Figure 15-13 Event Example 15-38Figure 15-14 Effects of Edge Filtering 15-41Figure 15-15 Event Selection Control Register (ESCR) for Intel Xeon

processor MP 15-52Figure 15-16 Counter Configuration Control Register (CCCR) 15-54Figure 15-17 PerfEvtSel0 and PerfEvtSel1 MSRs 15-59Figure 15-18 CESR MSR (Pentium® Processor Only) 15-63Figure 16-1 Real-Address Mode Address Translation 16-4Figure 16-2 Interrupt Vector Table in Real-Address Mode 16-7Figure 16-3 Entering and Leaving Virtual-8086 Mode 16-12Figure 16-4 Privilege Level 0 Stack After Interrupt or Exception in

Virtual-8086 Mode 16-18Figure 16-5 Software Interrupt Redirection Bit Map in TSS 16-25Figure 17-1 Stack after Far 16- and 32-Bit Calls 17-6Figure 18-1 I/O Map Base Address Differences 18-31Figure C-1 MP System With Multiple Pentium III Processors C-3

Table 2-1 Action Taken By x87 FPU Instructions for Different Combinations of

EM, MP and TS 2-15Table 2-2 Summary of System Instructions 2-18Table 3-1 Code- and Data-Segment Types 3-13Table 3-2 System-Segment and Gate-Descriptor Types 3-15Table 3-3 Page Sizes and Physical Address Sizes 3-20Table 4-1 Privilege Check Rules for Call Gates 4-20Table 4-2 Combined Page-Directory and Page-Table Protection 4-34Table 5-1 Protected-Mode Exceptions and Interrupts 5-3Table 5-2 Priority Among Simultaneous Exceptions and Interrupts 5-10Table 5-3 Debug Exception Conditions and Corresponding Exception Classes 5-23Table 5-4 Interrupt and Exception Classes 5-32Table 5-5 Conditions for Generating a Double Fault 5-33Table 5-6 Invalid TSS Conditions 5-35Table 5-7 Alignment Requirements by Data Type 5-49Table 5-8 SIMD Floating-Point Exceptions Priority .5-54Table 6-1 Exception Conditions Checked During a Task Switch 6-15Table 6-2 Effect of a Task Switch on Busy Flag, NT Flag, Previous Task Link Field,

and TS Flag 6-17Table 7-1 Initial APIC IDs for the Logical Processors in a System that has

Four MP-Type Intel Xeon Processors with Hyper-Threading Technology 7-35Table 8-1 Local APIC Register Address Map 8-8Table 8-2 Valid Combinations for the Pentium 4 and Intel Xeon Processors’

Local xAPIC Interrupt Command Register 8-25Table 8-3 Valid Combinations for the P6 Family Processors’ Local APIC

Interrupt Command Register 8-26Table 9-1 32-Bit IA-32 processor States Following Power-up, Reset, or INIT 9-3Table 9-2 Recommended Settings of EM and MP Flags on IA-32 processors .9-7Table 9-3 Software Emulation Settings of EM, MP, and NE Flags 9-8Table 9-4 Main Initialization Steps in STARTUP.ASM Source Listing 9-18Table 9-5 Relationship Between BLD Item and ASM Source File 9-30Table 9-6 Processor MSR Register Components .9-32Table 9-7 Microcode Update Encoding Format 9-33Table 9-8 Microcode Update Functions 9-42Table 9-9 Parameters for the Presence Test 9-43Table 9-10 Parameters for the Write Update Data Function .9-44Table 9-11 Parameters for the Control Update Sub-function 9-47Table 9-12 Mnemonic Values 9-47Table 9-13 Parameters for the Read Microcode Update Data Function .9-48Table 9-14 Return Code Definitions 9-49Table 10-1 Characteristics of the Caches, TLBs, Store Buffer, and Write

Combining Buffer in IA-32 processors 10-2Table 10-2 Memory Types and Their Properties 10-5Table 10-3 Methods of Caching Available in Pentium 4, Intel Xeon, P6 Family, and

Pentium Processors 10-7Table 10-4 MESI Cache Line States 10-9Table 10-5 Cache Operating Modes 10-12

Table 10-7 Effective Page-Level Memory Types for Pentium III, Pentium 4, and

Intel Xeon Processors .10-16Table 10-8 Memory Types That Can Be Encoded in MTRRs .10-23Table 10-9 Address Mapping for Fixed-Range MTRRs 10-27Table 10-10 Memory Types That Can Be Encoded With PAT 10-39Table 10-11 Selection of PAT Entries with PAT, PCD, and PWT flags 10-39Table 10-12 Memory Type Setting of PAT Entries Following a Power-up or Reset 10-40Table 11-1 Action Taken By MMX Instructions for Different Combinations of EM,

MP and TS 11-1Table 11-2 Effects of MMX Instructions on x87 FPU State 11-3Table 11-3 Effect of the MMX, x87 FPU, and FXSAVE/FXRSTOR Instructions

on the x87 FPU Tag Word 11-4

SSE2, EM, MP, and TS1 12-3Table 13-1 SMRAM State Save Map 13-5Table 13-2 Processor Register Initialization in SMM 13-9Table 13-3 Auto HALT Restart Flag Values 13-14Table 13-4 I/O Instruction Restart Field Values 13-16Table 13-5 On-Demand Clock Modulation Duty Cycle Field Encoding 13-21Table 14-1 Extended Machine-Check State MSRs 14-8Table 14-2 Simple Error Codes 14-12Table 14-3 General Forms of Compound Error Codes 14-12Table 14-4 Encoding for TT (Transaction Type) Sub-Field 14-13Table 14-5 Level Encoding for LL (Memory Hierarchy Level) Sub-Field 14-13Table 14-6 Encoding of Request (RRRR) Sub-Field 14-13Table 14-7 Encodings of PP, T, and II Sub-Fields 14-14Table 15-1 Breakpointing Examples 15-7Table 15-2 Debug Exception Conditions 15-8Table 15-3 IA32_DEBUGCTL MSR Flag Encodings 15-18

ESCR MSRs (Pentium 4 and Intel Xeon Processors) 15-24Table 15-6 Effect of logical processor and CPL qualification for

non-logical-processor-specific (TI) events 15-57Table 15-5 Effect of Logical Processor and CPL Qualification for

Logical-Processor-Specific (TS) Events 15-57Table 16-1 Real-Address Mode Exceptions and Interrupts .16-8Table 16-2 Software Interrupt Handling Methods While in Virtual-8086 Mode 16-24Table 17-1 Characteristics of 16-Bit and 32-Bit Program Modules 17-1Table 18-1 New Instruction in the Pentium and Later IA-32 Processors 18-4Table 18-2 Recommended Values of the EM, MP, and NE Flags for Intel486 SX

Microprocessor/Intel 487 SX Math Coprocessor System 18-19Table 18-3 EM and MP Flag Interpretation .18-20Table A-1 Pentium 4 and Intel Xeon Processor Performance Monitoring Events for

Non-Retirement Counting A-1Table A-2 Pentium 4 and Intel Xeon Processor Performance Monitoring Events For At-

Retirement Counting A-25Table A-3 List of Metrics Available for Front_end Tagging (For Front_end

Table A-7 Events That Can Be Counted with the P6 Family

Performance-Monitoring Counters A-38Table A-8 Events That Can Be Counted with the Pentium Processor Performance-

Monitoring Counters A-49Table B-1 MSRs in the Pentium 4 and Intel Xeon Processors B-1Table B-2 MSRs in the P6 Family Processors B-16Table B-3 MSRs in the Pentium Processor B-25Table B-4 IA-32 Architectural MSRs B-26Table C-1 Boot Phase IPI Message Format C-2Table E-1 Encoding of the MCi_STATUS Register for External Bus Errors E-1Table F-1 EOI Message (14 Cycles) F-1Table F-2 Short Message (21 Cycles) F-2Table F-3 Non-Focused Lowest Priority Message (34 Cycles) F-3Table F-4 APIC Bus Status Cycles Interpretation F-5

1About This Manual

ABOUT THIS MANUAL

The IA-32 Intel ® Architecture Software Developer’s Manual, Volume 3: System Programming Guide (Order Number 245472), is part of a three-volume set that describes the architecture and

programming environment of all IA-32 Intel Architecture processors The other two volumes inthis set are:

• The IA-32 Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture

archi-opcode structure These two volumes are aimed at application programmers who are writing

programs to run under existing operating systems or executives The IA-32 Intel Architecture Software Developer’s Manual, Volume 3, describes the operating-system support environment

of an IA-32 processor, including memory management, protection, task management, interruptand exception handling, and system management mode It also provides IA-32 processorcompatibility information This volume is aimed at operating-system and BIOS designers andprogrammers

This manual includes information pertaining primarily to the most recent IA-32 processors,which include the Pentium® processors, the P6 family processors, the Pentium® 4 processors,and the Intel® Xeon™ processors The P6 family processors are those IA-32 processors based

on the P6 family micro-architecture, which include the Pentium® Pro, Pentium® II, andPentium® III processors The Pentium 4 and Intel Xeon processors are based on the Intel®NetBurst™ micro-architecture

1.2. OVERVIEW OF THE IA-32 INTEL ARCHITECTURE

SOFTWARE DEVELOPER’S MANUAL, VOLUME 3: SYSTEM PROGRAMMING GUIDE

The contents of this manual are as follows:

Chapter 1 — About This Manual Gives an overview of all three volumes of the IA-32 Intel

Architecture Software Developer’s Manual It also describes the notational conventions in these

manuals and lists related Intel manuals and documentation of interest to programmers and ware designers

hard-Chapter 2 — System Architecture Overview Describes the modes of operation of an IA-32

processor and the mechanisms provided in the IA-32 architecture to support operating systemsand executives, including the system-oriented registers and data structures and the system-oriented instructions The steps necessary for switching between real-address and protectedmodes are also identified

Chapter 3 — Protected-Mode Memory Management Describes the data structures, registers,

and instructions that support segmentation and paging and explains how they can be used toimplement a “flat” (unsegmented) memory model or a segmented memory model

Chapter 4 — Protection Describes the support for page and segment protection provided in

the IA-32 architecture This chapter also explains the implementation of privilege rules, stackswitching, pointer validation, user and supervisor modes

Chapter 5 — Interrupt and Exception Handling Describes the basic interrupt mechanisms

defined in the IA-32 architecture, shows how interrupts and exceptions relate to protection, anddescribes how the architecture handles each exception type Reference information for each IA-

32 exception is given at the end of this chapter

Chapter 6 — Task Management Describes the mechanisms the IA-32 architecture provides

to support multitasking and inter-task protection

Chapter 7 — Multiple-Processor Management Describes the instructions and flags that

support multiple processors with shared memory, memory ordering, and Hyper-Threading nology

tech-Chapter 8 — Advanced Programmable Interrupt Controller (APIC) Describes the

programming interface to the local APIC and gives an overview of the interface between thelocal APIC and the I/O APIC

Chapter 9 — Processor Management and Initialization Defines the state of an IA-32

processor after reset initialization This chapter also explains how to set up an IA-32 processorfor real-address mode operation and protected- mode operation, and how to switch betweenmodes

Chapter 10 — Memory Cache Control Describes the general concept of caching and the

Chapter 11 — Intel MMX™ Technology System Programming Describes those aspects of

the Intel MMX technology that must be handled and considered at the system programminglevel, including task switching, exception handling, and compatibility with existing systemenvironments The Intel MMX technology was introduced into the IA-32 architecture with thePentium processor

Chapter 12 — SSE and SSE2 System Programming Describes those aspects of SSE and

SSE2 extensions that must be handled and considered at the system programming level,including task switching, exception handling, and compatibility with existing system environ-ments

Chapter 13 — System Management Describes the IA-32 architecture’s system management

mode (SMM) and the thermal monitoring facilities

Chapter 14 — Machine-Check Architecture Describes the machine-check architecture Chapter 15 — Debugging and Performance Monitoring Describes the debugging registers

and other debug mechanism provided in the IA-32 architecture This chapter also describes thetime-stamp counter and the performance-monitoring counters

Chapter 16 — 8086 Emulation Describes the real-address and virtual-8086 modes of the

IA-32 architecture

Chapter 17 — Mixing 16-Bit and 32-Bit Code Describes how to mix 16-bit and 32-bit code

modules within the same program or task

Chapter 18 — IA-32 Architecture Compatibility Describes architectural compatibility

among the IA-32 processors, which include the Intel 286, Intel386™, Intel486™, Pentium, P6family, Pentium 4, and Intel Xeon processors The P6 family includes the Pentium Pro, Pentium

II, and Pentium III processors The differences among the 32-bit IA-32 processors are also

described throughout the three volumes of the IA-32 Software Developer’s Manual, as relevant

to particular features of the architecture This chapter provides a collection of all the relevantcompatibility information for all IA-32 processors and also describes the basic differences withrespect to the 16-bit IA-32 processors (the Intel 8086 and Intel 286 processors)

Appendix A — Performance-Monitoring Events Lists the events that can be counted with

the performance-monitoring counters and the codes used to select these events Both Pentiumprocessor and P6 family processor events are described

Appendix B — Model Specific Registers (MSRs) Lists the MSRs available in the Pentium

processors, the P6 family processors, and the Pentium 4 and Intel Xeon processors and describestheir functions

Appendix C — MP Initialization For P6 Family Processors Gives an example of how to use

of the MP protocol to boot P6 family processors in n MP system

Appendix D — Programming the LINT0 and LINT1 Inputs Gives an example of how to

program the LINT0 and LINT1 pins for specific interrupt vectors

Appendix E — Interpreting Machine-Check Error Codes Gives an example of how to

inter-pret the error codes for a machine-check error that occurred on a P6 family processor

Appendix F — APIC Bus Message Formats Describes the message formats for messages

transmitted on the APIC bus for P6 family and Pentium processors

SOFTWARE DEVELOPER’S MANUAL, VOLUME 1: BASIC ARCHITECTURE

The contents of the IA-32 Intel Architecture Software Developer’s Manual, Volume 1 are as

follows:

Chapter 1 — About This Manual Gives an overview of all three volumes of the IA-32 Intel

Architecture Software Developer’s Manual It also describes the notational conventions in these

manuals and lists related Intel manuals and documentation of interest to programmers and ware designers

hard-Chapter 2 — Introduction to the IA-32 Architecture Introduces the IA-32 architecture and

the families of Intel processors that are based on this architecture It also gives an overview ofthe common features found in these processors and brief history of the IA-32 architecture

Chapter 3 — Basic Execution Environment Introduces the models of memory organization

and describes the register set used by applications

Chapter 4 — Data Types Describes the data types and addressing modes recognized by the

processor; provides an overview of real numbers and point formats and of point exceptions

floating-Chapter 5 — Instruction Set Summary Lists the all the IA-32 architecture instructions,

divided into technology groups (general-purpose, x87 FPU, Intel MMX technology, SSE, SSE2,and system instructions) Within these groups, the instructions are presented in functionallyrelated groups

Chapter 6 — Procedure Calls, Interrupts, and Exceptions Describes the procedure stack

and the mechanisms provided for making procedure calls and for servicing interrupts andexceptions

Chapter 7 — Programming With the General-Purpose Instructions Describes the basic

load and store, program control, arithmetic, and string instructions that operate on basic datatypes and on the general-purpose and segment registers; describes the system instructions thatare executed in protected mode

Chapter 8 — Programming With the x87 Floating Point Unit Describes the x87

floating-point unit (FPU), including the floating-floating-point registers and data types; gives an overview of the

Chapter 10 — Programming with Streaming SIMD Extensions (SSE) Describes the SSE

extensions, including the XMM registers, the MXCSR register, and the packed single-precisionfloating-point data types; gives an overview of the SSE instruction set; and gives guidelines forwriting code that accesses the SSE extensions

Chapter 11 — Programming with Streaming SIMD Extensions 2 (SSE2) Describes the

SSE2 extensions, including XMM registers and the packed double-precision floating-point datatypes; gives an overview of the SSE2 instruction set; and gives guidelines for writing code thataccesses the SSE2 extensions This chapter also describes the SIMD floating-point exceptionsthat can be generated with SSE and SSE2 instructions, and it gives general guidelines for incor-porating support for the SSE and SSE2 extensions into operating system and applications code

Chapter 12 — Input/Output Describes the processor’s I/O mechanism, including I/O port

addressing, the I/O instructions, and the I/O protection mechanism

Chapter 13 — Processor Identification and Feature Determination Describes how to

deter-mine the CPU type and the features that are available in the processor

Appendix A — EFLAGS Cross-Reference Summarizes how the IA-32 instructions affect the

flags in the EFLAGS register

Appendix B — EFLAGS Condition Codes Summarizes how the conditional jump, move, and

byte set on condition code instructions use the condition code flags (OF, CF, ZF, SF, and PF) inthe EFLAGS register

Appendix C — Floating-Point Exceptions Summary Summarizes the exceptions that can be

raised by the x87 FPU floating-point and the SSE and SSE2 SIMD floating-point instructions

Appendix D — Guidelines for Writing x87 FPU Exception Handlers Describes how to

design and write MS-DOS* compatible exception handling facilities for FPU exceptions,including both software and hardware requirements and assembly-language code examples.This appendix also describes general techniques for writing robust FPU exception handlers

Appendix E — Guidelines for Writing SIMD Floating-Point Exception Handlers Gives

guidelines for writing exception handlers to handle exceptions generated by the SSE and SSE2SIMD floating-point instructions

SOFTWARE DEVELOPER’S MANUAL, VOLUME 2:

INSTRUCTION SET REFERENCE

The contents of the IA-32 Intel Architecture Software Developer’s Manual, Volume 2, are as

follows:

Chapter 1 — About This Manual Gives an overview of all three volumes of the IA-32 Intel

Architecture Software Developer’s Manual It also describes the notational conventions in these

manuals and lists related Intel manuals and documentation of interest to programmers and ware designers

hard-Chapter 2 — Instruction Format Describes the machine-level instruction format used for all

IA-32 instructions and gives the allowable encodings of prefixes, the operand-identifier byte(ModR/M byte), the addressing-mode specifier byte (SIB byte), and the displacement andimmediate bytes

Chapter 3 — Instruction Set Reference Describes each of the IA-32 instructions in detail,

including an algorithmic description of operations, the effect on flags, the effect of operand- andaddress-size attributes, and the exceptions that may be generated The instructions are arranged

in alphabetical order The FPU and MMX instructions are included in this chapter

Appendix A — Opcode Map Gives an opcode map for the IA-32 instruction set.

Appendix B — Instruction Formats and Encodings Gives the binary encoding of each form

of each IA-32 instruction

This manual uses specific notation for data-structure formats, for symbolic representation ofinstructions, and for hexadecimal and binary numbers A review of this notation makes themanual easier to read

In illustrations of data structures in memory, smaller addresses appear toward the bottom of thefigure; addresses increase toward the top Bit positions are numbered from right to left Thenumerical value of a set bit is equal to two raised to the power of the bit position IA-32 proces-sors are “little endian” machines; this means the bytes of a word are numbered starting from theleast significant byte Figure 1-1 illustrates these conventions

In many register and memory layout descriptions, certain bits are marked as reserved When

bits are marked as reserved, it is essential for compatibility with future processors that softwaretreat these bits as having a future, though unknown, effect The behavior of reserved bits should

be regarded as not only undefined, but unpredictable Software should follow these guidelines

in dealing with reserved bits:

• Do not depend on the states of any reserved bits when testing the values of registers whichcontain such bits Mask out the reserved bits before testing

• Do not depend on the states of any reserved bits when storing to memory or to a register

Avoid any software dependence upon the state of reserved bits in IA-32

registers Depending upon the values of reserved register bits will make

software dependent upon the unspecified manner in which the processor

handles these bits Programs that depend upon reserved values risk

incompat-ibility with future processors

• A label is an identifier which is followed by a colon.

• A mnemonic is a reserved name for a class of instruction opcodes which have the same

function

• The operands argument1, argument2, and argument3 are optional There may be from

zero to three operands, depending on the opcode When present, they take the form ofeither literals or identifiers for data items Operand identifiers are either reserved names ofregisters or are assumed to be assigned to data items declared in another part of theprogram (which may not be shown in the example)

When two operands are present in an arithmetic or logical instruction, the right operand is thesource and the left operand is the destination

Figure 1-1 Bit and Byte Order

24 20 16 12 8 4

0 Address

Byte Offset

For example:

LOADREG: MOV EAX, SUBTOTAL

In this example LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX isthe destination operand, and SUBTOTAL is the source operand Some assembly languages putthe source and destination in reverse order

Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed bythe character H (for example, F82EH) A hexadecimal digit is a character from the followingset: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F

Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by thecharacter B (for example, 1010B) The “B” designation is only used in situations where confu-sion as to the type of number might arise

The processor uses byte addressing This means memory is organized and accessed as asequence of bytes Whether one or more bytes are being accessed, a byte address is used tolocate the byte or bytes memory The range of memory that can be addressed is called an

address space.

The processor also supports segmented addressing This is a form of addressing where a

program may have many independent address spaces, called segments For example, a program

can keep its code (instructions) and stack in separate segments Code addresses would alwaysrefer to the code space, and stack addresses would always refer to the stack space The followingnotation is used to specify a byte address within a segment:

1.5.6 Exceptions

An exception is an event that typically occurs when an instruction causes an error For example,

an attempt to divide by zero generates an exception However, some exceptions, such as points, occur under other conditions Some types of exceptions may provide error codes Anerror code reports additional information about the error An example of the notation used toshow an exception and error code is shown below

on-• Data Sheet for a particular Intel IA-32 processor

• Specification Update for a particular Intel IA-32 processor

• AP-485, Intel Processor Identification and the CPUID Instruction, Order Number 241618.

• Intel ® Pentium ® 4 and Intel ® Xeon™ Processor Optimization Reference Manual, Order

Number 248966

2 System Architecture

Overview