The Art of Error Correcting Coding phần 5 docx

BINARY CONVOLUTIONAL CODES 99xz xz yz 1 Figure 5.9 The modified state diagram of a memory-2 rate-1/2 convolutional code.. For transmission over a binary symmetric channel BSC and binary

BINARY CONVOLUTIONAL CODES 99

xz xz

yz

1

Figure 5.9 The modified state diagram of a memory-2 rate-1/2 convolutional code.

Example 5.3.3 Continuing with Example 5.3.2 , a modified state diagram for the

computa-tion of the CWES is shown in Figure 5.9.

The equations are

Bounds on the bit error probability of a binary convolutional code of rate k/n can be

obtained with the aid of the CWES described in the previous section For transmission over

a binary symmetric channel (BSC) and binary transmission over an additive white sian noise (AWGN) channel (Viterbi and Omura 1979) and maximum-likelihood decoding(MLD)6, the following upper bounds hold, respectively,

where the energy-per-bit-to-noise ratio E b /N0 is related to the energy-per-symbol-to-noise

ratio E s /N0 via the code rate R = k/n is as follows:

100 BINARY CONVOLUTIONAL CODESUnion bounds may be used to estimate the bit-error rate (BER) performance of a convo-lutional code The reader should be aware, however, that the bounds in Equations (5.16) and(5.17) are quite loose Fortunately, tighter (close to the actual BER performance) bounds

exist at relatively mild channel conditions, that is, low values of p for the BSC and high values of E s /N0 for the AWGN channel, and are given by the following (Johannesson andZigangirov 1999):

Example 5.4.1 The bounds in Equations (5.16) and (5.19) on the probability of a bit error P b

for the 4-state rate-1/2 convolutional code of Example 5.3.3, with transmission over a BSC with crossover probability p and MLD, are plotted in Figure 5.10 Evident from the figure

is the fact that the bound in Equation (5.19) is tighter than the bound in Equation (5.16).

Figure 5.10 Bounds in Equations (5.16) and (5.19) on the BER of a memory-2 rate-1/2 convolutional code with d f = 5 Transmission over BSC with crossover probability p and

MLD

BINARY CONVOLUTIONAL CODES 101

The trellis of convolutional codes has a regular structure It is possible to take advantage

of the repetitive pattern of the trellis in decoding However, for linear block codes obtainedfrom terminating convolutional codes and long information sequences, MLD is simply toocomplex and inefficient to implement

An efficient solution to the decoding problem is a dynamic programming algorithm

known as the Viterbi algorithm, also known as the Viterbi decoder (VD) This is a maximum

likelihood decoder in the sense that it finds the closest coded sequence ¯ v to the received

sequence ¯r by processing the sequences on an information bit-by-bit (branches of the trellis) basis In other words, instead of keeping a score of each possible coded sequence, the VD

tracks the states of the trellis.

The likelihood of a received sequence ¯ Rafter transmission over a noisy memoryless channel,given that a coded sequence ¯V is sent, is defined as the conditional probability densityfunction

where ¯V and ¯R are the transmitted and received sequences, respectively

It is easy to show that for a BSC with parameter p,

with d H (r i , v i ) = 1, if r i = v i , and d H (r i , v i ) = 0, if r i = v i That is, d H (r i , v i ) is the

Hamming distance between bits r i and v i For an AWGN channel, the likelihood is given by

where m(·) denotes a binary modulated signal Here, m is defined as a one-to-one mapping

between bits{0, 1} and real numbers {−√E s ,+√E s }, where E s is the energy per symbol.This mapping is also known as binary phase-shift keying (BPSK) modulation or polarmapping

An MLD selects a coded sequence ¯ vthat maximizes Equation (5.21) By taking the

log-arithm of Equation (5.21), the following can be shown For the BSC, an MLD is equivalent

to choosing the code sequence that minimizes the Hamming distance

102 BINARY CONVOLUTIONAL CODESthat is minimized by the coded sequence selected by the MLD In this section, a BSC with

crossover error probability p is considered The AWGN channel is covered in Chapter 7.

5.5.2 The Viterbi algorithm

Let S i (k) denote a state in the trellis at stage i Each state S i (k) in the trellis is assigned a

state metric, or simply a metric, M(S i (k) ) , and a path in the trellis, ¯ y (k) A key observation

in applying the Viterbi algorithm is:

With i being the time, most likely paths per state ¯ y i (k) (the ones closest to the

received sequence) will eventually coincide at some time i −
.

In his paper, Viterbi (1967) indicates that the value of
for memory-m rate-1/2 binary convolutional codes should be
> 5m The VD operates within a range of L received

n -tuples (output bits per state transition) known as the decoding depth The value of L must be such that L >
.

In the following text, the Viterbi algorithm applied to a memory-m rate-1/n binary

convolutional code is described and its operation illustrated via a simple example Someadditional notation is needed: Let

¯

v [i] = (v0[i]v1[i] v n−1[i])

denote the coded bits in a branch (state transition), and let

¯r[i] = (r0[i]r1[i] r n−1[i])

denote the output of the channel

Basic decoding steps

Initialization

Set i= 0 Set metrics and paths

M(S (k)0 ) = 0, y¯(k)0 = () (empty).

The specific way in which the initialization of the paths is performed is irrelevant,

as shown later For the sake of clarity of presentation of the algorithm, it is assumed

that the paths are represented as lists that are initialized to the empty list.

1 Branch metric computation

At stage i, compute the partial branch metrics

BM i (b) = d H ( ¯r[i], ¯ v [i]), (5.26)

b=
n−1

=0v
[i]2 n −1−
, associated with the n outputs ¯ v [i] of every branch (or state transition) and the n received bits ¯r[i].

BINARY CONVOLUTIONAL CODES 103

Branch

metric

generator

Add, compareand select

Update pathsand metrics

r

_

u

~

Figure 5.11 Block diagram of a Viterbi decoder

2 Add, compare and select (ACS)

For each state S i (k) , k = 0, 1, , 2 m− 1, and corresponding pair of incoming

branches from two precursor states S (k1)

i−1 and S i (k−12), the algorithm compares the

extended branch metrics M(S (k1)

3 Path memory update

For each state S i (k) , k = 0, 1, , 2 m − 1, update the survivor paths ¯y (k)as follows,with the output of the winning branch ¯v k j , j ∈ {1, 2},

¯

y i (k) = ( ¯y (k j )

4 Decode symbols

If i > L, then output as the estimated coded sequence ¯ y (k i −L) , where k is the index of

the state S (k) with the smallest metric Set i = i + 1 and go to decoding step 1.

It should be stressed that this is not the only way to implement the Viterbi algorithm The

procedure in the preceding text can be considered a classical algorithm This is shown in

Fig 5.11 There are alternative implementations that, depending on the particular structure

of the underlying convolutional encoder, may offer advantages (see, e.g., Fossorier and Lin(2000)) In addition, in the last step of the algorithm, symbol decoding can be applied toinformation bits directly This is the form usually employed in the software implementations

of VDs that are available on the ECC web site In hardware implementations, a method

based on a traceback memory is favored that estimates the original information sequence,

indirectly, on the basis of state transitions This technique is discussed later in the chapter

Example 5.5.1 Consider again the memory-2 rate-1/2 convolutional encoder with

gener-ators (7, 5) Note that d f = 5 for this code This example shows how a single error can

be corrected Suppose that ¯ v = (11, 01, 01, 00, 10, 11) is transmitted over a BSC and that

¯r = (10, 01, 01, 00, 10, 11) is received (one error in the second position) The operation of

the VD is illustrated in Figures 5.12 to 5.17 The evolution of the metric values with respect

to the decoding stages is shown in the following table:

104 BINARY CONVOLUTIONAL CODES

tech-Path metric initialization

The VD can operate in the same mode from the start (i= 0) The survivor paths can have

arbitrary values, without affecting the decoder’s performance The first L decoded bits are

Transmitted

01 01

M(S ) = min { M(S ) + BM , M(S ) + BM }(0)0 (0)1 (1)0 (3)1

Update metric M(S ) = 1(0)1 (0)1

1 (0) (0) 1

BINARY CONVOLUTIONAL CODES 105

00 11 11 00 10 01 01 10

0 1

01

10

11

01 00

106 BINARY CONVOLUTIONAL CODES

01

10

11

01 00

01

10

11

00 00

Figure 5.16 VD operation for Example 5.5.1, at i= 5

BINARY CONVOLUTIONAL CODES 107

Figure 5.17 VD operation for Example 5.5.1, at i= 6

therefore random and give no information For this reason, the value of L contributes to the decoding delay and is also known as the decoding depth Moreover, provided that L is large enough (L 
, where
> 5m for rate-1/2 binary codes), the decoded bit can either

output from the path with the lowest metric or always output from the zero state path ( ¯y ( 0)).The latter method is easier to implement and does not result in loss of performance Theprograms on the ECC web site that implement MLD using the Viterbi algorithm work inthis fashion

Also note that in Example 5.5.1 the branch labels (output) were stored in the survivorpaths This was done in order to facilitate understanding of the algorithm In a practical

implementation, however, it is the corresponding information bits that are stored This is

discussed in the following text, in connection with path memory management

Synchronization

Branch symbols must be properly aligned with the received symbols Any misalignment

can be detected by monitoring the value of a random variable associated with the VD

Two commonly used synchronization variables are (1) path metric growth, and (2) channel

BER estimates The statistics of these variables give an indication of abnormal decodingbehavior

Assume that the received sequence is not properly received, that is, the n-bit branch

labels ¯v [i] in the decoder are not properly aligned, or synchronized, with the received sequence ¯r[i].

Example 5.5.2 Figure 5.18 shows an example for a rate-1/2 in which the received sequence

¯r is not synchronized with the reference coded sequence ¯ v.

108 BINARY CONVOLUTIONAL CODES

In other words, not all the bits in the received subsequence ¯r[i] belong to the same trellis

stage in the decoder In this case, the two events that may occur are (1) the path metricsare close to each other and grow rapidly and (2) the estimated channel BER approaches

1/2 Figure 5.19 shows the block diagram of a VD and a BER monitor.

A synchronization stage needs to be added, external to the decoder itself, whose function

is to advance the reference sequence ¯v in the decoder until the statistics return to normal

This can be done by skipping received symbols (a maximum of n− 1 times) until the chronization variables indicate normal decoding behavior This is indicated in Figure 5.18

syn-of Example 5.5.2 for the case syn-of a rate-1/2 convolutional code.

Metric normalization

As the VD operates continuously, the path metrics will grow proportional to the length onthe received sequence To avoid overflow or saturation (depending on the number represen-tation used), the metrics need to be normalized There are basically two methods of doingthis Both rely on the following two properties of the Viterbi algorithm:

1 The MLD path selection depends only on the metric differences.

2 The metric differences are bounded

BINARY CONVOLUTIONAL CODES 109

is compared to a threshold T at each decoding stage If Mmin> T , then T is subtracted

from all the metrics Clearly, this does not affect the selection process because themetric differences remain the same This is a method that can be easily implemented

in software on a generic processor

• Modular arithmetic method:

The metrics are computed modulo N , so that they lie within the range [0, N− 1],

where N = 2max and max is the maximum difference in survivor path metrics

Obviously, max depends on the range of values received from the channel Fromthe two properties of the Viterbi algorithm, it can be shown that the same MLD path

is selected by the VD when computing path metrics with modular arithmetic In

par-ticular, it is possible to use two’s complement arithmetic7in such a way that overflowcan occur but it does not affect the selection process For details, see Hekstra (1989)

and Onyszchuk et al (1993) This method is favored in hardware implementations

of VDs

Path memory management

In a VD, survivor paths and their metrics need to be stored and updated In a continuous

operation mode, while updating the survivor paths at stage i, earlier portions of the survivor paths merge with high probability at stage i − L, where L is the decoding depth The

estimated information bits are taken from the (single) portion of the merged paths at stage

i − L There are different techniques to extract the information bits Two of the most

common are (1) register exchange and (2) traceback memory

• Register exchange:

This method is the easiest to implement in software All the survivor paths areupdated at each iteration of the Viterbi algorithm Therefore, the information bits can

be read directly from the survivor paths However, if this technique is implemented

in hardware, the decoding speed would be low because of the excessive number oftimes the path memory is read and written To simplify control flow instructions, a

circular pointer of length L can be used With a circular pointer, at decoding stage

i , the position (i − L) in memory (to output the decoded bit) is equal to the position

(i + 1) modulo L.

• Traceback memory:

This technique is favored in implementations in hardware The survivor paths are

composed of decision values, which indicate state transitions in order to trace back the survivor paths and reconstruct a sequences of states in reverse order.

7 Arithmetic using the additive group {−2m−1,1− 2m−1, ,2m−1− 1} of m-bit integers (Hekstra 1989).

110 BINARY CONVOLUTIONAL CODES

The traceback memory can be organized as a rectangular array, with rows indexed

by k, for all the trellis states S i (k) , k = 0, 1, , 2 m − 1 At decoding stage i, for each trellis state S i (j ), 0≤ j ≤ 2 m − 1, the traceback memory (or TB RAM) is written, with the rightmost bit of the previous state S i (b−1j ) ,
∈ {1, 2} associated with the winning

branch

The traceback method trades off memory for decoding speed, since it writes only

one bit per state per decoding stage, instead of L bits per state per decoding stage,

as in the register exchange method The information bits are decoded by readingthe state transitions in reverse order with an encoder replica (or looking up a statetransition table) More memory (number of columns if organized in a rectangulararray) is required for continuous operation because information bits are read out(decoded)and new decision values written simultaneously

Example 5.5.3 Continuing with Example 5.5.1, using the traceback technique, at the end

of the i = 6 received pair of bits from the channel, the traceback memory would have the

contents shown in Table 5.2.

The traceback memory is read, starting from the last bit (e.g., use a “last in, first out”),

i = 6 (in general T = L) The row address is given by the state with the best metric This

is state S ( 0) in the example The transition bit b6 (in general, b L ) is read To read the next transition bit b5, the row address (ROW) at i = 5 (i = L − 1) is obtained by shifting the

address k at i = 6 (i = L) and appending the previous decision bit b6 (b L ) This can be stated in the following C language instruction:

ROW[j] = ((ROW[j+1] << 1) && MASK) ^ TB_RAM[ROW[j+1]][j+1];

For high-speed continuous VD operation with the traceback method, the tracebackmemory must be partitioned into several blocks In this way, while one block is being

written with decisions at the current stage i, another block is read (decoded) at a time

i − L, L >
, and another (possibly more than one) block for intermediate stages is used

for performing traceback tracing This memory partitioning improves speed but increases

the latency (or decoding delay) of the decoder (Boo et al 1997; Collins 1992).

Table 5.2 Tracing back the path that ended in

BINARY CONVOLUTIONAL CODES 111

ACS

For memory-m rate-1/n binary convolutional codes, the basic trellis element is a butterfly,

as shown in Figure 5.20 The ACS operation is implemented using this structure over 2m−1

pairs, that is, j = 0, 1, 2, , 2 m−1− 1 Therefore, the ACS operation can be done either

serially (a loop on j in software) or in parallel, with 2 m−1 ACS units, one per butterfly.

If the code is antipodal, then the generators of the code have one unit in the first and last positions In this case, the labels of the branches incident to a state S ( 2j ) are the same as

those incident to state S ( 2j+1) in a butterfly Moreover, the label of a branch incident to a

state S ( 2j ) is equal to the complement of the label of the other branch.8 Using these facts, aclever technique (Fossorier and Lin 2000) based on branch metric differences was proposed

Figure 5.21 Simulation and bound on the bit error probability of a memory-2 rate-1/2convolutional code Binary transmission over an AWGN channel with hard decisions

8The complement of a bit a is 1 + a mod 2.