Broadband Circuits for Optical Fiber Communication phần 6 potx

The three-stage amplifier in [27] uses this topology for the second and third stage.. This differential stage is part of a four-stage AGC amplifier, which has a bandwidth of 18 GHz and i

Fig 6.40 MESFET/HFET implementation of a single-ended gain stage based on [27]

The three-stage amplifier in [27] uses this topology for the second and third stage

The first stage is realized as a common-gate stage, which provides good input matching and low noise All stages in this single-ended design are AC coupled

Differentia/ Gain Stage Figure 6.41 shows a simplified schematic of the GaAs- FET VGA stage reported in [78] This differential stage is part of a four-stage AGC amplifier, which has a bandwidth of 18 GHz and is implemented in a 0.3-pm GaAs- HFET technology with enhancement- and depletion-mode devices

VDD

"IN

vss Fig 6.47 MESFET/HFET implementation of a differential VGA stage based on [78]

The differential input signals u ~ p and UIN are fed into a cascade of three source followers, M I , Mi, M2, Mi, M?, and M i , which provides impedance transformation and level shifting The source followers are implemented with enhancement-mode FETs, whereas the bias current sources are implemented with depletion-mode FETs The depletion-mode current sources are easier to bias, have lower crosstalk, and reduced supply voltage dependence The source followers M3 and Mi are enhanced

with an R-C coupling network to improve their speed (active source follower) The

operation of this network can be understood as follows: when the output of source follower M3 is rising, the bias current of M3 is momentarily reduced by means of the control voltage at node b, thus accelerating the transition This bias current reduction

MA CIRCUIT IMPLEMENTATIONS 215

is caused by the falling edge at the output of the source follower M;, which is coupled

to node b through the R-C high-pass network Similarly, M2 helps to accelerate the transitions of Mi The output signals from the source follower cascade drive the differential pair, M4 and M i FET M5 acts as a voltage-controlled resistor, which varies the amount of series feedback and thus the gain of this stage The source degeneration resistor Rs improves the linearity

The AGC amplifier in [78] consists of an input buffer, four DC-coupled stages of the type shown in Fig 6.41, and an output buffer A passive on-chip R-C-R feedback

network reduces the offset voltage (cf Section 6.3.3) The voltage VAGC is produced

by an on-chip AGC circuit

In [77], a similar differential stage has been reported, which is part of a three-stage

LA with a bandwidth of 29.3 GHz implemented in a 0.2-km GaAs-HFET technology

In contrast to Fig 6.41, this stage has no gain control, and therefore the degeneration devices Rs and A45 are removed and nodes s and s' are shorted together With this modification, the stage operates at its maximum gain Furthermore, this LA stage uses inductive loads for shunt peaking

6.4.2 BJT and HBT Technology

Cherry-Hooper Stage Figure 6.42 shows a simplified schematic of the bipo-

lar gain stage reported in [86] This stage is part of a three-stage LA, which has

a bandwidth of 45 GHz and is implemented in a 105-GHz SiGe-HI3T technology

This type of stage is known as a Cherry-Hooper stage and has been used success-

fully since 1963, when the original Cherry-Hooper paper [22] was published (e.g., see [38,96, 133, 143]).'*

Fig 6.42 BJT/HBT implementation of a gain stage based on the Cherry-Hooper architecture

(e.g., I861 )

'*The paper [22] describes the design of single-ended wideband amplifiers using an alternation of series-

and shunt-feedback stages Later, this concept was extended to a differential topology and to include

emitter followers (see Fig 6.42)

The input signals u p and VIN drive the differential pair Ql and Q; with the emitter degeneration resistors RE and RL We already discussed in Section 6.3.2 how emitter

degeneration (series feedback) reduces the input capacitance and thus speeds up the

BJT input pole The emitter capacitor CE can be used to introduce a zero, further improving the speed The load of the input differential pair is presented by the TIA

consisting of Q2, Q i , Q3, and Q; and the shunt-feedback resistors RF and R;

Note the similarity between this TIA and the one shown in Fig 5.31 We know from Section 6.3.2 how the low input impedance of the TIA speeds up the pole associated

with the nodes x and x’ and also reduces the Miller capacitance at the input of this stage Finally, the differential output signals are buffered with the emitter followers

Q4, Q i , Qs, and Q s These buffers reduce the loading, can provide some peaking,

and shift the DC voltage to a lower level such that the Ql and Q; of the next stage can operate at a higher VCE, which improves their speed

The degenerated input differential pair has a transconductance of about TR RE

(more precisely, I / [ R E + l/gml]), whereas the TIA has a transresistance of about

RF (assuming the gain of Q2 and Q; is much larger than one) The product of these

two quantities, A = R F / R E (or A = RF/[RE + l/gml], to be more precise), is the voltage gain of the Cherry-Hooper stage Because this gain is given primarily by a resistor ratio, it is insensitive to process, temperature and supply voltage variations Note that the Cherry-Hooper stage can be viewed as a double stage combining a

transadmittance stage (TAS) with a transimpedance stage (TIS) Thus in a multistage

application we have an alternation between TAS and TIS It also has been observed that the large impedance mismatch between the TAS, TIS, and emitter followers contributes to the wide bandwidth of this architecture [22, 1451

In [38], a similar Cherry-Hooper stage has been reported, which is part of a three- stage LA with a bandwidth of 15 GHz implemented in a 47-GHzSiGe HBT tech- nology In contrast to Fig 6.42, this stage does not have the emitter degeneration

resistors RE and RL in the TAS, resulting in the increased stage gain A = g,l R F Furthermore, the collector resistors Rc and RL are each split into a series connection

of two resistors RCI-RCZ and RL1-RL2 with the bases of Q3 and Q i connecting to

the midpoints This modification provides a gain enhancement of 1 + Rc2/ Rcl with little impact on the bandwidth

In [ 1331, another form of the Cherry-Hooper stage has been reported, which is part of a three-stage LA with a bandwidth of 9 GHz implemented in a 0.4-pm BJT

technology In contrast to Fig 6.42, this stage uses a simplified TIA load without

the emitter followers Q3 and Q; In this case, the noninverted and inverted currents from the TAS and TIS, respectively, flow into the same collector resistors Rc and R(c,

possibly giving rise to a nonmonotonic DC transfer function To ensure monotonic behavior and proper limiting, it is recommended to make the TIS tail current, 12, twice as large as the TAS tail current, I I

Four-Quadrant Multiplier VGA Stages How can we control the gain of a Cherry-

Hooper stage for use in an AGC amplifier? Unfortunately, bipolar technologies don’t

offer voltage-controlled resistors that we could use to control RE or RF (cf Sec-

10 GHz and is implemented in a 22-GHz BJT technology

fig 6.43 BJT/HBT implementation of a four-quadrant multiplier VGA stage based on [98]

Nodes x and x’ connect to a TIA load as in Fig 6.42

b G C

fig 6.44 BJT/HBT implementation of a modified four-quadrant multiplier VGA stage based

on [98] Nodes x and x’ connect to a TIA load as in Fig 6.42

Figure 6.43 shows how the input differential pair can be turned into a four-quadrant multiplier that has the form of a Gilbert cell The TIA load is the same as that shown

in Fig 6.42 If the gain-control voltage VAGC is large, the output currents from the differential pair Ql and Q; are directly routed through Q A and Q> to the nodes x and

x’ producing a gain of approximately A = R F / R E , as in the original Cherry-Hooper

stage However, if VACC is reduced, the currents to the nodes x and x’ become a combination of the direct contributions through Q A and Q> and the crossed-over

contributions through QB and QL These two contributions partly cancel each other which results in a reduced gain In particular, for VACC = 0, the cancellation is

complete and the gain becomes zero (assuming the transistors QA, QX, QB, and Ql, are sized identically) Note that the gain control voltage for this stage always must be kept positive Should it drop below zero, the gain starts to increase again (and the data signal is inverted), which means that the negative-feedback AGC loop turns into a

positive-feedback loop, making the AGC unstable Also, note that the input dynamic range of this stage, just like that of the original Cherry-Hooper stage, is determined

by the voltage drop across the emitter degeneration resistors RE and Rk, and thus

is independent of the gain-control voltage VAGC This may be an issue at low gains where the input signals are largest

Figure 6.44 shows another approach to design a VGA stage with BJTs Compared with Fig 6.43, the input ports of this modified four-quadrant multiplier are used differently: the lower inputs are now used for the gain-control voltage, whereas the upper inputs are used for the input signal The maximum gain of approximately

A,,, = R F / R E I is obtained when all of the tail current is directed through QA into the differential pair Q 11 and Q;, If we reduce VAGC and divert some of the tail current through Q B into the other pair, Q12 and Qi2, the transconductance of the first pair drops, whereas the second pair contributes an inverted signal current to the

output As a result of these two mechanisms, the gain is reduced

In [98], the first stage uses the topology shown in Fig 6.43, the second stage uses the topology shown in Fig 6.44, and the third stage has a fixed gain The reason for using both types of VGA stages is that they can be made to have complementary characteristics Whereas the gain of the stage in Fig 6.43 drops with increasing input voltage, that of the stage in Fig 6.44 increases Whereas the bandwidth of the stage in Fig 6.43 shrinks with decreasing gain, that of the stage in Fig 6.44 can

be made to expand with the appropriate choice of R E ] , R L l , RE^, Rb2, C E ~ , and

c E 2 Thus, combining the two stages results in superior linearity (large u;:) and a gain-independent bandwidth In addition to the three gain stages, the AGC-amplifier chip in [98] also includes an input buffer, two output buffers (one to drive the decision circuit and one to drive the clock-recovery circuit), an offset compensation circuit, and a gain-control circuit

In [ 1141, similar VGA stages have been reported, which are part of a three- stage AGC amplifier with a bandwidth of 32.7 GHz implemented in a 92-GHz SiGe HBT technology

Two-Quadrant Multiplier VGA Stage Figure 6.45 shows a simplified schematic

of the bipolar VGA stage reported in [ 1781 This stage is part of a three-stage VGA for

a 20-Gb/s application and is implemented in a 60-GHz SiGe graded-base technology

In contrast to Fig 6.43, this stage is based on a two-quadrant multiplier The two

quadrants corresponding to VAGC < 0 are not needed; in fact, they must be avoided

to keep the control loop stable The stage shown in Fig 6.45 controls the gain by dumping a variable amount of signal current through Q B and Q’, into VCC Thus,

when the stage is completed with a TIA load as in Fig 6.42, the gain can be varied

in the range A = 0 to R F / R E A drawback of this topology is that the DC currents

MA CIRCUIT IMPLEMENTATIONS 219

Fig- 6.45 BJT/HE%T implementation of a two-quadrant multiplier VGA stage based on [ 1781 Nodes x and xf connect to a TIA load as in Fig 6.42

into the nodes x and xf are varying with the gain-control voltage, producing a variable

output common-mode voltage A bias stabilization circuit can be added to take care

of this problem

The VGA in [178] uses the topology shown in Fig 6.45, enhanced with a bias stabilization circuit and with R E = RL = CE = 0 for the first stage The second and third stages have a fixed gain This VGA is used to drive a decision circuit located

on the same chip

Selectable Gain Stage Figure 6.4.6 shows a simplified schematic of the bipolar

VGA stage reported in [37, 391 This stage is part of a three-stage AGC amplifier

with a bandwidth of 9 GHz and is implemented in a 50-GHz SiGe technology

Fig 6.46 BJT/HBT implementation of a selectable gain stage based on 137, 391 Nodes x

and x’ connect to the gain-control circuit (emitters of Q A , Q B and Q>* Qh) in Fig 6.43 or to the TIA load in Fig 6.42

In this approach, the input signals are applied simultaneously to two differential pairs, one with emitter degeneration resistors RE^, RL, and the other with RE^, RL2

The differential pair, Q A and Q B , acts as a switch that steers the tail current either

into the left or the right differential pair, depending on the binary value of the select signal The active pair together with the TIA load in Fig 6.42 determine the gain

to be either A = R F / R E I or R F I R E ~ This topology has the advantage that it has a wide input dynamic range when the lower gain is selected (large degeneration resistor), whereas it has a good noise figure when the higher gain is selected (small degeneration resistor)

The first stage of the AGC amplifier in [37,39] combines the selectable gain circuit

in Fig 6.46 with the the gain-control circuit ( Q A , QL, Q B , Qk) in Fig 6.43 The select input is used to choose the gain range, whereas the VAGC input is used to control the gain continuously within each range In the lower range (-7 dB to 7 dB), the maximum input voltage is 1.7V and the noise figure is 16dB, whereas in the upper range (7 dB to 20 dB), the maximum input voltage is 0.2 V and the noise figure improves to 12dB The second stage features a continuous gain control input only, and the third stage has a fixed gain The whole AGC amplifier is integrated with a CDR and DMUX on a single chip

Distributed Amplifier Figure 6.47 shows a simplified schematic of the bipolar distributed amplifier reported in [ 101 This single-ended amplifier has a bandwidth

of 74 GHz and is implemented in a 160-GHz InP-HBT technology

50.Q

k E (OV) I1

Fig 6.47 BJT/HBT implementation of a distributed amplifier based on [lo] Each of the four sections of the distributed amplifier is structured as a cascode circuit with Ql and Q2 The cascode technique lowers the input capacitance of each section by suppressing the (section dependent) Miller capacitance of Ql Further- more, it lowers the output conductance of each section, thus reducing the losses in the output transmission line The emitter-degeneration resistor of Q 1 increases the input resistance of each section, thus reducing the losses in the input transmission line Furthermore, the resistor improves the linearity and lowers the input capaci-

MA CIRCUIT IMPLEMENTATIONS 221

tance The input transmission line is formed by the transmission-line segments Z T S ~ , and the output transmission line is formed by the transmission-line segments 2 ~ ~ 2 ,

which are all realized as coplanar waveguides The transmission-line segments Z ~ s 3

provide a small amount of peaking An RF choke (RFC) can be used to shunt the back-termination resistor of the output transmission line, thus eliminating the DC voltage drop across this resistor

The circuit in Fig 6.47 also can be used as a TIA In this case, the photodetector

is connected directly to the input V I As in a low-impedance front-end, the detector current is converted first to a voltage by means of the 5042 input impedance, then this voltage is amplified by the distributed amplifier

6.4.3 CMOS Technology

Low-Voltage VGA Stage Figure 6.48 shows the schematic of the CMOS VGA

stage reported in [187] This stage is part of a four-stage AGC amplifier, which has

a bandwidth of 2 GHz and is implemented in a 0.15-wm, 2-V CMOS technology

v VAGC

"ON

v,

VOP

Fig- 6.48 CMOS implementation of a VGA stage based on [187]

The stage consists of the n-MOS differential pair M I and Mi and the p-MOS load

transistors M2 and M i Note that the p-MOS loads operate in the linear regime The gain is controlled with the p-MOS transistor M3, which presents a variable differential load resistance

In [187], the first three stages of the AGC amplifier have a fixed gain and are implemented as shown in Fig 6.48, but without the FET M3 The last stage has a variable gain and is implemented as shown in Fig 6.48 This AGC amplifier is part

of a single-chip receiver, which includes a TIA, a CDR, and a DMUX

VGA Stage with Replica Biasing Figure 6.49 shows a simplified schematic of the

CMOS VGA stage reported in [47] This stage is used in a six-stage VGA amplifier for a 48O-Mb/s application and is implemented in a 1.2-pm 5-V CMOS technology The gain of this stage is controlled by the variable p-MOS load transistors M2

and M;, which both operate in the linear regime The replica biasing circuit, on

the right-hand side, generates the gate voltage such that the (large-signal) drain-

Fig 6.49 CMOS implementation of a VGA stage based on [47]

source resistance of the replica M i and the loads M2 and M i all become equal to ( VDD - VAGC)/ZO Thus, a well-controlled (temperature- and process-independent) variable load resistance is created A potential drawback of varying the single-ended load resistance (as opposed to the differential load resistance, as in Fig 6.48) is that the common-mode output voltage varies with the gain; in fact, in Fig 6.49, we have

MA CIRCUIT IMPLEMENTATIONS 223

shown in Fig 5.19 The differential pair M2 and Mi provides the voltage gain and FETs MF and MI, constitute the active feedback Neglecting the effects of the load resistors and the FET's output conductances, the transimpedance of this TIA is l/&F The active-feedback TIA load and the bandwidth extension that can be achieved with

it was discussed in Section 6.3.2

In [3 11, the bandwidth of this stage is enhanced further by applying shunt peaking and negative Miller capacitances The LA chip also contains an input matching network with a T-coil and an offset cancellation circuit

Gain Stage with Active Inductors Figure 6.51 shows the schematic of the MOS

gain stage reported in [156] This circuit is used for the last three stages of a four- stage LA, which has a bandwidth of 3 GHz and is implemented in a 0.25-~m, 2.5-V CMOS technology

Charge Pump

Fig 6.57 CMOS implementation of a gain stage with active-inductor loads based on [156]

The differential pair M1 and M i is loaded by the active inductors consisting of

transistors M2 and Mi and resistors R and R' The active inductor and the bandwidth

extension that can be achieved with inductive loads was discussed in Section 6.3.2

To alleviate headroom problems in this low-voltage design, the bias voltage VBl J is

set to one n-MOS threshold voltage above VDD As shown in Fig 6.51, this bias

voltage easily can be generated on chip with a charge pump: a ring oscillator drives a capacitor-diode charge pump (Cl , C2, Dl , and D2), producing a voltage above VDD

This voltage is clamped to the desired value by M3 Oscillator ripples are filtered out with the low-pass network R3, Cz A welcome side effect of using active-inductor loads is that the low-frequency gain of the stage is set primarily by the transistor

geometry A = ,/-, which is insensitive to process, temperature, and supply voltage variations

In [ 1561, the active-inductor stages are combined with inverse scaling and buffering

to boost the bandwidth of the LA further

Common-Gate Stage with Offset Control Figure 6.52 shows a simplified

schematic of the common-gate CMOS stage reported in [156] This circuit, en- hanced with active-inductor loads, is used as the input stage of the four-stage LA mentioned above

Fig 6.52 CMOS implementation of a common-gate input stage based on [156]

The common-gate n-MOS transistors M I and Mi provide a low-impedance input, which can be made equal to 50 st with the appropriate choice of transistor dimensions and bias currents (constant-g, biasing) Apart from providing the input termination, the common-gate input transistors also provide an effective electrostatic discharge (ESD) protection Standard ESD networks are not suitable for high-speed inputs because they limit the signal bandwidth too much It therefore is advantageous to build the input stage such that the parasitic MOS diodes act as the ESD protection:

in Fig 6.52, there are three parasitic diodes at each input, two to ground and one to

VDD Finally, the input stage also features the p-MOS differential pair M2 and M;,

which permits to control the offset voltage with Vosp - V O ~ N A feedback circuit,

as shown in Fig 6.29, can be used to cancel the offset voltage automatically

Tables 6.1 and 6.2 summarize the main parameters of some commercially available

LA and AGC amplifiers The numbers have been taken from data sheets of the manu- facturer that were available at the time of writing For up-to-date product information, please contact the manufacturer directly For single-ended amplifiers, the gain value,

tabulated under A , is followed by “(s).” For differential amplifiers, the dcperentiul

gain value is given followed by “(d).” The input overload voltage, LJ:;!, as well as the maximum input voltage for linear operation, L ( are specified as peak-to-peak values The noise-figure values, tabulated under F , are measured single endedly, that

is, the source noise is that of a single 5042 resistor (cf Section 6.2.3)

We note that all listed 2.5- and 10-Gb/s parts have a differential topology The two single-ended 40-Gb/s parts are implemented as distributed amplifiers Comparing parts for different bit rates, we find that, in general, higher-speed parts consume quite a bit more power The reader may wonder about the difference between the two similar Nortel parts: the AC03 requires a 5.2-V power supply, whereas the AClO runs from the lower 3.3-V supply, which also explains the difference in power dissipation

reach this goal (cf Appendix D)

The following papers on high-speed MAS were published recently:

0 In SiGe-HBT technology, a 31-GHz and a 32.7-GHz AGC amplifier as well

as a 4O-Gb/s and a 49-GHz LA have been reported in [87], [114], [150], and [86], respectively

0 In GaAs-HFET technology, a 18-GHz AGC amplifier as well as a 27.7-GHz and a 29.3-GHz LA have been reported in [78], [78], and [77], respectively

0 In GaAs-HBT technology, a 26-GHz VGA has been reported in [153]

0 In InP-HBT technology, a 30-GHz LA and a 74-GHz distributed amplifier have been reported in [96] and [ 101, respectively

It can be seen that, in terms of speed, the LAs have an advantage over the more complex AGC amplifiers

Lower Cost Another area of research is focusing on the design of high-

performance MAS in low-cost, mainstream technologies For the reasons already

given in Section 5.5, digital CMOS is of particular interest

For example, a SONET-compliant 10-Gb/s LA has been implemented in a low-cost

“modular BiCMOS” technology [70] A 2.4-Gb/s, 0.15-pm CMOS AGC amplifier has been reported in [ 1871, and a SONET-compliant 2.5-Gb/s, 0.25-pm CMOS LA has been demonstrated in [156] 10-Gb/s, 0.18-pm CMOS LAs have been reported

in [ 1281 and [31] The promise of a CMOS main amplifier is that it can be integrated with the CDR, DMUX, and the digital frame processing on single CMOS chip to provide a cost-effective and compact low-power receiver solution

SUMMARY 227 6.7 SUMMARY

Two types of main amplifiers (MA) can be distinguished:

0 The limiting amplifier (LA), which generally is faster, dissipates less power,

and is easier to design However, its strong nonlinearity for large input signals restricts its field of application

.0 The automatic gain control (AGC) amplifier, which is linear over a wide range

of input amplitudes and thus is suitable for receivers with an equalizer, decision- point steering, a soft-decision decoder, and so forth However, its more complex design generally results in a lower bandwidth and higher power dissipation The main specifications of the MA are as follows:

0 The voltage gain, which must be large enough to provide enough voltage swing for the subsequent clock and data recovery (CDR) circuit

0 The bandwidth, which must be large enough to prevent the MA from introduc-

ing a noticeable amount of intersymbol interference (ISI)

0 The group-delay variation, which must be kept small to minimize jitter and other signal distortions

0 The noise figure, which must be low enough to avoid a noticeable degradation

of the receiver sensitivity

0 The MA sensitivity, which must be much smaller than the minimum input

signal into the MA to avoid a noticeable degradation of the receiver sensitivity

0 The input overload voltage, which must be large enough to avoid harmful pulse-width distortion and jitter for the maximum input signal into the MA

0 The input offset voltage, which must be much smaller than the minimum input signal into the MA to avoid a harmful slice-level error (especially in LAs)

0 The low-frequency.cutoff, which must be low enough to avoid a noticeable baseline wander This is particularly important if signals with long runs of zeros and ones (i.e., scrambled data signals) are used

0 The AM-to-PM conversion, which must be low enough to limit the generation

of jitter in the presence of spurious amplitude modulation

Virtually all MAS are structured as multistage amplifiers because this topology

permits the realization of very high gain-bandwidth products (>>fr) Furthermore, broadband techniques such as series feedback, emitter peaking, cascoding, tran- simpedance load (with shunt feedbaclk or active feedback), negative Miller capac- itance, buffering, scaling, inductive load (e.g., shunt peaking), inductive interstage network, and distributed amplifier are applied to the gain stages to improve their bandwidth and to shape their rolloff characteristics

Most MAS include an offset compensation circuit to reduce the random offset

voltage below a critical value Some MAS also permit the introduction of a controlled

amount of offset to adjust the slice level This feature is useful to optimize the bit- error rate (BER) performance in the presence of unequal noise distributions for zeros and ones AGC amplifiers consist of a variable-gain amplifier (VGA), an amplitude detector, and a feedback loop that controls the gain such that the output amplitude remains constant Some MAS feature a loss-of-signal detector to detect faults such

as a cut fiber Burst-mode amplifiers have special provisions, such as fast decision threshold control, to deal with a bursty signal of varying amplitude and no DC balance MAS have been implemented in a wide variety of technologies including metal- semiconductor FET (MESFET), heterostructure FET (HFET), BJT, heterojunction bipolar transistor (HBT), BiCMOS, and CMOS The Cherry-Hooper architecture, which combines series-feedback and shunt-feedback stages, often is chosen for BJT and HBT implementations

Currently, researchers are working on 40-Gb/s MAS and beyond, as well as MAS

in low-cost technoIogies such as CMOS

6.8 PROBLEMS

6.1 Power Penalty What is the optical sensitivity of a receiver that consists of a

photodetector with the responsivity R, a TIA with the input-referred rms noise current iT+,A and the transimpedance R T , an MA with the gain A, and a DEC with the sensitivity VDTA?

6.2 Noise Figure (a) Write the noise-figure expression “total output noise power”

divided by “fraction of the output noise power due to the thermal noise of the source resistance” in mathematical form Show that this expression is identical

to “input SNR’ divided by “output SNR,” where the input SNR is based on the thermal noise of the source resistance only In both cases, take the noise power in the frequency band from f l to f2 (b) Show that for f 2 - f l + 0, the noise figure expression from Problem 6.2(a) becomes the spot noise figure

in Eq (6.14) (c) Show that for f 1 = 0, f 2 -+ 00, the noise figure expression from Problem 6.2(a) becomes the wideband noise figure in Eq (6.15)

6.3 AC-Coupling Capacitor An amplifier with the output resistance Ro = 50 !2 is

AC coupled with capacitor C to another amplifier with the same input resistance

Ro = 50 52 (a) What is the low-frequency cutoff, f L F , caused by the capacitor C? (b) What is the power penalty caused by a finite capacitor C? (c) How

large should the capacitor C be made for a 2.5-Gb/s and 10-Gb/s system?

6.4 Bandwidth Shrinkage and GBW Extension (a) Calculate the 3-dB band-

width of a cascade of n identical second-order Butterworth stages Normalize

this bandwidth to that of a single stage to obtain the bandwidth shrinkage

as a function of n (b) Given a desired gain, Atot, and bandwidth, B w o t ,

for the n-stage amplifier above, calculate the GBW necessary for each stage

Miller Effect A capacitor C is connected between an input terminal with

voltage 211 and a node with the voltage A vI (a) Assuming A is frequency independent, calculate the effective input capacitance, CI (b) Assuming A has the frequency dependence A ( s ) = Ao/( 1 + sT), calculate the input admit- tance, Y ( s )

fT Doubler It has been suggested that a simple differential pair is an f~ doubler

because its differential input capacitance is &/2 (neglecting c b c ) , whereas its differential transconductance, g, = A(ic.p - ~ c , N ) / A ( v B E , P - V B E , N ) , is the same as that of a single transistor What is wrong with this argument?

Series Feedback (a) Calculate the voltage transfer function, A ( s ) = V,/ V, ,

for the MOSFET stage with series feedback shown in Fig 6.53(a) Use a simplified FET model with CXd = gmb = go = R, = 0; assume CJh is

included in Cs and c& is included in C L Derive expressions for the poles

and zeros of A ( s ) (b) What vallue for CS results in a single-pole response?

(c) Calculate the input admittance, Y ( s ) , for the above circuit assuming the

same simplified FET model Derive expressions for the poles and zeros of

Y ( s ) (d) What are the conditions for a purely capacitive input?

Regulated Cascode (a) Calculate the input admittance, Y I (s), of the MOS- FET regulated-cascode circuit shown in Fig 6.53(b) Use a simplified (DC) FET model with all capacitances set to zero and gmb = 0; also assume that

the feedback amplifier has the frequency-independent gain A F Simplify the

resulting expression for RD << I / g , and (1 A F I + 1) g, /go >> 1 (b) Cal- culate the output admittance, YO (s), of the regulated-cascode circuit using the same FET and amplifier models as before Simplify the resulting expression

for (IAFI + 1 ) g m / g , >> 1 and (IAFI + 1) gmRS >> 1 (c) Discuss the

advantage of the regulated cascode over the simple cascode (d) How do these

Fig 6.54 Circuits for Problems 6.9 and 6.10: (a) common-source stage, (b) stage with TIA

load, and (c) split stage

results change if the FET is replaced by a bipolar transistor? Compared with the FET, the bipolar transistor has a nonzero base-emitter conductance equal

to g m / B

6.9 Shunt-Feedback TIA Load (a) Calculate the bandwidth BW of the simple

MOSFET common-source stage shown in Fig 6.54(a), assuming R, = go = 0 and a total capacitance at the output node equal to CL (b) Calculate the bandwidth BW' of the MOSFET stage with shunt-feedback TIA load shown

in Fig 6.54(b), assuming the same characteristics for the MOSFET, the same total capacitance CL at the drain of the MOSFET, the same overall stage gain as before, a single-pole feedback amplifier with gain A F and bandwidth BWF, and

a Butterworth response for the overall stage Hint: use the result in Eq (5.19)

for the shunt-feedback TIA load (c) What is the relationship between BW and BW'? Assume that the gain-bandwidth product of the simple common-source

stage and the feedback amplifier in the TIA load are the same

6.10 Stage Splitting (a) Calculate the bandwidth BW' of the MOSFET amplifier

with two identical stages shown in Fig 6.54(c), assuming the same character-

istics for the MOSFET, the same load capacitance C L , the same overall stage

gain as in Problem 6.9(a) (b) What is the bandwidth extension, BW'/BW, as a

result of splitting the simple common-source stage of Problem 6.9(a) in two?

6.11 Active-Feedback TIA Load Show that the bandwidth extension given in

Eq (6.55) also holds for a gain stage with active-feedback TIA load Hint: use

the results from Problem 5.13 for the active-feedback TIA load

6.12 Negative Capacitance (a) Calculate the differential admittance Y (s) = 1 /2

(I,) -Z,,)/(V,,- V,) oftheMOSFETNIC withcapacitor C showninFip 6.55(a)

(cf Appendix B.2 for the definition of the differential admittance) Use a

simplified FET model with Csh = Cdh = C,, = gmh = g,, = R, = 0 and assume ideal current sources (b) What is the maximum frequency for which

Y (s) represents a negative capacitance and how large is this capacitance?

6.13 Source Follower and Capacitance-Transformation Ratio (a) Calculate the

voltage transfer function A(s) for the MOSFET source follower shown in Fig 6.55(b) Use a simplified PET model with R, = 0; assume Csb is in- cluded in CL The current source is ideal Derive expressions for the poles and zeros of A ( s ) What is the bandwidth, BWB, of this buffer? (b) Calcu- late the input admittance Y (s) for the above circuit assuming the same FET and current-source model Derive expressions for the poles and zeros of Y (s)

What is the low-frequency input capacitance, C I , of this buffer? (c) Calculate

thecapacitance-transformation ratio^ = (CL -CLO)/(CI + C I ~ ) ofthis buffer, where CLO is the self-loading caLpacitance of the buffer, which includes Csb,

and CI 1 is the wiring capacitance to the buffer input Express K as a function

of fT/BWB, where f~ = g,/[2n(CgS + C,d)] Evaluate this function for

A ( 0 ) = 0.8, C,d = 0.3C,,, CLO = 1.7Cg,, and C I ~ = 0.2C,,

6.14 Common-Source Buffer and Capacitance-Transformation Ratio (a) Cal-

culate the voltage transfer function A ( s ) for the MOSFET common-source

buffer shown in Fig 6.55(c) Use a simplified FET model with R, = 0; as-

sume Cdh is included in CL The resistor is ideal Derive expressions for the

poles and zeros of A ( s ) What is the bandwidth, BWB, of this buffer? (b) Cal-

culate the input admittance Y (s) for the above circuit assuming the same FET and resistor model Derive expressions for the poles and zeros of Y (s) What

is the low-frequency input capacitance, C I , of this buffer? (c) Calculate the

capacitance-transformation ratio K = (CL - CLO)/(CI + CI1) of this buffer, where CLO is the self-loading capacitance of the buffer, which includes c d h , and CI 1 is the wiring capacitance to the buffer input Express K as a function

of fT/BWB, where fT = g,/[2n(Cx, + C,d)] Evaluate this function for

A(0) = -0.8, C,d = 0.3C,,, CLQ = O.6CRs, and c11 = 0.2c,,

6.15 Amplifier with Scaled Stages A scalable first-order stage with scale param- eter ( has the input capacitance 6 C I O , output capacitance ( COO, transcon- ductance g,O, and load resistance Ro/C Its power dissipation is 6 PO,

and its input-referred mean-square noise voltage is - u$/c; note that its gain,

A s = gmoRg, and unloaded bandwidth, BWs = 1/(2nRoCoo), are indepen-

dent of the scale parameter t A multistage amplifier with the input capacitance

CI driving the load capacitance C L < C I is assembled from n such stages (a) Assuming identically scaled stages, = 61 for i = 1 n, what are the amplifier's bandwidth, power dissipation, and input-referred noise? (b) As- suming uniformly down-scaled stages, & + I = 4, / K for i = 1 n - 1, what are the optimum scale factor K , the amplifier's bandwidth, power dissipation, and input-referred noise? (c) How do these two designs compare given the values n = 4, CI/CL = 16, CIo/Coo = 1.5, and gmoRo = 2.5?

6.16 Shunt Peaking (a) Calculate the voltage transfer function A ( s ) for the MOS-

FET stage with shunt peaking shown in Fig 6.19(b) Use a simplified FET model with Cgd = go = R, = 0; assume c& is included in the load capaci-

tance C L Derive expressions for the poles and zeros of A @ ) (b) A numerical analysis shows that peaking occurs when the poles are conjugate complex with

Q > 0.644 For what peaking inductor value is the frequency response maxi- mally flat?

6.17 Active Inductor (a) Calculate the impedance Z(s) for the MOSFET active inductor shown in Fig 6.22(b) Use a simplified FET model with Csh = R, = 0 (Csh can be accounted for by CL in a shunt-peaking application) Derive

expressions for the dominant pole and the zero of Z(s); assume that the poles are spaced far apart (b) In which frequency range is Z(s) inductive? (c) What

is the condition for the impedance to be inductive at any frequency? (d) What

is the inductance value assuming the poles are far away from the zero?

6.18 Bode Theorem Bode's network theorem about physically realizable passive

impedances in the finite frequency range 0 to B W can be written as [ 161

MA inputs, VIP and V I N , are driven from the voltage source us through two series

resistors Ro = 50 S2; the MA core and the error amplifier have the frequency independent gains A and A 1, respectively; and the offset compensation input of

the DDA has the reduced gain $A Derive expressions for the poles and zeros

of Atot(s) (b) What is the LF-cutoff frequency for C + 00 and C1 + co?

7

Optical Transmitters

Having completed our discussion of the optical receiver, we now turn to the trans- mitter We start with a brief discussion of the transmitter specifications Then, we focus on the devices used for the electrical-to-optical conversion, namely, the laser and the modulator Their characteristics are important for the driver design as well

as the transmission system design

Types of Modulation Figure 7.1 illustrates two alternative ways to generate a modulated optical signal In Fig 7.1 (a), the laser is turned on and off by modulating its current; this method is known as direct modulation In Fig 7.l(b), the laser is on at all times, a so-called continuous wave (CW) laser, and the light beam is modulated with a kind of optoelectronic shutter, a so-called modulator; this method is known as external modulation Direct modulation has the advantages of simplicity, compactness, and

cost effectiveness, whereas external modulation can produce higher-quality optical pulses, permitting extended reach and higher bit rates

Direct as well as external modulation can be used to produce non-return-to-zero ( N U ) or return-to-zero (RZ) modulated optical signals However, to produce very high-speed RZ-modulated signals, a cascade of two optical modulators, known as a

tandem modulator, frequently is used In this arrangement, the first optical modulator

modulates the light from the CW laser with an NRZ signal and the second modulator, which is driven by a clock signal, coniverts the NRZ signal to an RZ signal in the optical domain

233

7.1 TRANSMllTER SPECIFICATIONS

In the following, we look at two important specifications of the optical transmitter: (i) the spectral linewidth and (ii) the extinction ratio The values that can be achieved for these parameters depends on whether direct or external modulation is used

Spectral Linewidth For a perfectly monochromatic light source followed by a per-

fect intensity modulator, the optical spectrum of the modulated output signal looks like that of an amplitude-modulated (AM) transmitter: a carrier and two sidebands corresponding to the spectrum of the baseband signal In the case of an NRZ modu- lation, the spectrum looks as shown in Fig 7.l(b) The 3-dB bandwidth of one NRZ sideband is about half the bit rate, B / 2 , and thus the full bandwidth, which covers both sidebands, is about equal to the bit rate.’ If we convert this bandwidth or frequency linewidth to the commonly used wavelength linewidth, we get

where h is the wavelength and c is the speed of light in vacuum (c = 3 lo8 m/s) For

example, at 10 Gb/s, the frequency linewidth is about I0 GHz, corresponding to a wavelength linewidth of 0.08nm for A = 1.55 pm In practice, it is difficult to build a transmitter with a linewidth as narrow as this; only some types of external modulators can come close to this ideal Optical pulses that do have this narrow spectrum are

known as transform limited pulses

For most transmitters, the modulation process not only changes the light’s am- plitude but also its phase or frequency This unwanted frequency modulation (FM)

is called chirp and causes the spectral linewidth to broaden as shown in Fig 7.l(a)

The directly modulated laser is a good example for a transmitter with a significant

‘The full bandwidth measured null-to-null is 2B

where (Y is known as the chirp parameter or linewidth enhancement factor [44, 731

With the typical value (Y x 4 for a directly modulated laser [a], the linewidth of

a 10-Gb/s transmitter broadens to about 41 GHz or 0.33 nm External modulators also exhibit a small amount of chirp, but virtually all types of modulators can provide

la I i 1 and some achieve la! I < 0.1, thus approaching the transform limited case [a]

So far, we assumed that the unmodulated source is perfectly monochromatic (zero

linewidth), or at least that the unmodulated linewidth is much smaller than those given

in Eqs (7.1) and (7.2) Single-longitudinal mode (SLM) lasers, which we discuss in Section 7.2, can provide such a source However, many sources have a much larger linewidth For example, a Fabry-Perol: laser has a typical unmodulated linewidth of

about 3 nm, a light-emitting diode (LED) has an even wider linewidth in the range of

50 to 60 nm For such wide-linewidth >iowces, the spectrum of the modulation signal

and the chirp mostly are irrelevant, and the transmitter linewidth is simply given by

where Ahs is the linewidth of the unmodulated source

We know from Chapter 2 that optical pulses with a wide linewidth tend to spread out quickly in a dispersive medium such as a single-mode fiber (SMF) operated at a wavelength of 1.55 pm The power penalty due to this pulse spreading is known as

the dispersion penalty Data sheets of lasers and modulators frequently specify this

dispersion penalty for a given amount of fiber dispersion For example, a 2.5-Gb/s, 1.55-pm laser may have a dispersion penalty of 1 dB given a fiber dispersion of 2,00Ops/nm We know from Section 2.2 that a fiber dispersion of 2,00Ops/nm

corresponds to about 120km of SMF With Eqs (2.6) and (2.8), we further can

estimate that the linewidth of this laser transmitter must be around 0.1 nm

We analyze the impact of direct and external modulation on the maximum bit rate and transmission distance in Section 7.4 But as a rough guide, we can say that telecommunication systems at 10 Gb/s and more generally use external modulation, 2.5-Gb/s systems use direct or externla1 modulation depending on the fiber length, and systems less than 2.5 Gb/s generally use direct modulation Short-reach data

communication links operating at the 1.3-pm wavelength, where dispersion in an SMF is small, use direct modulation even at 10Gb/s

The narrow linewidth obtained with external modulation not only reduces the dispersion penalty, but also permits a closer channel spacing in a dense wavelength division multiplexing (DWDM) system To avoid crosstalk, the channels must be spaced further apart than the linewidth of each channel Current DWDM systems have a channel spacing of 200 or 100 GHz with a trend toward 50 GHz

Extinction Ratio Optical transmitters, no matter if directly or externally modu-

lated do not shut off completely when a zero is transmitted This undesired effect is

quantified by the extinction ratio (ER), which is defined as follows2:

p1 ER= ,

where PO is the optical power emitted for a zero and P1 the power for a one Thus, an

ideal transmitter would have an infinite ER The ER usually is expressed in dBs using the conversion rule 10 log ER Typically, ERs for directly modulated lasers range from 9 to 14 dB, whereas ERs for externally modulated lasers can exceed 15 dB [29] SONETKDH transmitters typically are required to have an ER in the range of 8.2 to

10 dB, depending on the application

It doesn't come as a surprise that a finite ER causes a power penalty Figure 7.2(a) and (b) illustrates how decreasing the ER reduces the optical signal swing, P1 -

PO, even if the average power = ( P I + P0)/2 is kept constant To restore the

original signal swing, we have to increase the average transmitted power, as shown

in Fig 7.2(c) The power penalty PP due to a finite

Fjg, 7.2 Eye diagram (a) with infinite ER, (b) with ER = 5, and (c) with ER = 5 and

increased average power (1.5 x ) to restore the original signal swing

In deriving Eq (7.5), it was assumed that the ER does not affect the amount of noise

at the receiver This is the case for unamplified p-i-n receivers; however, in systems with an avalanche photodetector (APD) or optical amplifiers, the noise increases when the ER is reduced: (i) the nonzero value of PO adds noise on the zeros and (ii) the increase in power to compensate for the finite ER adds noise on the zeros and ones,

necessitating an even larger power increase to compensate for this noise As a result

*In the literature, ER sometimes is defined as PI /Po and sometimes a P ( ) / P l in this book, we follow [ 1881 and use the former definition, which results in an ER that is larger than one